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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 5, OCTOBER 1986

Regular

Correspondence

Accurate

Simulation of Power Dissipation in VLSI Circuits

SUNG Abstract VLSI

—Power

design

important

MO KANG,

dissipation

and

its

increases.

Therefore

highfy

desirable

while circuits

SPICE. circuit.

Tfte

power

drawn from

for CMOS

Power tion.

techniques

significantly

power

“power

disturbing

the

power

technology

chip

useful will

circuit

circuits

introduce

Fig. average large source.

value

1 shows power capacitor

an

in

meeting cost,

power

circuit

other

where

and

circuit,

dissipa-

T

yet accuwithout

is inserted

in

series

with

monitoring

the

In

supply

impedance.

enough

When

not

to introduce

the series impedance

voltage

across the voltage

current

as

any

this voltage

is small,

significant

0.25 mA 0.00 mA

XIO-8

the case

corresponding

the calculated

CMOS

to the machine

cycle of the

value of lDD depends

strongly

on CX

I. For a large value of C’, the corresponding

T needs to be increased

period

proportionally

not even be detectable.

since otherwise

The results shown in Table I

that this scheme is not usable. methods

power

for

estimating

For example,

dissipation

the power the frequently

consumption

are

used formula

for

is [3]

a

cTv&f

P=

v~~

series

the average

where

CT is the total

change

in a machine

The application a moderate estimate tion

I ~D =

0.027 x10-8 O.m

based on formulas.

the steady-state

VX can be used to calculate

1.OF

in Table

V, (T) would

It appears to be a viable means so long as the capacitance is large

T

mA

0.58

10 F

is the period

as shown

METHODS for

O.35OX1O-8

and k’. (0) is set to zero,

In reality,

simulators

a simple

circuits.

IDD =

is

indicate

scheme

integrated

C, V.(T)

“;11

OIF

behavior.

often-mentioned

dissipation

I wrm THE METER IN FIG. 1 in Fig, 4 and T= 600 nS,)

at com-

as a subcircuit

IN CONVENTIONAL

is shown

c,

Others DRAWBACKS

OBTAINED

circuit

designers

device

with

CURRLNTS

measured

pay

circuit

force in the

VLSI

while area,

(The

of the major

circuits

to simulate

that can be inserted

the origirtaf

One

a technology,

are analyzed

[2]. This paper

meter”

TABLE AVERAGk

by the

designers

in CMOS

dissipation

as speed,

circuits

limited

to become a major dissipation

it is quite

while

II.

Load

to the

and apply

dissipation.

technology

such

related

[1], circuit

of technology

the power

Therefore

such as SPICE rate

results are shown

is closely

dissipation

than that in other

minimize objectives

accurately

c

reads the average

has been often

the power

is that lower

reliability. tion

circuits

speed. Even after choosing to

+7-+ Cif%it

+ T)

= Vin(t

RC

design, and also the scale of integra-

to the choice

to reduce

VLSI

Vin(t)

the power

and a parallel

C-xvr(7-)/T.

integrated

reasons for the CMOS

need

for simulating

source

Device

Input

such as

INTRODUCTION

circuit

maximum

attention

design

is

Vx(o)=o

Fig. 1. An often-proposed scheme for measuring the average current drawn from the voltage source VDD. The idea is to calculate the average power by

dissipation,in

acceptable

parable

method

dissipation

T-. –J

L

more in

Vxl

lx*

in

of devices

simulators

source. Simulation

Since the scale of integration

current

of power

across the capacitor

the supply voltage

of technology,

special

increasingly

with circuit

current

factors

circuits.

I.

choice

simulation

an accurate

voltage

becomes

as the number

are simnlated

use of a dependent

steady-state

It

dissipation

accurate

This paper presents with

choice.

the pbwer

VLSI

I#+i

SENIOR MEMBER, IEEE

is one of the most important

technology

to rednce

dissipation

889

Cx~(T) T

of this formula

of state-changing

f

mainly

Therefore,

to the accurate integrated

to disturb

Not

with

$01.00

01986

regions

along with

of power

to

identificacapacibackgate

the above formula

monitoring

NONINVASIVE

the magnitude supply

IEEE

not only

cannot

dissipation

in

circuits.

in the simulation,

the power

of even

logic gates, but also their effective in practice,

supply

circuits

because it is difficult

of CT requires

biasing

III.

by the logic

cycle frequency,

to real integrated

and drain

effects.

affected

is the machine

tances in the gate regions

large-scale

0018 -9200/86/1000-0889

capacitance

size is not practical

CT. The estimation

be applied

Manuscript received October 22, 1985. This work was supported in part by the Semiconductor Research Corporation (SRC) under Grant RSCH 84-06. 049-5. The author is with the Coordinated Science Laboratory and the Department of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign, Urbana, IL 61801. IEEE Log Number 8609887.

effective cycle and

POWER METERS

of current

the subcircuit

should

drawn

from

the power

to be inserted

not have any loading

effect.

in series Such a

[EEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 5, OCTOBER 1986

890

idd(t)~

‘D

[;

:F!z3?jvy ------------

{

9

+“ Device

Device

Input

Vin (t) = Vin (t + T)

Fig,

A

2,

subcircuit

R C circuit

allel

Input

c Load T

a current-controlled

measuring

the

average

current power

source

and

consumption

by

a parreading

Fig. 3. A sub circuit with a voltage-controlled current source and a parallel RC circuit for measuring the average power consumption by reading VV(T),

subcircuit

A.

c Losd

*T

*

k’,(T).

dent

or Circuit

Vin(t) = Vi”(t + T)

Cir%uit

with

for

(”)’”

can be realized

by using

a current-controlled

source or a voltage-controlled

Power

Meter

with

a Current-

dependent Controlled

depen-

Current

RC

parallel

Some earlier versions

circuit.

current-controlled

source [4]. Source

2 shows a subcircuit that is composed of a currentcontrolled current source and a parallel l?C circuit. The shunt to provide a dc path. resistor R, is required in the simulation

of SPICE

can be used instead.

The series resistance

that

in i~d is negligible.

the disturbance

be modified

did not allow

sources. In such cases, the subcircuit rx should

in Fig. 3

be small

For this circuit,

so

(2) can

as

Fig.

The insertion

of O-V independent

the intrinsic of

the

in the circuit.

idd

dependent

loading.

With

thevoltage

source,

a proper

choice

average

power

as follows.

consumption

source does not chahge

due to theunidirectionality

the subcircuit

across thecapacitor

derived

voltage Also,

(7)

does not

of the current

when any R&

gain parameter~,

C,, inthesubcircuit P,vg.r The proper

impose will

value

>> T,

att=T

read the (8)

of /3 can be

First we note that which

suggests that

(1)

From

thesubcircuit

in Fig. 2

(2)

or

(9) where

i,, =iJ,,

and V,(0)=O.

Solving

for ~Y in(2)

yields IV.

(3) To compare where

a = I/I?

then

at

(4)

t= T -FL

e-”(’–’)idd).

of

) d.

(5)

[5]

inverters.

F’avg when

v..;

=

wiring

VDDCJ.

(6)

Power

Meter

with

a Voltage-Controlled

Current

VDDCV f/rK,

or

Source

Fig. 3 shows a subcircuit for monitoring the average power consumption with a voltage-controlled current source and a

composed total

we will use C,,f

fan-out done

the

gates with

the

drawn

and logic

drawn power

or

CPf/rx

to

effective only

of

capacitance wiring

are tied subcircuit

the

logic

same

in Fig.

states

type.

involved

nodes. 3 at

in

It

in individual

capacitances

in

is nontrivial

to

switching.

is specified The

and

gate is the sttm of l-pF

gate-to-substrate the

capacitance

to output

NOR gates,

V~~ source is the

the

CL of each

the totaf gates

NAND,

from

to switch

capacitance

capacitance

simulation,

of multiple-input current

required

loading

fan-outing

calculate cuit

B.

VDDCY f

The

The

three /3=

the results

modification should not cause any confusion of ~ or gm, is simply scaled down by VD~; Le.,

sum of currents gates.

~y (T)=

with

the average current. The power dissipation is simply VDD~ (T) tinder this arrangement. Fig. 4 shows a CMOS polycell

circuit

suggests that

approaches

monitor

.)

This

CIRCUITS

This

the value

instead V,(T)

the results of proposed

consumption. since

~T

TO CMOS

shown in Table I, we chose to monitor the average current from the power supply voltage instkad of the average

,,C,,. If we choose Rp and Cy such that R ,,C,, >> T

APPLICATION

SPICE

and

In

cir-

the three

simulation

was

T = 95° C, VDD= 4.5 V with

R,, = 10120, C, = 1 pF, and T= 600 nS. This choice satisfies the R ,,CP>> T. Three different values of rx, 10– 5, 10 – 6,

inequality

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO, 5, OCTOBER 1986

891

v ~~ = 4.5

volts

idd(t) + r- I -a I Current I lL Meter ! - l-- A

V,n(t CL

t

Fig. 4.

ACMOSpolycell

circuit used tosimtdate from

TABLE AVERAGE

the average

I2x1o–4

OBTAINED IN FIG.

WITH

L

IDD = v;T)

10-7 Q 10-6 Q

O 124 mA 0.124 mA 0.124 mA

Q

drawn

I

I

I

I

I

I 1.0

I 2.0

I 3.0

I 4.0

I 5.0

3

(The measured cmw,t M shown in Fig. 4 and T= 6(XJ nS.)

10-5

currerrt

source.

11

CURRENT THF METER

the voltage

?0 –

8-

6-

4–

! 2–

1

1 VIN

3,6

2.6

1,6

0.6

o

–2 –

-4 0.0

Time

Fig, 6, SPICE output waveforms for idd and ~,. Here the steady-state value VV( T ) represents the average current drawn from the voltage source over the period 7’.

VLSI

5.

Input

voltage

waveform

used

in

SPICE

simulation

of

circuit

circuit

X1O–7

Time (s)

Fig.

choosing

Fig,

tion

10– 7 0,

average

were

current

AS

remains

which

indicates

shows

the input

corresponding

tried.

that

in

constant

Table

11,

throughout

the proposed

voltage

outputs

shown

approach

waveform

the

the

measured

three

is reliable.

cases, Fig.

used in the simulation.

5

The

are shown in Fig. 6 for both instantaneous

source

renders

accurate

end

source,

of the

results

circuit

so long

the

method

the

a current-controlled

average

by reading

period

while

By properly

gn, in the case with power

through

a

consump-

the voltage

T. This method

as demonstrated

The proposed

paper

any interference such as SPICE.

conductance

can be measured

at the

electric

transfer

current

of circuits

this paper.

causing

a simulator

gain /3 in the case with

or the

capacitor

this

without with

the transfer

current

4 circuit,

model

is simulated

voltage-controlled

and

6.0 X1O–7

(s)

across

the

is simple

yet

an example

in

can be used in any electronic

or

as the inequality

constraint

mentioned

in

is satisfied.

zdd ( ~) ~d Y(t). Note that as expected ~,(t) reaches its steadystate value at t = T, which is the average current drawn from the

VDD source

over

the period

T= 600 nS.

REFE32f3NcEs [1]

V. In this paper, average

power

we presented consumption

current-controlled junction power

with

a simple

measurement.

RC circuit This

circuit

in integrated

or voltage-controlled a parallel

[2]

REMARKS

CONCLUDING

circuits,

dependent

yielded

subcircuit

for measuring

a simple

The

the

use of

source in consubcircuit

can be inserted

into

for any

W. Keyes, “Physical limits in semiconductor electronics,” Electronics; The Continuing Evolution. Washington, DC: AAAS, 1977, pp. 197-202. L. W, Nagel and D, 0, Pederson, “Simulation program with integrated circuit emphasis (SPICE),” in Proc. 16th Jfidwe$t Symp. Circuit Theory, R.

Apr.

[3]

D:

1973. A.

Hodges

tegrated

[4]

L. 0.

Chua

Englewood

[5]

S. M. Circuits

and

Circuits. and Cliffs,

Kang, and

“A

H.

G.

New P.-M. NJ: design

Systems,

Jackson,

York: Lin,

Computer-Aided

Prentice-Hall, of CMOS vol.

A rtalysis

McGraw-Hill, 1975, polycells

and

Design

1983,

ch. 3.

A na[ysis

of Digital

of Electronic

In-

Circuits.

ch, 2. for

LSI

circuits,”

CAS-28, no. 8, pp. 838-843,

Aug.

IEEE 1981.

Tram.