Active Transient Voltage Compensator Design for VR

Active Transient Voltage Compensator Design for VR Load Line Improvement Shamala A. Chickamenahalli Intel Corporation, Chandler AZ 5000, W. Chandler Blvd, Chandler, AZ85226 [email protected] Edward Stanford Intel Corporation, Dupont, WA [email protected]

Xiangcheng Wang, Hua Zhou, Majd Batarseh and Issa Batarseh Department of Electrical and Computer Engineering University of Central Florida Orlando, Florida 32816, USA [email protected]

more capacitors for the increasing slew rate. Furthermore, increased motherboard capacitors have limited effect on the voltage spike suppression due to the existence of resistance and inductance of PCB traces and socket [1-2]. The effective way to reduce the second voltage spike is to reduce the delay times in controller, especially in large signal transients. There are three main delay times in VRs: LC filter, compensation network and the IC propagation delay times. How to reduce those delay times in a simple way is a challenge and needs a tradeoff between fast transient response and high efficiency. The barrier of output VR current slew rate is determined by the VR equivalent inductance and its applied voltage. High switching frequency operation helps to reduce its LC filter for high bandwidth but it introduces higher switching loss. Recently many other efforts have been put into the VRs to improve the transient response by reducing the output impedance or load line [4] [8-17]. The concepts of current and voltage compensations are widely used in the harmonic compensation in power system and inverters [5-6], and this current compensation concept can also be used in VR to improve the transient response [8-11], but it has large conduction or switching losses in the extra converter which is used for current compensations. Active transient voltage compensator (ATVC) has been proposed to improve the VR transient response by reducing second voltage spikes [4]. It is composed of two switches and one transformer and in parallel between the VR output and load as shown in Fig.1. It injects high slew rate current in step-up load and recovers energy in step-down load.

Abstract: Active transient voltage compensator (ATVC), only engaged in transient periods, was proposed to improve the VR load line and main VR can be optimized design with better efficiency which mainly handles the dc current. ATVC has reduced switching and conduction losses in extra converter due to the introduction of a transformer and it can also reduce the number of VR capacitors for required voltage tolerance. The compensation network delay times deteriorate the second voltage spike at high slew rate transient, especially in the high bandwidth controller. In this paper, combination of linear and adaptive nonlinear control is used to reduce the delay times of the compensation network. Finally a prototype of 3-Ch VR + ATVC was carried out on Intel motherboard and detailed experimental results are given.

I.INTRODUCTION With the advancement of CPU, great challenges have been posed on the power delivery architecture, such as the requirements: low output voltage down to less than 1V, high current up to 120A, high slew rate up to 10A/ns, high power density and good thermal performance. Some of these requirements contradict each other, such as the high slew rate and high efficiency. High slew rate needs small filter inductance, but this leads to high current ripple which increases the conduction and switching losses. Interleaved multiphase VR can reduce the input and output current ripples and has good distributed thermal capability which is commonly used in desktop and laptop computer system to power the CPU [1]. In high slew transient, the VR current cannot catch up with load current immediately, the unbalanced current will be provided by filter and decoupling capacitors thus two transient voltage spikes occur in the VR output voltage [2]. VR10.1 [1] lists the specification for voltage tolerance in transient. The first voltage spike is determined by ESR, ESL of capacitors, and the second voltage spike is mainly determined by the energy stored in filter inductors related to the close-loop bandwidth [2-3]. In order to reduce the transient voltage spikes, typically a large number of capacitors are mounted close to the processor on the motherboard for lower ESRs, ESLs. Unfortunately, the available space on the motherboard makes it difficult to add

Vo2

Tr

Vo1

Rskt

* * Qa1 CPU

V1

Vin

Cp C0 Qa2

-------------------------------------------------This work is funded by Intel Corp.

0-7803-9547-6/06/$20.00 ©2006 IEEE.

Rtrace

Fig.1 Interleaved multiphase VRs with parallel ATVC

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ATVC engaged only in transient periods injects voltage source instead of current source by the introduction of a transformer. It handles only 1/(1+N) of the current handled by current injection methods and it injects current slew rate 1+N times higher than that of current injection methods [8-11], which result in high efficiency in ATVC. Furthermore, the main VR can operate in relatively low switching frequency and large filter inductance for better efficiency. Table 1 shows the current slew rate comparisons. High switching frequency operation, such as 1.5MHz, can reduce the filter inductance for high slew rate current, but it introduces high switching losses and thermal issues. From the table, it’s clear that ATVC can inject higher current slew in step-up and in step-down load, it’s suitable for high slew rate load applications. Fig.2 shows the VR load line composition [1] with AVP or droop-compensation control, which is composed of ac load line and dc load line. The dc load line is set and programmable in design which is related to the accuracy of current sensing, and the ac load line is determined by the delay time in actual controller. Reduced the delay time and widened the bandwidth lead to smaller ac load line. ∆VAC1 is the ideal maximum ac voltage improvement in step up load and ∆VAC2 is the ideal maximum ac voltage improvement in step down load. Delay times exist in actual controller and it is impossible to eliminate them because of the requirement of enough phase and gain margins for converter stability, resulting in the deterioration of the transient voltage spikes. Longer compensation network delay time and higher transient voltage spike. At the same time the small signal model used for compensation network design cannot explain large signal transient effectively, especially for duty cycle saturation in transient periods. This paper presents the combination of linear and active nonlinear control to reduce delay times.

∆VAC2

VO ∆VDC

∆VAC1

Fig.2 VR load line compositions a). 3 Ch VR, 12Vin, 1Vo, Lf=0.45uH, fs=300kHz b). 3 Ch VR, 12Vin, 1Vo, Lf=0.1uH, fs=1.5MHz c). VR same as (a), ATVC: V1=5V, N=2,fs=1.5MHz, LLK=25nH Current slew rate in stepup load

Current slew rate in stepdown load

0.073A/ns (VR)

0.0067A/ns (VR)

a) b)

0.33A/ns (VR)

0.03A/ns (VR)

c)

0.073A/ns (VR) 0.48A/ns (ATVC)

0.0067A/ns (VR) 0.12A/ns (ATVC)

Table.1 Current slew rate comparison RLK1

LLK1

RLK2

LLK2

1

*

* N

LM

Fig.3 Equivalent ATVC transformer model

II. ATVC TRANSFORMER DESIGN ATVC adopts a transformer to inject voltage source and the filter inductance contains the transformer leakage inductance, parasitic inductance of PCB traces, vias and socket connections. It is very important to optimize the transformer design in ATVC because the injected current slew rate is determined by the leakage inductance of the ATVC transformer and the turn-ratio of transformer determines the power rating and power loss of ATVC [4]. 3D Maxell transformer simulation is one way to optimize the design based on the tradeoff between the current slew rate and the efficiency. Fig.3 shows the equivalent ATVC transformer model, which includes RLK2, LLK2 in primary side and RLK1, LLK1 in secondary side. LLK1 and LLK2 determine the current slew rate, and RLK1 and RLK2 determine the transformer conduction loss, also they will decrease the injected voltage source. Table 2 shows the 3D simulation results based on a 4-layer planar transformer of ER11 magnetic core. Small turn-ratio transformer has smaller leakage inductance and resistance, but increases the current rating and power loss in ATVC.

Table.2 3D Maxell simulation

results VREF2

VO

VREF1

td2 td1 a) Constant reference VREF2

VO VREF1

td1’

td2’

b) Adaptive nonlinear reference

Fig.4 Concept of adaptive nonlinear control

60

R C1

Vo

CC1

CC2

R FB

RC

I2 IO

CC

I1 o

400

PWM +

IO

Filter

Gm

VR22

EAO

EA

VO

VREF1

VR12

o

R1 Cm1 + VR12

VNL

One V NL1 D1 RNL1 Shot

EAO

310

+ VR22

One Shot

o

VNL2 R 2

1 Q1

Duty o

320

Fig.5 Combination of linear and adaptive nonlinear control

III.

VNL2

300

R NL2 Cm2

VNL1 o

t12 t22

t32 t42

time

Fig.6 Key analysis waveforms in linear and adaptive nonlinear control

Delay times are very important to transient response improvement, especially in high bandwidth control loop. How to reduce the delay times in ATVC controller is the big challenge to optimize the transient response improvement. This paper proposes the combination of linear and adaptive nonlinear control. Fig.4 (b) shows the concept of adaptive nonlinear control by introducing the load current or inductor current signal to the delay time by minimizing the hysteretic comparator two input voltages difference: the feedback voltage and reference voltage, and so the delay time can be further reduced both in step up and in step down load. Fig.5 and 6 show the implementation circuit and key waveforms with combination of linear and adaptive nonlinear control. Adaptive nonlinear control is carried out in dash block 400, which is composed of a filter, a trans-conductance amplifier Gm and a controlled current source. The comparator reference voltages VR12 in step up load and VR22 in step down load in adaptive nonlinear control are shown in dash line in Fig.6, which are dependent on the load current. With the introduction of current signal, the delay time of nonlinear control can be t22-t12 in step up load and t42-t32 in step down load because the voltage difference of comparator is reduced largely, only 5~15mV difference between the output voltage VO and the reference voltage VR12, VR22 compared with the constant reference in Fig.4 (a). So the combination of linear and adaptive nonlinear control further improves transient response by reducing the control delay times and it also simplifies the linear compensation network design. Moreover, no stability problem exists in adaptive nonlinear control because only one nonlinear pulse signal is injected via one-shot circuit. Furthermore nonlinear signal can be injected either in linear control loop or combined with the PWM output in linear controller by logic circuit. Expected maximum ac voltage improvement is ∆VAC1 – (5~15mV) in step up and ∆VAC2 – (5~15mV) in step down.

ATVC CONTROLLER DESIGN

Transient or large signal response is mainly determined by the LC filter and the error amplifier (EA) dv/dt. Fast transient response requires high performance EA, especially dv/dt. Nonlinear control has very short delay time due to none existence of compensation network that mainly determines by IC propagation delay time, such as in hysteretic control that is widely used in literatures [7-18]. The basic operation principle of nonlinear control is that the controller is activated when the output voltage is less than constant voltage reference VREF1 in step up load or higher than the reference voltage VREF2 in step down load. Because it does not sense the load current or its changes directly, delay times appear in the nonlinear controller: td1 and td2 that vary with the slew rate of load current shown in Fig.4 (a). Higher slew rate transient current leads to smaller delay time because of faster voltage change, which makes it difficult to improve the transient response within such short duration. The main disadvantage of hysteretic control is the sensitivity to noise and variable frequency control. The tight tolerance requirements for the interleaved multiphase VR output voltage makes it even more difficult to separate the output voltage change from the noise caused by a load current transient. And the switching frequency of hysteretic control strongly depends on ESR, ESL, delay time in its control and the hysteretic window Hyst when the ESL meets some conditions [21]. If it does not, the voltage drop across the ESL during switching period will exceed the hysteretic window, and then switching frequency becomes too high and uncontrollable. It becomes even worse in small filter inductance and high slew rate current applications due to the existence of PCB traces and socket inductances except for the ESL of capacitors. Another shortcoming of hysteretic control is variable switching frequency, which makes it difficult to design the filter inductor and suppress the EMI.

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IV. EXPERIMENTAL VERIFICATION

85.00%

Experiments have been carried out to verify the combination of linear and active nonlinear control on 2-Ch VRM. Parallel ATVC with the combination of linear and adaptive nonlinear control is also implemented on the Intel motherboard to improve transient responses. Fig.7 shows that the tested efficiency of ATVC in CCM is up to 84% at 1.5MHz and it also achieves over 250 kHz crossover frequency with 50o phase margin with 47nH filter inductance. Parallel ATVC with different control methods: linear, nonlinear and adaptive nonlinear control is tested on 2-Ch VRM [17], which operates at 300 kHz switching frequency with 2.2uH filter inductance; the parallel ATVC operates in 1.5MHz and its planar transformer turn ratio is 2:1 with ER11 magnetic core and it is in parallel with the PCB traces between the output and load. Fig.8 shows the tested transient waveforms in 2-Ch VRM with 0~25A step load. There are 2.4us delay times in ATVC linear control combined with nonlinear control and 280mV voltage spike in step up load. With the introduction of adaptive nonlinear control, the delay time is largely shortened to 0.2us leading to only 188mV voltage spike. Table 3 shows the experimental load line improvement in 2-Ch VRM with parallel ATVC. With combination of linear and adaptive nonlinear control, transient response has been further improved by reducing response time both in step up and step down loads. Parallel ATVC with combination of linear and adaptive nonlinear control has also been implemented for the second voltage spike suppression on the Intel desktop motherboard D915Gev with socket LGA775 and VR10.1 [1]: 2-Ch VR with 4*560uF/6.3V (2 less than specification) in north side and 1-Ch VR with 4*560uF/6.3V in east side, 450nH filter inductance per channel as shown in Fig.1. Fig.8 shows the bottom view of prototype on Intel motherboard. ATVC is directly parallelled with the motherboard via 3 connection points: Vo1, Vo2 and gnd. The ATVC control has two controllers: step up and step down controller with different reference voltages: VR12 and VR22. ATVC transformer turnratio is 1:1. There is no change or modification on VRs. VTT tool [18-19] is used to simulate CPU current at different programmable current and current slew rate: 5~50A, 5~80A and 5~100A @ 180A/us, 250A/us, 550A and 10A/ns. Fig. 9 shows the 3-Ch VR base transient waveforms without AVTC @5~50A, 550A/us. The under-voltage spike is 79.2mV (1.76mΩ LL) and the over-voltage spike is 75.2mV (1.67mΩ LL). It has 1.2mΩ dc LL and around 0.5mΩ ac LL. As previous discussion, the expected maximum ac load line improvement (10mV difference) is around 0.36mΩ in step up and 0.31mΩ in step down load. Also it’s clear that the total load line is very difficult to be constant by AVP or droop compensation control because of the existence of delay times in VR controller and the impact of the current sensing inaccuracy. The ac load line caused by delay times increases the total load line a lot.

84.00% 83.00% 82.00% 81.00% 80.00% 79.00% 78.00%

5A

10A

15A

20A

25A

30A

1.56MHz

81.22%

84.06%

84.11%

83.68%

81.39%

80.43%

1.93MHz

79.46%

81.12%

83.05%

82.24%

80.12%

79.21%

Fig.7 Tested ATVC efficiency

Fig.8 Combination of linear and nonlinear control in 2-Ch VRM Load line in 2-Ch VR PT8124A with ATVC@ 0~25A, 100A/us dc load line VRM baseline

ac load line Step up

Response time

Step down

Response time

120mV 4.8mΩ

340mV 13.6mΩ

N/A

350mV 14mΩ

N/A

VRM ATVC+NL&L

120mV 4.8mΩ

280mV 11.2mΩ

2.4us

292mV 11.68mΩ

2.4us

VRM ATVC+ Adaptive NL&L

120mV 4.8mΩ

188mV 7.52mΩ

0.2us

228mV 9.12mΩ

0.2us

Table.3 Tested results in 2-Ch VRM with ATVC

Connection points 98mm

gnd Vo2 55mm

20*20mm2

Vo1

Fig.8 Bottom view of prototype on the Intel MB

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VR10.1, VTT Tools, Vo=1.5V, RLL-DC=1.2mΩ, ATVC for 2nd voltage spike RLL-AC improvement ATVC: ER11, 1:1, 5Vin, 1.5MHz, 2nd voltage spike RLL-AC experimental test results 5~50A Slew rate

Step up load

Step down load

5A~80A

5A~100A

Base

ATVC

∆(+)

Base

ATVC

∆(+)

Base

ATVC

∆(+)

180A/us

1.69mΩ

1.42mΩ

15.8%

1.73mΩ

1.41mΩ

18.4%

1.75mΩ

1.45mΩ

16.8%

250A/us

1.71mΩ

1.44mΩ

15.6%

1.77mΩ

1.44mΩ

18.7%

1.79mΩ

1.42mΩ

16.4%

550A/us

1.76mΩ

1.48mΩ

16.1%

1.81mΩ

1.53mΩ

15.4%

1.83mΩ

1.56mΩ

14.9%

10A/ns

1.8mΩ

1.51mΩ

15.8%

1.84mΩ

1.59mΩ

13.7%

1.87mΩ

1.64mΩ

12.3%

180A/us

1.6mΩ

1.39mΩ

13.3%

1.64mΩ

1.41mΩ

13.8%

1.63mΩ

1.46mΩ

10.3%

250A/us

1.65mΩ

1.37mΩ

17.2%

1.68mΩ

1.45mΩ

13.5%

1.68mΩ

1.52mΩ

9.5%

550A/us

1.67mΩ

1.41mΩ

15%

1.71mΩ

1.52mΩ

11%

1.74mΩ

1.58mΩ

9.7%

10A/ns

1.69mΩ

1.48mΩ

12.6%

1.75mΩ

1.57mΩ

10%

1.77mΩ

1.65mΩ

6.8%

Table 1 Experimental results of socket transient load line of VR with ATVC Fig.10 shows the VR transient waveforms with ATVC in step up @ 5~50A, 550A/us. Vga1 and Vga2 are the averaged driver signal of Qa1 and Qa2. The tested under-voltage is reduced to 66.4mV (1.48mΩ LL) and over-voltage spike is reduced to 63.2mV (1.41mΩ LL), about 16.1% load line improvement in step up and 15% load line improvement in step down load. The tested ac load line improvement referred to the expected ac load line reduction (0.36 mΩ and 0.31 mΩ) is about 78% in step up and 84% in step down load. Fig.11 shows the VR improved transient waveforms by using ATVC @ 5~80A, 250A/us load. It has only 108mV (1.44mΩ LL) in step up and 109mV (1.45mΩ LL) in step down load. The base load in same load tranisent is 1.77mΩ in step up and 1.68mΩ in step down load, about 18.7% load line improvement in step up and 13.5% in step down load. For the ac load line referred to the expected maximum as load line improvement is 82% in step up and 95.8% in step down load. Table 3 shows the VR transient load line [1] (measured between pin: AN4 and AN3 in LGA775) improvement of the second voltage spike with different step current loads at different slew rates. When the slew rate exceeds 800A/us, the first voltage spike dominates while ATVC cannot compensate the first voltage spike. In step up load with different step current, the improvements of socket transient load line are all above 12%. In step down load with different step current, the improvements are between 6.8% with 17.8%. Generally, the improvement of transient load line in step up load is better than that in step down load because higher injected current slew rate occurs in step up than that in step down load because of the characteristics of the buck converter. Also ATVC achieves better improvement under slower slew rate load because the IC propagation delay time has stronger impact on the delay time reduction in higher slew rate cases.

Io

Io 79.2mV

Vo

Vo

75.2mV

Fig.9 Baseline waveforms w/o ATVC @ 5~50A, 550A/us Io

Io Vo

66.4mV 63.2mV

Vo

Vga2

Vga1

Fig.10 Transient waveforms w/ ATVC @ 5~50A, 550A/us Io

Vo

Vga1

Io 108mV Vo

109mV

Vga2

Fig.11 Transient waveforms w/ ATVC @ 5~80A, 250A/us

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V. CONCLUSIONS

[13] Hirokawa, M, et.al, “Improvement of transient response in high-current output DC-DC converters”, IEEE PESC2003, pp705-710 [14] Jieli, L. et.al, “Using coupling inductors to enhance transient performance of multi-phase buck converters”, IEEE APEC2004, pp.1289-1293 [15] K.Yao, et.al, “Design considerations for VRM transient response based on the output impedance”, APEC2002, pp.14-20 [16] Y.Ren, et.al, “Two-stage approach for 12V VR”, IEEE APEC2004 [17] “30A 12V-input programmable integrated switching regulator PT8120 series”, Texas Instruments application datasheets [18] www.casdesystems.com/lga775.html [19] Shamala A. Chickamenahalli, et.al, “Microprocessor platform impedance characterization using VTT tools” IEEE-APEC2005 [20] “Designing fast response synchronous buck regulators using the TPS5210,” Texas Instruments application report

Parallel ATVC experimental prototypes have been carried out to improve the VR load line by introducing the combination of linear and adaptive nonlinear control. Some features are: 1. Parallel ATVC is easy to implement; 2. ATVC injects high slew rate current in step-up and recovers energy in step-down, 3. ATVC is only engaged in transient periods, 4. High bandwidth can be obtained in ATVC, 5. Combination of linear and active nonlinear control largely can reduce the delay times in controller, and can also help in reducing transient voltage spikes or ac load line, 6. ATVC also can reduce the number of bulk capacitors on the Intel motherboard. REFERENCES [1] “Voltage regulator-Down (VRD) 10.1 Design Guide for Desktop LGA775 Socket” document number: 302356003, webs: http://www.intel.com/design/Pentium4 /documentation.htm [2] Rais Miftakhutdinov, “Analysis and optimization of synchronous buck converter at high slew rate current transient”, IEEE Power Electronics Specialists Conference, June 2000, pp.714-721 [3] Shamala A. Chickamenahalli, et, al, “Effect of target impedance and control loop design on VRM stability”, APEC2002, pp.196-202 [4] X. Wang, Issa Batarseh, “active transient voltage compensator for VRM transient improvement at high current slew rate load”, IEEE-APEC2005, pp: 1430-1435 [5] Hirofumi Akgi, et.al, “ A new power line conditioner for harmonic compensation in power systems”, IEEE Trans. on Power Delivery, Vol.10, pp:1570-1576, 1995 [6] Juan W. Dixon, et.al, “A series active power filter based on sinusoidal current-controlled voltage-source inverter”, IEEE Trans. on Industry Electronics, Vol.44, pp:612-621, 1997 [7] X. Wang, ect, “A novel control for two-stage dc/dc converter with fast dynamic response”, IEEE-PESC2004, pp:43-48 [8] X. Wang, ect, “Transient response improvement in isolated dc/dc converter with current injection circuit”, IEEE-APEC2005,pp:706-710 [9] Barrado, A, et,al, “New DC/DC converter with low output voltage and fast response”, IEEE APEC 2003, pp.432-437. [10] Amoroso, L, et.al, “Single shot transient suppressor (SSTS) for high current slew rate microprocessor”, IEEE APEC 1999, pp.284-288 [11] Consoli, A, et.al, “A new VRM topology for next generation microprocessors”, PESC2001, pp.339-344. [12] Song Qu, “Modelling and design considerations of V2 controlled buck regulator”, PESC2001, pp.507-513

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