Adiabatic 5T SRAM by Mamatha Samson, Satyam Mandavalli
in International Symposium on Electronic System Design (ISED) : 267 -272
Kochi, India
Report No: IIIT/TR/2011/-1
Centre for VLSI and Embeded Systems Technology International Institute of Information Technology Hyderabad - 500 032, INDIA December 2011
2011 International Symposium on Electronic System Design
Adiabatic 5T SRAM
Mamatha Samson, Satyam Mandavalli Center for VLSI and Embedded System Technologies, International Institute of Information Technology, Hyderabad, India e-mail:
[email protected] Abstract— In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write operation. This energy efficient SRAM also provides good performance parameters and hence suitable for high density embedded systems.
designed for SRAM in [7]. The imbalance in load capacitances will affect the operation of the clock driver. The design of an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by recovering energy from the bit/word line capacitors and powered by a single-phase sinusoidal power-clock is reported in Ref.[8]. A low-power SRAM using hierarchical bit-line and local sense-amplifiers (HBLSASRAM) has been reported to reduce write power consumption in bit-lines [2]. It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSASRAM reduces the write power consumption in bit lines by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive subbit line. However, HBLSA-SRAM needs local senseamplifiers in each SRAM sub-arrays and results in additional area overhead. The write scheme with differential voltage swing of a bit-line obtained by recycled charge from its adjacent bit-line capacitance instead of the power line is implemented and reported in [9]. Although this significantly reduces the total power dissipation, this scheme employs many power switches and reference generating circuit resulting in additional area over head. Static noise margin is found to be reduced by 38%. A 6T Single ended SE-SRAM bit cell and its word orientation array design is presented in [10]. This circuit employs only one bit line for both read and write operation to save power as well as area. However the mean read access time is much larger than the conventional 6T SRAM. A 5T SRAM was proposed by Hiep Tran [12] in which the latch of the cell is floated during write operation. Another 5T SRAM that is asymmetric in size was proposed by Ingvar Carlson [13] which has 50% lower static noise margin SNM compared to 6T SRAM. The 5T SRAM proposed in [14] is port less SRAM and has a dependency of bit line capacitance on cache data, an effect not seen in other SRAM methodologies. From the above description it is clear there is always some drawback of a feature or of complex nature. In view of this, investigations have been carried out to arrive at a memory cell structure which is simple and energy efficient.
Keywords- Energy, Adiabatic, 5TSRAM, read stability, driver
INTRODUCTION Stable, low leakage and energy efficient SRAMs are essential for mobile applications where on chip memories are employed. But bit line charging and discharging during write operation results in most of the energy loss and is the bone of contention. It is reported that 70% of the total active power is dissipated during read and write operations [1]. The power dissipated in bit lines represents about 60% of the total dynamic power consumption during a write operation [2]. The power consumption by bit lines is proportional to the bit line capacitance, square of the bit line voltage and the frequency of writing. A number of SRAM memory designs are reported in the literature which attempt to achieve minimum energy loss both at SRAM cell level as well as at the architecture level. Allowersson and Andersson [3] proposed a technique where they use a low bit line reference voltage of 0.5 volt under VDD equal to 5volts. The penalty of this technique is that when access n-transistors are gated by a lower voltage, their read accesses become slower, resulting in a longer read delay. Half swing technique shows about 45% write power reduction by reducing the bit line swing to 0.5VDD [4]. Noise margin is found to be reduced by this method. A 7T sense amplifying SRAM cell that can achieve 90% power consumption reduction has been reported in [5]. In this scheme for stable write operation, the bit line voltage swing should be greater than a marginal value to be able to invert the status of SRAM cell in write operation. Both read delay and noise margin are degraded in it. In 7T cell reported in [6], write operation depends only on transferring a small voltage swing on bit lines to store it in the cell. The ground transistor provided assists to achieve the result. An energy- recovery latch/driver based on bootstrapping effect in conjunction with two phase resonant clock driver is 978-0-7695-4570-7/11 $26.00 © 2011 IEEE DOI 10.1109/ISED.2011.57
In this paper an effort is made to design a 5T SRAM with a single bit line, a simple energy recovery driver per bit line and a single ended read amplifier in 65nm technology using
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Predictive Technology (PTM ) models [16] to arrive at high density reduced leakage and energy efficient SRAM suitable for embedded applications. Section II explains briefly working of energy efficient SRAM. Section III compares the performance of the adiabatic SRAM with non adiabatic 5T SRAM and section IV briefly examines the effect of threshold voltage variations on the stability of adiabatic SRAM. Section V compares the total energy of adiabatic 5T SRAM with other SRAMs which is followed by conclusion in the last section. Single ended read amplifier
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Figure 1. Circuit diagram of Energy efficient SRAM: (a) SRAM with write driver
CMOS latch and a single access transistor. One write driver is needed for each column. The same access transistor is used during reading as well as writing. Larger sized access n transistor and the write driver helps in the overcoming the writing problem associated with single bit line SRAMs. The ratio of the widths of pull up p transistor to pull down n transistor of the first inverter is equal to 1 where as that of the second inverter is 1/6.15.This ratio provides higher read stability. The driver circuit consists of an n and a p transistor connected to the bit line capacitance through diodes. When the input data say ‘Din’ is high, the capacitance charges to the peak value of the power clock voltage ‘Vpc’ through the diode D1. When the input data is low, the excess charge stored in the capacitance is pumped back to the power clock through diode D2. Hence there is very less loss of energy as adiabatic principle is used. In order to make use of these drivers to save energy in bit lines, one driver is needed for a bit line. The energy saved is proportional to 1/2CV2 (C represents the bit line capacitance and V represents the bit line voltage). The bit line capacitance depends on the number of rows and the technology. Energy dissipated during charging the load capacitance can be reduced by employing slowly varying supply waveform such as triangular, sinusoidal etc. We have considered sinusoidal signal source of 100MHz with a dc shift of value equal to that of half of power supply voltage (1.1V) mainly because of ease of generation. A single sinusoidal signal source is sufficient for the entire SRAM array. The MOSFET models for 65nm are derived from predictive technology model (PTM) web site [17]. The JUNCAP1 model level equal to 4 is used for diodes. The waveforms during write, hold and read are as shown in the Fig. 2 for non adiabatic SRAM and in Fig.3 for adiabatic 5T SRAM. The write enable signal ‘WE’ (Fig. 2d and Fig. 3d) activates the switch connected to the bit line during write operation. This ensures that the data is applied
Figure 1: (b) Circuit diagram of single ended read amplifier:
Predictive Technology (PTM) models [16] to arrive at high density reduced leakage and energy efficient SRAM suitable for embedded applications. Section II explains briefly working of energy efficient SRAM. Section III compares the performance of the adiabatic SRAM with non adiabatic 5T SRAM and section IV briefly examines the effect of threshold voltage variations on the stability of adiabatic SRAM. Section V compares the total energy of adiabatic 5T SRAM with other SRAMs which is followed by conclusion in the last section.
II.
ENERGY EFFICIENT SRAM –OPERATING PRINCIPLE
Energy efficient SRAM cell is shown in the Fig. 1a. It consists of asymmetrically sized CMOS latch and a single access transistor. One write driver is needed for
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to the bit line only when the write operation is enabled. The first step in the write operation is to apply the data ‘DIN’ to the bit line through the energy recovery driver unlike in the case of non adiabatic one where it is applied through driver transistors. The waveforms of bit line voltages are shown in Fig. 2b and Fig. 3b for non adiabatic and adiabatic 5T SRAM respectively. Then the word line signal ‘wl_00’ is activated as shown in Fig. 2c and Fig. 3c for non adiabatic and adiabatic 5T SRAM respectively. In case of adiabatic 5T SRAM, when the input signal say ‘DIN’ is high, the bit line capacitance ‘CBL’ charges to the peak value of the power
clock voltage ‘Vpc’ through diode D1. When the input signal is low, the excess charges stored in the capacitance are pumped back to the signal generator through diode D2.Thus when the storage node (Fig. 2a and Fig. 3a) has to change from ‘1’ to ‘0’ the energy from the bit line flows into the power clock through the energy recovery driver. Where as in the conventional SRAM it goes to the ground and gets wasted. Thus in this new SRAM the energy that is usually lost during writing operation is partially recovered. Reading is done by the single ended read amplifier to improve read stability. The single ended read amplifier
1.1V
(a) 0V 1.1V
(b)
0V 1.1V
(c)
0V 1.1V
Voltage (V)
(d) 0V 1.1V
0V 1.1V
(e)
0V
(f)
Figure 2. Waveforms during write, hold and read operation of 5T SRAM with single ended read amplifier
1.1V
(a)
0V 1.1V
(b) 0V 1.1V
(c) 0V 1.1V
Voltage (V)
(d) 0V 1.1V
0V 1.1V
(e)
0V
(f)
Figure 3. Waveforms during write, hold and read operation of energy efficient SRAM with single ended read amplifier
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as shown in the Fig. 1b consists of two staged CMOS inverters sized in increasing order . It is shared between the cells in the column and enabled by ‘psae_00’ alias ‘RD’ during read operation as shown in the Fig. 2e and Fig. 3e. The output of the read amplifier is as shown in the Fig. 2f and Fig. 3f for non adiabatic and adiabatic 5T SRAM respectively. Prior to reading pre charging is not used and the charge on the bit line is used during read operation. If no level change is needed during read operation the bit line charge is retained in the bit line. The quantity of energy lost during reading however is controllable by restricting the time of discharge in the proposed adiabatic SRAMs. In the following section the performance parameters of 5T adiabatic SRAM is compared with that of non adiabatic 5T SRAM at room temperature. III.
Figure 4. Total energy (pJ) of SRAM for both the types of SRAMs
COMPARISON OF PERFORMANCE OF ADIABATIC 5T SRAM WITH 5T SRAM
A. Total energy In order to study the performance of adiabatic 5T SRAM in comparison with non adiabatic 5T SRAM two write operations and three read operations with hold operation between every write and read operation on a 4X8 SRAM are carried out. It is seen in the Fig. 4 that the energy consumed in the non adiabatic 5T SRAM (Type1) is comparatively higher. However 53% of total energy is saved by the adiabatic SRAM (Type2) when compared to its non adiabatic type. The energy overhead of the power clock is not considered in the calculation.
Figure 5. Static noise margin of SRAM for both the types of SRAMs
B. Static noise margin The static noise margin is defined as the maximum noise that can be tolerated at the input of the SRAM without changing its status. It is given by the size of the smallest square that can be inscribed in the butter fly curve of the SRAM [15]. The SNM of both SRAMs is found to be 0.357V by using HSPICE code [16]. Fig.5 shows the similarity of SNM of both SRAMs.
Figure 6. Write margin (V) of SRAM for both the types of SRAMs
C. Write margin Write margin is found as the maximum bit line voltage at which the write operation is obtained when the bit line voltage is changed from VDD to 0V. It is found to be same for both SRAMs and is equal to 0.669V (0 to 1 change) and 0.72V (1 to 0 change). The similarity is shown in the Fig. 6. D. Read delay The read delay is defined as time delay between 50% level change in the word line signal to 50% level change in the output of the sense amplifier. Generally the differential type of sense amplifier results in less delay compared to single ended buffer. However the delay in the single ended buffer is improved by choosing inverters with sizes in the increasing order reduced bit line capacitance. The comparison of read delays is shown in the Fig.7. The read
Figure 7. Read delay (ns) of SRAM for both the types of SRAMs
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been carried out to find the spread of total energy consumed, SPNM, WTP, read delay and write delay both for non adiabatic and adiabatic SRAMs at room temperature. The distribution of total energy of non adiabatic 5T SRAM cell and that of adiabatic SRAM cell is as shown in the Fig. 10 and Fig. 11 respectively. It can be seen that there is total energy reduction to the tune of around 50% in case of adiabatic 5T SRAM. The distribution has a mean of 0.275V and sigma of 30.373mV. The performance parameters of adiabatic 5T SRAM namely static noise margin, write margins and read delay have not varied much. However the write delay has changed marginally.
delay is found to have remained same in both the SRAMs with single ended reading amplifier. E. Write delay The write delay is the difference in time between 50% level change in the word line signal and the 90% level of the storage node. As it is seen in the Fig. 8 the write delay is found to be increased in the adiabatic SRAM when compared to the non adiabatic SRAM at room temperature. The rise is 9.89 times in case of adiabatic SRAM with single ended reading amplifier. F. Leakage power Leakage power is found to be generally less in 5T SRAM due to the absence of a bit line. But it is found that the adiabatic SRAM further reduces leakage power by 0.25 times as it is seen in the Fig. 9. Thus we can conclude that leakage current is also converted into useful current by means of pumping action. IV.
V.
PERFORMANCE OF 5T SRAMS WITH OTHER SRAMS
The total energy of various SRAM cells is compared in the Table 1.1. It is seen that 5T SRAM has saving in energy of the order of 98% when compared with 6T conventional SRAM.
EFFECT OF PROCESS VARIATION ON 5T ADIABATIC SRAM
VI.
The threshold voltage Vt is expected to vary randomly due to variations in the process. The threshold voltage considered is -0.471 for PMOSFET and 0.516 for NMOSFET. The value of standard deviation is taken to be 30mV (approximately 8% of the threshold voltages. The power supply voltage is taken as 1.1V and a 10% variation
CONCLUSION
In this paper effort is put in order to arrive at an energy efficient and high density 5T SRAM. Energy saving of the 40 35
Frequency
30 25 20 15 10 5 0 0
0.2
0.4
0.6
0.8
Total energy in joules
1 -10
x 10
Figure 10. Distribution of total energy (J) of non adiabatic 5T SRAM Figure 8. Write delay(ns) of SRAM for both the types of SRAMs
160 140
Frequency
120 100 80 60 40 20 0 0
of this which is 110mv is taken as the sigma for the variation of the power supply voltage. Using these
0.2
0.4
0.6
0.8
Total energy in Joules
parameters Monte power carloofsimulation (1000) in Hspice has Figure 9. Leakage SRAM for both the types of SRAMs
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1 -10
x 10
Figure 11. Distribution of total energy (J) of adiabatic 5T SRAM
order of 53% is achieved along with leakage power reduction. However the write delay of the adiabatic 5T SRAM is more than that of the non adiabatic 5T SRAM at room temperature. This type of SRAM can be used in hand held mobile systems and embedded systems.
ACKNOWLEDGMENT
This work has been funded under WOS-A scheme of Department of Science and Technology, Govt. of India.
Table 1
REFERENCES
Mean and standard deviation of Adiabatic 5T SRAM [1] Adiabatic 5T SRAM cell Performance parameters
Mean(μ)
Standard deviation()
[2]
Total energy(n J)
0.0285
0.01
[3]
0.275
0.03
[4]
0.626
0.021
0.778
0.027
Read delay(ns)
1.48
0.2592
Write delay(ns)
13.9
8.21
SNM (V)
Write margin (V) 0 to 1 1 to 0
[5]
[6]
[7]
[8]
[9]
Table 2 [10] Performance comparison of various types of SRAMs
Type of SRAM
6T SRAM Symmetricdouble ended reading (2 bit lines) 5T SRAM Asymmetric-single ended (1 common bit line) Adiabatic 6T SRAM Symmetric-double ended reading (2 bit lines) Adiabatic 5T SRAM Asymmetric-single ended (1 common bit line)
Percentage saving in energy when compared with 6T non adiabatic SRAM
[11]
2.995X10-9
---------
[13]
11.19X10-11
96.26
1.189 X10-9
60.3
5.2X10-11
98.2
Total energy in joules
[12]
[14]
[15]
[16]
[17]
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