ADVANCED COMPUTER ARCHITECTURE.pdf - Google Drive

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VII Semester B.E. (CSE/ISE) Degree Examination, June/July 2015 (2K11 Scheme) CI71/IS74.3 : ADVANCED COMPUTER ARCHITECTURE Time : 3 Hours

Max. Marks : 100

Instruction : Answer any 5, selecting atleast 2 from each Part. PART – A 1. a) Briefly discuss the five generation of the electronic computer.

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b) Explain the concepts of implict parallelism and explicit parallelism and list the differences. 10 2. a) Consider the execution of an object code with 2,00,000 instruction on a 40 – MHz processor. The program consists of four major type of instruction. The instruction mix and the number of cycle (CPI) needed for each instruction type are given below based on the result of a program trace experiment. 10 Instruction Type

CPI

Instruction Mix

Arithmetic and logic

1

60%

Load/store with cache hit

2

18%

Branch

4

12%

Memory reference with cache miss

8

10%

i) Calculate the average CPI when the program is executed on a uniprocessor, with the above trace results. ii) Calculate the corresponding MIPS rate based on the CPI obtained in part (i) b) Explain the architecture based on resource sharing, structure and interprocessor communication of UMA, NUMA and COMA computer.

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3. a) Define the following terms related to parallelism and date dependence relation (5×2=10) 1) Flow dependence 2) Anti dependence 3) Output dependence 4) Input/output dependence 5) Unknown dependence. P.T.O.

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b) Explain the Bernsteins conditions with the example which has the statements as below : S1

:

A=B+C

S2

:

C=D+F

S3

:

F=G+E

S4

:

C=A+F

S5

:

M=G+C

S6

:

A=L+C

S7

:

A=E+A

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4. a) Draw the block diagram of RISC superscalar processor and explain its architecture.

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b) Describe the daisy-chaining bus arbitration in a multiprocessor system.

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PART – B 5. a) Differentiate between linear pipeline processor and non-linear pipeline processor. b) For a given pipeline design below, i) ii) iii) iv)

Construct reservation lable Find MAL Determine all cycles Determine greedy cycle.

The O/D is obtained from stage S1 at 6th clock pulse.

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6. a) With respect to Snoopy bus protocol, explain write-through caches and writeblock caches. 10 b) Explain with a neat diagram a cross point switch design in a cross bar network and list out the limitation of cross bar.

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7. a) Discuss the feature of a language required for parallel processing.

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b) With a case-study, explain the application of parallel program.

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8. Write a short notes on (any four) : 1) Message passing schemes 2) Omega network 3) Scalable multiprocessor 4) Goodman’s write-once protocol 5) Cache coherence problem.

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(5×4= 20)