All-optical logic gates using a semiconductor optical amplifier assisted by an optical filter Z. Li, Y. Liu, S. Zhang, H. Ju, H. de Waardt, G.D. Khoe H.J.S. Dorren and D. Lenstra Abstract: A simple all-optical logic device, composed of an SOA and an optical filter, is proposed. By utilizing optical filtering, multi-logic functions (AND, OR and XOR) are demonstrated at 10 Gb/s using the same setup, under different operation conditions. Simulations indicate that the device can operate at much higher bit rate. Introduction: All-optical logic gates have received considerable attention in the field of optical networks [1]; they can enable many advanced functions such as all-optical bit-pattern recognition [2], all-optical bit-error rate monitoring [3], all-optical packet address and payload separation [4], all-optical label swapping [5] and all-optical packet drop in optical time domain multiplexing (OTDM) networks [6]. Many approaches have been proposed to achieve all-optical logic functions, based on the nonlinear effects either in optical fibre or in semiconductor material. Compared with their optical-fibre based counterparts [6, 7], all-optical logic gates based on semiconductor optical amplifiers (SOAs) are promising because of their power efficiency and their potential for photonic integration [1-5, 8-9]. In the literature most of the SOA-based optical logic gates employ interferometric structures, which requires several SOAs and makes the system complicated [1, 8-9]. A logic gate based on four wave mixing (FWM) in an SOA has also been demonstrated in [10], however, the scheme suffers from a low conversion efficiency, high input power and polarization dependence.
In this letter we propose a simple and polarization-independent logic gate composed of a single SOA followed by an optical bandpass filter (BPF). We achieve various logic functions with the same setup under different operation conditions. Two control signals (pulsed) and a probe (continuous wave, CW) are injected into the SOA, leading to a broadened probe spectrum due to carrier density modulation by the control signals. We explain how different logic functions can be realized by filtering the spectrally broadened probe light using the BPF. We demonstrate AND, OR and XOR logic functions at 10 Gb/s. Our results are in agreement with the numerical simulations. Simulations show that higher bit rate operation should be possible.
Operation principle: The proposed logic gate is shown in the dashed box in Fig.1 (a). Two modulated optical return-to-zero (RZ) control signals (Data1 and Data2), combined with a CW probe, are injected into the SOA. The signals Data1 and Data2 might be at different wavelengths but this is not essential. However, Data1 and Data2 should be at a different wavelength than the probe. Due to cross gain modulation (XGM) and cross phase modulation (XPM), the falling edge of the probe is shifted by the SOA towards longer wavelength (red-shift), while the rising edge is shifted towards shorter wavelength (blue-shift)[11]. Hence, the probe spectrum is broadened, as illustrated in Fig.1(b), where the BPF shape is also shown by the dashed curve. Since the control pulses introduce spectral blue-shift for the probe light, an optical filter can be utilized to reject the central wavelength of the probe light and to select the blue-shifted spectrum, so that the probe can only pass through the optical filter when the control signal is present. Based on this principle, non-inverted all-optical wavelength conversion at 40 Gb/s has been demonstrated [12]. The amount of the induced blue-shift can be controlled by the power of the input light (Data1, Data2 and
probe). Through properly adjusting the power levels and the filter centre wavelength (by adjusting
), we show that different logic functions can be realized.
If control pulses are launched simultaneously at Data1 and Data2, the modulated probe will receive a much stronger spectral blue-shift compared to the case that only one pulse is present, either in Data1 or Data2, because the SOA is working in deeper saturation due to the higher power. The BPF can be utilized to select the stronger blue-shift caused by the two control pulses, while rejecting the weaker blue-shift created by one single control pulse. Thus, at the output of the BPF, a pulse from the probe will be generated only when there are simultaneous control pulses in Data1 and Data2. In this way an AND gate is realized.
Similarly, the BPF can be adjusted to select the weaker blue-shift created by one control pulse and to reject the stronger blue-shift created by two control pulses. At the output of the BPF, a pulse from the probe will be generated only when one control pulse appears. Therefore, an XOR gate can also be realized.
When the SOA operates in a strong-saturation regime, the difference of the amount of blue-shift, induced by two simultaneous control pulses or a single control pulse, is small. Both of the induced blue-shifts can be fitted in the pass band of the BPF. In this way, an OR gate is realized.
The logic functions are simulated on the basis of a rate equation model [11] at a data rate of 10 Gb/s, as shown in Fig.1 (c-g). In the simulations, a Gaussian filter of 15
GHz full-width-at-half-maximum (FWHM) is used. The SOA has a carrier lifetime of 200 ps and a line-width enhancement factor of 6.
Experiment and Results: The experimental setup shown in Fig.2 was constructed using commercially available fibre-pigtailed components. A 10 Gb/s data stream with 2.3 ps FWHM optical pulses, generated by an actively mode-locked fibre ring laser, is modulated by an external modulator at 10 Gb/s to form a 27-1 RZ pseudo random binary sequence (PRBS). The center wavelength of the data signal is 1549.98 nm. This data stream then is divided into two channels (Data1 and Data2) by a 3dB coupler. The signal in Data2 is delayed by propagating through 2 km dispersionshifted fibre (DSF) to remove the coherence between the two channels. Another 3 dB coupler is used to combine the two channels again. After being amplified through an EDFA, Data1 and Data2 are injected into the optical logic gate with a CW probe through a 3dB coupler. As shown in Fig.2, attenuators ATT1 and ATT2 are adjusted so that the average powers in Data1 and Data2 are equal before the SOA. The variable delay VD is adjusted such that pulses in Data1 and Data2 are synchronized. As shown in the dashed box in Fig.2, the optical logic gate is composed of an SOA and a 0.3nm (FWHM) BPF, whose centre wavelength is fixed at 1560nm. After the optical filter, the signal is amplified by another EDFA before being monitored by an oscilloscope with a specified electrical bandwidth (FWHM) of 50 GHz. The SOA (manufactured by JDS Uniphase) is pumped with a current of 350 mA. The gain recovery time of the SOA is approximately 150 ps. Note that, in the experiment, we tune the wavelength of the probe to change the relative position of the filter with respect to the probe without adjusting the filter centre-wavelength. Since the filter is detuned from the central wavelength of the probe light, the output power from the filter is attenuated. The
amount of the attenuation is mainly determined by the filter detuning. In the experiment the attenuation is more than 15 dB.
Fig.3 shows the experimental results at 10 Gb/s. Two input control channels are shown in Fig.3 (a) and (b). The AND gate operation is presented in Fig.3 (c), where the input power of the probe is 1.12 mW, the powers of both control channels are 0.65 mW and the filter detuning is 1.82 nm. The operation conditions can be found in Table.1. By changing the powers of the input signals (probe light and control pulses) and the filter detuning, OR and XOR gates are also realized, as shown in Fig.3 (d) and (e). The corresponding operation conditions are also presented in Table.1. We do not observe patterning effect in the experiment. We observe some small residual pulses in the AND and XOR gates output where ideally they should not appear. However, this could be improved by optimizing the filter transfer function. In Fig.3 the zero levels of the output signals are not precisely at the ground level. This is due to the fact that the slope of the optical bandpass filter in the experiment is about 0.4dB/GHz, which is not steep enough to reject the centre part of the probe spectrum. The simulations show that the zero levels can reach the ground level if the filter slope is steeper than 0.6dB/GHz. This is also experimentally confirmed [12].
Simulations show that the proposed logic gate could operate at considerably higher bit rate (for example, OR operation at 80 Gb/s). However, the filter then needs to be further detuned from the probe carrier wavelength, which will degrade the optical signal-to-noise ratio of the output signal. This will ultimately put a speed limit on the ultra-high bit rate operation.
Conclusion: A simple optical logic device is proposed and demonstrated at 10 Gb/s. We explain how this system can realize AND, OR and XOR gate functions based on the same setup but with different operating conditions. The proposed logic gate has a very simple structure and allows photonic integration.
Acknowledgement: This work was supported by the Netherlands Organization for Scientific Research (NWO), the Technology Foundation STW and the Ministry of Economic Affairs through respectively the NRC Photonics grant, the “Innovational Research Incentives Scheme Program” and the technology program “Towards Freeband Communication Impulse”.
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Authors’ affiliations: The authors are with COBRA Research Institute, Eindhoven University of Technology, P. O. Box 513, 5600 MB Eindhoven, The Netherlands, (Telephone: +31 40 247 5066, E-mail:
[email protected]). D. Lenstra is also with Laser Centre Vrije Universiteit, Amsterdam, The Netherlands
Captions for figures and tables: Figure 1: (a): Proposed logic gate structure; (b): Simulated spectrum of the probe; (c-g): simulation results of the logic gates. Figure 2:
Experimental setup. VD: variable delay, ATT: variable optical attenuator.
Figure 3: The input pulse train in Data1 (a) and Data2(b) and the corresponding output:(c): AND gate output; (d): OR gate output; (e): XOR gate output. Table 1: Input signal configuration in the experiment (Pcw: the input power of the probe; PData: Average power in each data channel)
Figure 1
Figure 2
Figure 3
Logic
Fig
Pcw(mW)
PData (mW)
AND OR XOR
Fig.3(c) Fig.3(d) Fig.3(e)
1.12 0.64 1.06
0.65 1.13 0.27
Table 1
(nm) 1.82 0.54 1.52
