Alpha-particle-induced upsets in advanced CMOS ... - IEEE Xplore

Alpha-particle-induced upsets in advanced CMOS circuits and technology In this paper, we review the current status of single-event upsets caused by alpha-particles in IBM circuits and technology. While both alpha-particles and cosmic radiation can induce upsets, the alpha-particle-induced upset rate has become an increasingly important issue because alpha-particle-induced upsets are no longer limited to memory circuits. Latch circuits have become highly sensitive to alpha-particles. The alpha-particle-induced upset rate of latch circuits is one of the most critical issues for microprocessors requiring both high performance and high reliability.

Introduction Radiation-induced single-event upsets (SEUs) in logic and memory circuits continue to be a key issue for advanced CMOS (complementary metal-oxide semiconductor) technologies. Recent publications show experimental upset rates in both bulk CMOS [1–3] and silicon-on-insulator (SOI) CMOS technologies [4]. For high-performance 65-nm and 45-nm circuits, the critical charge (Qcrit) required to upset the circuit can be very small, making latch and memory circuits susceptible to a wide range of ionizing particles. While alpha-particles have been known to produce SEUs in very-large-scale integrated circuits (ICs) for many years, these upsets were mostly limited to memory circuits in CMOS chips. Specifically, SRAM (static RAM) circuits can be upset with a relatively small amount of charge, so SRAM circuits are the most susceptible to the low level of ionization produced by alpha-particles. With technology scaling, latch circuits have become susceptible to alpha-particles. Currently, the upset rate of latch circuits often determines the overall level of soft errors in high-performance microprocessors. Three factors have contributed to the increased importance of alpha-particle-induced upsets in latches. First, technology scaling has reduced the Qcrit required to upset the latch circuit; smaller capacitances and lower power-supply voltages also have reduced this Qcrit value. In addition, in advanced transistors, bipolar currents can be induced by the deposited charge [5]. The bipolar current adds to the total charge collected, and therefore,

D. F. Heidel K. P. Rodbell E. H. Cannon C. Cabral, Jr. M. S. Gordon P. Oldiges H. H. K. Tang

the charge that must be deposited by ionization can be very small. Second, the increasing number of latches on a chip contributes to the increasing chip fail rate due to latches. While technology scaling reduces the sensitive area of each latch, the number of latches in high-performance microprocessors has increased significantly. The size of the microprocessor chip has also continued to increase with every technology generation. Combining all of these factors leads to an increase in the total sensitive area associated with latch circuits and, therefore, an increase in the SEU rate. Finally, latch circuits are more important in determining the overall fail rate because SEU mitigation techniques are commonly applied to memory circuits. A number of SEU mitigation techniques are available that can be used for memory with a relatively low impact on total system performance and power. One of the most common approaches is the use of error checking and correction (ECC) codes (typically double-bit-error detection and single-bit-error correction). The impact of double-bit errors can be further reduced by interleaving the bits used in any given ECC word. High-performance systems also typically have a memory hierarchy that provides an efficient means of SEU mitigation. Data is stored in multiple levels of the memory system. As soon as one level detects that an error has occurred, it can recover the data from a higher level of the memory system. These SEU mitigation techniques have proven very effective in controlling the overall soft-error rate (SER) from SEUs in memory circuits.

Copyright 2008 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied by any means or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor. 0018-8646/08/$5.00 ª 2008 IBM

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0.4

L1, data 0 L1, data 1 L2, data 0 L2, data 1

0.2

c

0.8 0.6

0.0 0

10 20 30 40 50 60 70 80 Angle (degrees) (a)

2,800 2,400 2,000 1,600 1,200 800 400 0

Data 1, fail 0 Data 0, fail 1 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Vdd (V) (b)

Fail cross-section (maximum normalized to 1.0)

Vdd 1.0 V Upsets

Upsets (maximum count set to 1.0)

3,200 1.0

1.0 0.1 0.01

Data 0, fail 1 V 0.8 V

0.001

0.0001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Alpha-particle energy (MeV) (c)

Figure 1 (a) Measured upsets versus angle for latch chain B on a 65-nm SOI single-event-upset test chip using 5.28-MeV alpha-particles at normal incidence. (b) Measured upsets versus voltage in a 65-nm 1-Mb single-event-upset (SEU) test array using 5-MeV alpha-particles at normal incidence. (c) A plot of the 1-Mb SRAM SEU cross-section, showing the relative dependence of the cross-section on the alpha-particle energy. (Reproduced from [4]; ©IEEE 2006.)

Table 1 Critical angles (hc) and critical charge (Qcrit) values obtained from data using 5.28-MeV alpha-particles.

226

Vdd ¼ 1 V

Latch chain A

Latch chain B

L1, data ¼ 0

hc ¼ 29 degrees Qcrit ¼ 0.5 fC


L1, data ¼ 1



L2, data ¼ 0



L2, data ¼ 1



Because it is much more costly to provide SEU mitigation for latch circuits, the relative SER from SEUs in latches is increasing more rapidly with technology scaling than the SER from SEUs in memory. In addition, the latch fail rate is further increased because the latches can now be upset not only by cosmic particles but also by alpha-particles. The latch fail rate due to alpha-particles is reviewed in this paper. The next section of this paper reviews recent data on alpha-particle-induced upsets in IBM latch and memory circuits. A comparison with modeling results is also shown with the data. A more complete analysis of the SEU circuit modeling is covered in Reference [6]. The third section of this paper describes techniques for mitigating alpha-particle-induced upsets in both memory and latches. The fourth section covers evolving issues for SEUs in latches. The last section summarizes the results presented and describes the projections for SEUs in future technology generations.

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Alpha-particle sensitivity of advanced latches and memory circuits A series of experiments on the upset rates of IBM 65-nm SOI latch and memory circuits have been completed. The data was taken using a 3-MV Tandem Van de Graaff accelerator that can produce a monoenergetic beam of alpha-particles. The full details of the experiments are provided in Reference [4]. Figure 1(a) shows an example of the data obtained on one of the 65-nm SOI latch chains (chain B), as well as the fail rate as a function of angle for both data states of the level 1 (L1) (or master) latch and the L2 (or slave) latch, using 5.28-MeV alpha-particles. Table 1 shows critical angles and the critical charge derived for two of the latch chains tested in these experiments (latch chains A and B). The critical angle is the angle at which the fail rate per incident particle is 10% of the maximum fail rate per incident particle. The 10% angle criteria is low enough to represent the turn-on angle for fails but high enough to contain a sufficient number of fails to produce consistent results. This turn-on angle can then be converted into a critical charge by calculating the charge deposited within the body of the transistor for each angle. Figures 1(b) and 1(c) show the data for an SRAM array at normal incidence. Figure 1(b) shows fail rates for both data ¼ 0 and data ¼ 1 as a function of voltage, while Figure 1(c) shows the measured fail cross-section (at 0.8 V) as a function of the alpha-particle energy. As seen in Table 1, the critical charge for the latches was determined to be approximately 0.5–1.0 fC (femtocoulomb) for states data ¼ 0 and data ¼ 1. This small value of the critical charge can be easily obtained by a wide range of alpha-particle energies and angles.

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FIELDAY modeling Transistor modeling of single events in small circuits was performed using the mixed-mode capability of the FIELDAY program [5, 7, 8]. As described above, the L1 latch (chain A) was defined and simulated. The critical charge is determined by assuming that the alpha-particle strikes at normal incidence through the center of the channel. The charge generation model has an adjustable parameter to scale the ionization. A simple binary hunt algorithm is implemented to submit simulation jobs in parallel with different charge-scaling factors. Iterations on this scaling factor are performed to determine the charge generation that only causes the logic state to switch. Table 2 shows an example of these calculations for the L1 latch (chain A). The simulation results compare favorably with the measured hardware data (shown in Table 1). The measured hardware data is typically dominated by the lowest critical charge value. Therefore, the n-FET values shown in Table 2 (0.53 fC and 0.98 fC) should be compared with the measured values from Table 1 (0.5 fC and 0.9 fC). Using these results, the relative contribution of n-FET and p-FET strikes to the SER can be quantified using the SEU simulator SEMM-2 (IBM soft-error Monte Carlo model) [9]. (For details on the first version of this model, see Reference [10].) These simulation results were further used to help develop a Qcrit model using SPICE, through a detailed comparison of the time evolution of the circuit contact voltages and internal potentials, as described in [5]. Additional single-event simulation studies were performed on the effects of nonnormal incidence strikes including rotation angle, investigation of technology variants, Qcrit variations in SRAM cells, and Qcrit fluctuations due to process variability. The simulations on the rotational angle show that the SEU cross-section is only weakly dependent on the rotational angle; the results of these simulations are consistent with the small Qcrit differences between

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2.0 With mean LET Upper bound Lower bound

1.5 Qdep (fC)

Simulation methodology and extraction of critical charge The deposited charge for a given ion incident energy is calculated by accurately accounting for the energy loss (dE/dx) of the incident particle as it travels through the various materials (wiring metals and insulators) of the back-end-of-line (BEOL) interconnects. Figure 2 shows an example of such a calculation for a 5-MeV alphaparticle as a function of the incident angle. Three curves are shown: one using the mean linear energy transfer (LET) for each of the 11 dual damascene levels in the BEOL process, an upper bound using a particle path that traverses mainly metal regions, and a lower bound using a particle path that traverses mainly insulator regions.

1.0

0.5

0.0 0

20

40 Angle (degrees)

60

Figure 2 The calculated deposited charge from 5-MeV alpha-particles incident on a 65-nm, 1-Mb SRAM array, as a function of incident angle. The BEOL of this sample has 22 levels of metal and insulator, with a total thickness of approximately 11 m. The 60-nm thickness of the active Si layer is used in this simulation. The red curve is computed by using a mean linear energy transfer (LET) for each level. (Reproduced from [4]; ©IEEE 2006.)

Table 2 Critical charge for a level-1 master latch (chain A) at Vdd ¼ 1 V calculated using the FIELDAY program (reproduced from Reference [5]; IEEE 2006). Device

Data ¼ 0 (fC)

n-FET

0.53

p-FET

1.50

Data ¼ 1 (fC) 0.98 .10.0

modeling two-dimensional (2D) and three-dimensional (3D) devices.

Mitigation of alpha-particle-induced upsets The accurate determination of the energy spectra from alpha-particle sources in IBM semiconductor chips and packaging components is critical. Having detectors with low background levels is necessary in order to be able to adequately screen these materials in a timely manner. This is especially true as the need for screening low-alphaparticle materials for chip and package applications increases, a need driven by the increased sensitivity of modern circuits (both memory and logic) to alphaparticle-induced soft fails [11]. In many cases, the alphaparticle source is commonly generated in materials adjacent to the chip, in the solders, and in the packaging materials.

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Package Cu pad

Cu via

Ta/TaN

SiO2 Si3N

Conventional BEOL (a)

Package Cu pad Cu via

Ta/TaN PSPI

Typically, SERs in volatile memory can be ameliorated through software using ECC. This option does not exist in logic, because costly circuit redundancy would be required. Other approaches entail additional layers sandwiched between the traditional last level of metallization on the chip and the solder that is used for attachment to the package (Figure 3). Two approaches should be considered: The first is to extend the current BEOL structure using a copper (Cu) damascene integration approach, and the second is to add a layer of Si (silicon) interposer, containing through-vias for contacts. Two options have been explored for the first approach [12]: 1) Cu in SiO2 and 2) Cu in a photosensitive polyimide (PSPI). In addition to serving as blocking layers, circuitry can be added to these layers, such as passive electronic components (e.g., resistors and capacitors), in order to enhance chip performance. The advantage of the Si interposer approach over the Cu damascene approach is that it can be produced and tested independent of the IC chip, lowering both the production cost and the good die yield loss.

Adhesion layer

Summary of alpha-particle emissions from interconnect metallization and packaging Conventional BEOL (b)

Package

W via

Ti/TiN Silicon

Conventional BEOL (c)

Figure 3 A schematic representation of three alpha-particle mitigation layers that will prevent alpha-particles emitted from packaging materials from reaching the silicon surface: (a) a Cu damascene build in SiO2; (b) a Cu damascene build in PSPI; (c) a silicon interposer build. In (c), the via is an annular via in which the outside of the via is composed of a Ti/TiN liner followed by CVD-W; the inside of this via is an insulator (Si/SiO2); the conducting path is through the CVD-W ring around the center support pillar. (PSPI: photosensitive polyimide; BEOL: back end of line; CVD-W: chemical vapor deposition of tungsten.) (Reproduced from [12].)

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The alpha-particle SER is driven by BEOL metallization and packaging material alpha-particle-emitter compositions. Lead (Pb) solder in the form of solder balls is a significant contributor to the SER. The Pb-210 isotope, which leads to alpha-particle emissions, is chemically inseparable from stable Pb isotopes. Therefore, obtaining very low alpha-particle-emitting Pb is a challenge for the semiconductor industry. Lead-free solder does not guarantee low alpha-particle levels, since tin (Sn), for example, can have an appreciable alphaparticle component because of the incorporation of impurities during Sn refining. Samples of Sn have been observed to emit alpha-particles at rates as high as or higher than those of Pb. Within IBM, there are continuous efforts to achieve the lowest alpha-emitting solder for both Pb solder and Pb-free solder; however, solder balls remain a significant source of the alphaparticles. The alpha-particle emission rates for solder are typically in the range of 5–50 counts/cm2-khr. Another source of alpha-particle emission is the packaging materials. Underfill, overmolds, organic packages, and ceramic packages can all be sources of alpha-particles. While mold compounds are generally in the range of 1–5 counts/cm2-khr, this alpha-particle contribution to the SER cannot be ignored as the industry moves toward technologies that are more sensitive to alpha-particle energy. Organic and ceramic packages can also emit a significant amount of alphaparticles, on the order of 80–100 counts/cm2-khr.

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0.006

Multiple-bit fails (% of SEU)

Two paths can be taken to control the alpha-particle component of SERs in new technologies. The first is an effort to drive the alpha-particle levels of the material to even lower emission rates. This requires the development and manufacturing of products using new material compositions, as well as better qualification and monitoring of incoming materials, which in turn requires the development of more-sensitive alphaparticle detection equipment that can isolate subtle changes in the alpha-particle emission rate of materials. The second is an effort to develop an alpha-particle barrier that prevents all alpha-particles from external sources from affecting product circuits. The barrier could reside either on the chip directly under the solder balls or on the packaging above the thin-film wiring levels. Both of these approaches add processing complexity and cost, and they still require a level of internal alpha-particle contamination control by manufacturing lines. However, the flux of alpha-particles reaching the ICs is greatly reduced, effectively switching this problem from one of internally generated alpha-particles to one of solely a cosmic neutron particle flux issue.

Multiple-bit fail data 148-MeV protons 0.004

0.002

Closely spaced SEUs

0.000 1

2

3

4

Cell pitch

Figure 4

Evolving single-event issues

Multiple-bit upsets (MBUs) in 65-nm SOI SRAM arrays. The value at a cell pitch of 1 represents MBUs on nearest-neighbor cells, while the point at a cell pitch of 1.4 represents the MBUs on cells that are on a diagonal path. The shaded region at the bottom of the figure represents a statistical limit to the data on the basis of the total number of fails observed in each sampling of the data. This limit represents the probability that two random single-event upsets (SEUs) will occur in cells at a given cell pitch.

In latches, the increasing rate of SEUs caused by alpha-particles, as described above, is one of the most difficult SEU issues for advanced high-performance microprocessors. However, numerous additional singleevent effects are also important, including multiple-bit upsets (MBUs), single-event transients (SETs), and the upsets caused by direct ionization from protons. As described below, these single-event effects are mostly initiated by inelastic collisions from terrestrial cosmic neutron radiation. Because alpha-particles are among the most prevalent fragments generated in an inelastic collision, the increasing upset sensitivity from alphaparticles also enhances the SEU issues that are due to cosmic neutrons. MBUs are a key issue for many systems [2]. Most of the published work on MBUs has focused on memory circuits. However, as with single-bit upsets in memory, effective mitigation techniques exist to minimize the impact of MBUs in memory. The more challenging issue is multiple-bit effects in latches. MBUs can prevent parity-checking circuits from detecting latch upsets and can limit the effectiveness of redundant latches. MBUs can be caused by several mechanisms, the most common of which is charge sharing between two closely spaced nodes. An ionizing particle at a particularly shallow angle will deposit charge in the silicon substrate or well structures of bulk CMOS circuits. The charge generated can be collected and can upset multiple circuits. Because SOI technology isolates each transistor from the silicon substrate, charge sharing will not create MBUs

in SOI circuits. However, MBUs can still be created in SOI transistors. An inelastic collision from a high-energy neutron can often produce multiple fragments and each of these fragments can upset a memory cell or latch. A single fragment that is emitted parallel to the silicon surface can also cross and upset multiple memory cells in either bulk or SOI technologies. Figure 4 shows data on MBUs from a 65-nm SOI memory array produced by 148-MeV protons. The 148-MeV protons will create fragments from inelastic collisions that are similar to fragments created by terrestrial neutrons of the same energy. These data indicate that the MBU rate is relatively low in SOI technology. Even for closely spaced circuits, the MBU rate is much less than 1% of the singlebit error rate. The lower MBU rate is one advantage of SOI technology. Nevertheless, MBUs in all technologies can be important if parity checking and ECC are used to eliminate SEUs. The issue of SETs is becoming more significant in advanced technologies. For older technology generations, SETs are typically observed only in space applications and are caused by the heavy ions in the space environment. For 90-nm technologies and beyond, SETs can also be produced in terrestrial environments. The largest transients are created by the heavier fragments produced in an elastic collision of a high-energy neutron. The length of the transient pulse created is long enough

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45

180

No. of fails (0.4 V)

40

Level 1, data 1 Level 2, data 1 Level 1, data 0 Level 2, data 0 Level 1, data 1, 0.8 V

120 100 80

35 30 25 20

60

15

40

10

20

5

0 0

20

40 Angle (degrees)

60

80

No. of fails (0.8 V)

160 140

0

Figure 5 SEU fails as a function of the incident angle at 0.4 V for L1/L2 and data 0 and data 1 and at 0.8 V for the L1 latch and data 1 state, using 1.25-MeV protons. (Reproduced from [13]; ©IEEE 2007.)

that it will not be attenuated in passing through stages of logic toward the latch circuit. For static CMOS circuits, the pulse must arrive at the latch simultaneously with the clock capture edge. Therefore, the upset rate due to SETs will scale as the length of the SET divided by the clock period. The increasing importance of SETs is a function of both the longer transients created and the shorter cycle times of high-performance chips. Upsets due to direct ionization from high-energy protons [13] have also been observed. Figure 5 shows upsets of 65-nm SOI latches that are due to direct ionization resulting from high-energy protons. The energy of the proton was carefully chosen in order to produce the maximum rate of ionization in the body of the transistor. Most high-energy protons create less charge per unit length and are not capable of upsetting these latches. However, the results demonstrate that upsets can be created by the relatively low ionization rate of protons. As latches become more susceptible to protons, these fail rates can become significant because of both the large number of secondary protons created in inelastic collisions and the long distances that protons travel.

Discussion and conclusions

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The issue of radiation-induced upsets of latch circuits by both alpha-particles and cosmic radiation is significant for systems requiring high reliability. The alpha-particleinduced upset rate of latches has increased dramatically for several technology generations and will continue to increase in future technologies. This increasing trend of upsets is driven by the lower critical charge required to

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upset the latches, as well as the rapidly increasing number of latches on a chip. The increasing upset rate can be mitigated by many techniques. Technology options include using materials with lower emission rates, building barriers to reduce the number of alpha-particles that reach the transistors, and building circuits that are less sensitive to collecting the charge generated. As is described in other papers in this issue, the upset rate can also be mitigated at the circuit level or the system level. With the increasing sensitivity to alpha-particles, choosing latch designs consistent with the overall SER for the system is important.

Acknowledgments We acknowledge valuable interactions with many of our IBM colleagues including Robert Dennard, AJ KleinOsowski, Scott McAllister, Charles Montrose, Conal Murray, and Tak Ning.

References 1. D. G. Mavis and P. H. Eaton, ‘‘SEU and SET Modeling and Mitigation in Deep Submicron Technologies,’’ 2007 Proceedings of the 45th Annual IEEE International Reliability Physics Symposium, 2007, pp. 293–305. 2. G. Gasiot, D. Giot, and P. Roche, ‘‘Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm SRAMs and Its Dependence on Well Engineering,’’ IEEE Trans. Nucl. Sci. 54, No. 6, 2468–2473 (2007). 3. P. Roche and G. Gasiot, ‘‘Impacts of Front-End and MiddleEnd Process Modifications on Terrestrial Soft Error Rate,’’ IEEE Trans. Device Mater. Reliability 5, No. 3, 382–396 (2005). 4. D. F. Heidel, K. P. Rodbell, P. Oldiges, M. S. Gordon, H. H. K. Tang, E. H. Cannon, and C. Plettner, ‘‘Single-EventUpset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells,’’ IEEE Trans. Nucl. Sci. 53, No. 6, 3512–3517 (2006). 5. A. KleinOsowski, P. Oldiges, R. Q. Williams, and P. M. Solomon, ‘‘Modeling Single-Event Upsets in 65-nm Siliconon-Insulator Semiconductor Devices’’ IEEE Trans. Nucl. Sci. 53, No. 6, 3321–3328 (2006). 6. A. KleinOsowski, E. H. Cannon, P. Oldiges, and L. Wissel, ‘‘Circuit Design and Modeling for Soft Errors,’’ IBM J. Res. & Dev. 52, No. 3, 255–263 (2008, this issue). 7. P. Oldiges, R. Dennard, D. Heidel, B. Klaasen, F. Assaderaghi, and M. Ieong, ‘‘Theoretical Determination of the Temporal and Spatial Structure of a-Particle Induced Electron-Hole Pair Generation in Silicon,’’ IEEE Trans. Nucl. Sci. 47, No. 6, 2575–2579 (2000). 8. E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, ‘‘Finite-Element Analysis of Semiconductor Devices: The FIELDAY Program,’’ IBM J. Res. & Dev. 25, No. 4, 218–231 (1981). 9. H. H. K. Tang and E. H. Cannon, ‘‘SEMM-2: A Modeling System for Single Event Upset Analysis,’’ IEEE Trans. Nucl. Sci. 51, No. 6, 3342–3348 (2004). 10. P. C. Murley and G. R. Srinivasan, ‘‘Soft-Error Monte Carlo Modeling Program, SEMM,’’ IBM J. Res. & Dev. 40, No. 1, 109–118 (1996). 11. P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones, ‘‘Soft-Error Resilience of the IBM POWER6 Processor,’’ IBM J. Res. & Dev. 52, No. 3, 275–284 (2008, this issue).

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12. C. Cabral, Jr., K. P. Rodbell, and M. S. Gordon, ‘‘Alpha Particle Mitigation Strategies to Reduce Chip Soft Error Upsets,’’ J. Applied Phys. 101, No. 1, 014902-1–014902-6 (2007). 13. K. P. Rodbell, D. F. Heidel, H. H. K. Tang, M. S. Gordon, P. Oldiges, and C. Murray, ‘‘Low-Energy Proton-Induced SingleEvent-Upsets in 65 nm Node Silicon-on-Insulator Latches and Memory Cells,’’ IEEE Trans. Nucl. Sci. 54, No. 6, 2474–2479 (2007).

Received July 12, 2007; accepted for publication November 19, 2007; Internet publication February 27, 2008

David F. Heidel IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 ([email protected]). Dr. Heidel received his B.S. degree in physics from Miami University in 1974, and his M.S. and Ph.D. degrees in physics from Ohio State University in 1976 and 1980, respectively. In 1980, he joined the IBM Research Division at the T. J. Watson Research Center in Yorktown Heights, New York, working on Josephson superconducting technology. Since 1984, he has been working on the design and testing of high-speed circuits, as well as radiation-induced soft errors in memory and logic circuits.

Kenneth P. Rodbell IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 ([email protected]). Dr. Rodbell is a Manager of the Thin Film Metallurgy and Soft Error Rate (SER) Research Department. He joined IBM Research as a Research Staff Member in 1989 after spending 3 years at the IBM Semiconductor Development Laboratory in East Fishkill, New York. Dr. Rodbell received his B.S. (1982), M.S. (1983), and Ph.D. (1986) degrees in materials science and engineering, with a minor in statistics, from Rensselaer Polytechnic Institute. His research interests have focused on silicon-based electronic materials, specifically thin-film metallurgy, crystallographic texture, and electromigration. He began work on radiation-induced soft errors in semiconductor devices in 1999. He has coauthored more than 100 technical articles and has more than 50 U.S. patents. Dr. Rodbell was a recipient of the New York State 2006 Inventor of the Year Award for a Cu plating technology patent.

Ethan H. Cannon IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 ([email protected]). Dr. Cannon received a B.S. degree in engineering physics from the University of California, Berkeley in 1994, and M.S. and Ph.D. degrees in physics from the University of Illinois at Urbana-Champaign in 1995 and 1999, respectively. After postdoctoral studies at the University of Notre Dame, he joined IBM in Essex Junction, Vermont. Currently, he is a reliability engineer focusing on soft-error simulations and measurements.

Cyril Cabral, Jr. IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 ([email protected]). Mr. Cabral is a Research Staff Member at the T. J. Watson Research Center in Yorktown Heights, New York. He received an M.S.E.E. degree from Polytechnic University in 1992 and a B.S.E.E. degree from Manhattan College in 1989. In 1988, he received a B.S. degree in physics/mathematics from Pace University. Mr. Cabral joined IBM in 1989 as an Engineer in the Thin Film Metallurgy and Interconnections Group in the Silicon Technology Department. Currently, he is in the Thin Film Metallurgy and Soft Error Rate Research Department. His main focus has been in the area of silicides used for contacts to CMOS devices, copper interconnects, diffusion barriers, gate metal materials, phase-change memory materials, intermetallic reactions, and development of silicon-based detectors for soft-error rate reduction. Mr. Cabral holds 92 U.S. patents and is first author of 18 publications and coauthor of more than 170 additional publications.

Michael S. Gordon IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 ([email protected]). Dr. Gordon is a Research Staff Member at the T. J. Watson Research Center. He joined IBM in 1987 and spent 15 years working in the IBM

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Semiconductor Research Development Laboratory in East Fishkill, New York, in the field of electron beam lithography before joining the Research Laboratory. He received his B.S. degree in 1982 in engineering physics from the University of Colorado, Boulder, and his Ph.D. degree in 1989 in experimental nuclear physics from the State University of New York at Stony Brook. Dr. Gordon’s research interests are focused on applications of accelerator-based ions including materials analysis and singleevent upsets in semiconductors. He has 24 patents issued and 9 patents pending or in process, and he has 10 inventions published in the IBM Technical Disclosure Bulletin. Dr. Gordon has coauthored more than 40 technical articles. In 2007, he received an IBM Outstanding Technical Achievement Award.

Phil Oldiges IBM Semiconductor Research and Development Center, Systems and Technology Group, Hopewell Junction, New York 12533 ([email protected]). Dr. Oldiges received a B.S. degree in physics from Thomas More College in 1981, and M.S. and Ph.D. degrees in electrical engineering from Cornell University in 1984 and 1988, respectively. From 1984 to 1986, he was a Visiting Research Scientist at Toshiba Corporation in Kawasaki, Japan, investigating the dynamics of alpha-particleinduced charge collection in dynamic memories. From 1988 to 1993, he worked at Sony Corporation, Atsugi, Japan, developing physical models for device simulation. From 1993 to 1998, he worked in the TCAD Group at Digital Equipment Corporation in Hudson, Massachusetts, developing models for front-end process simulation and tools for soft-error evaluation of SRAM and logic. Currently, he is Manager of the Research TCAD Group with the IBM Systems and Technology Group in Hopewell Junction, New York, and is responsible for front-end process and device models for the 32-nm technology node and beyond. He is a member of the IEEE, Tau Beta Pi, and Sigma Pi Sigma.

Henry H. K. Tang IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 ([email protected]). Dr. Tang is a Senior Engineer at the IBM T. J. Watson Research Center. He received his B.A. degree from Kalamazoo College in 1974 (magna cum laude, honors in physics and mathematics, Phi Beta Kappa). He received his Ph.D. degree in 1979 (theoretical physics) from Yale University, where he was a Heyl Predoctoral Fellow. He was a member of the research staff at the Massachusetts Institute of Technology, the Niels Bohr Institute at the University of Copenhagen, and the Cyclotron Institute at the Texas A&M University. In 1986, Dr. Tang joined IBM at East Fishkill to work on the company’s first modeling toolset for particle-induced soft-error analysis. Other areas he has worked on include the modeling of advanced devices and NVRAM (nonvolatile RAM) technology. In 2001, he joined his present group at Yorktown Heights to focus on new radiation-related technology issues, and to develop a new generation of single-eventeffect models and design tools. Dr. Tang has authored and coauthored more than 40 research papers, and he has mentored a number of experimental nuclear physics programs. In 2007, he was awarded an Invention Achievement Award and an Outstanding Technical Achievement Award.

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VOL. 52 NO. 3 MAY 2008