An Application of Network Processor for On-the-fly Packet Payload Compression Ashish Shukla Freescale Software India Pvt. LTD,Bangalore INDIA
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Abstract Getting enough bandwidth is a big problem for a number of network applications. As technology is improving, network capacity is also increasing to address increasing bandwidth demand. We have found that not much work has been done to reduce network traffic by compressing packets that are flowing in a network. However, most of the approaches try to compress packet header, which occupies only a fraction of total packet size, our approach suggest use of network processors to achieve packet payload compression and decompression. On the fly packet payload compression can significantly increase network capacity. Most of the packet payload compression works are based on the use of specialized hardware, ASIC, for compression. In this paper we propose use of network processors to achieve packet payload compression. The proposed solution can be deployed on edge routers or wireless access points.
1. Introduction As the internet applications are growing, bandwidth demand is also increasing. Data compression is most widely used technique to cater bandwidth requirements of applications. However, the computational complexity involved in data compression limits its use in on-the-fly data compression over the network. Almost all on-the-fly packet compression researches are based on the use of specialized hardware ASICs. We introduce here an application of network processor for packet payload compression. Network processors are programmable processors optimized for network processing task. A network processor in general consists of a set of execution engines, where each engine can execute a set of tasks or threads in a highly pipelined manner. These processors also have high speed external memory interface connected to fast memory for storing packets under processing. Some network processors may have built in traffic management capabilities for QoS support. Network processors have drawn significant interest for a variety of compute intensive, high speed lower layer network functions [1, 2, 3]. A network processor offers flexibility of general purpose processors, high
speed equivalent to that of ASIC, short time to market solutions. Network processors consume less power compared with FPGA solutions.
2. Proposed Framework The proposed packet payload solution shall be implemented on data plane of a network processor. The co-processors or packet processing engines shall be running threads that will do packet payload compression and decompression. A data packet when enters into system ingress of network processor shall be compressed, if its payload is more than a defined threshold. On the reverse direction when network processor receives a compressed packet it shall decompress the packet. The packet payload compression threshold can be defined based on particular network characteristics. All packets that are below this threshold shall not be compressed and passed as such to system egress. There are several issues that need attention with such a scheme. First, there should be a method to differentiate between compressed packets and uncompressed packets. Second, the compression algorithm should processes only bulk of payload at a time, i.e. it should not require complete packets in order to produce compressed one. This constraint is to make sure that network processors can implement compression/decompression at line rate. Finally, the compression algorithm should be easy to compute and implement, to allow efficient data plane programming [4]. Implementing a compression algorithm on a particular network processor may not be trivial. Sometimes packet compression at line rate may not be feasible on particular network processor architecture. In such a case an external CAM can be used to achieve line rate. Almost every network processors have high speed external interface to connect to CAM. To differentiate between compressed and uncompressed packets, several techniques can be used. We are suggesting here, use of IP Version field in IP header to indicate compressed and uncompressed packets. The first 4 bit of IP packet contain IP version field. This field can be either 4 or 6 depending upon IPv4 or IPv6. To indicate whether a packet is compressed or not we set/reset the MSB of 4 bit IP version field. A compressed packet shall be indicated by setting MSB to
one. Therefore, when a network processor compresses packet payload, it sets the first bit, i.e. MSB of 4 bit version information. Other end network processor checks this field and if MSB is set, concludes compressed packet. For IPv4 packets the value of 4 bit version field becomes 12 after compression and for IPv6 this becomes 14 after compression. The MSB of 4 bit version information is reset to zero once packet payload is decompressed. Therefore end systems on network do not see compressed packets and behave as such they are sending or receiving normal IP packets. Similar technique can be applied for networks that do not use IP packets. Checksum calculation is required with such a scheme and can be implemented with a separate thread. Further, most of the network processors have instructions in its instruction set for efficient calculation of checksum and bit lookup.
3. Conclusion In this paper we introduce a new method for reducing network traffic by compressing packets that are flowing
in network. We present use of network processors for achieving on-the-fly packet payload compression on a network. This research is underway, and we are evaluating different network processor architectures and a compression algorithm that can be efficiently mapped to data plane of selected network processor.
4. References [1]. Applied Micro Circuits Corporation http://www.amcc.com [2]. Intel Corporation http://www.intel.com/design/network/products/npfamily/index. htm [3]. C-Port network processors http://www.freescale.com [4]. Data Compression algorithms http://datacompression.info
