An Area-Efficient Noise-Adaptive Neural Amplifier ... - Semantic Scholar

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 1, NO. 4, DECEMBER 2011

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology Vikram Chaturvedi, Student Member, IEEE, and Bharadwaj Amrutur, Member, IEEE

Abstract—Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) tech, modunology. It can be biased adaptively from 200 nA to 2 . We also deto 3.9 lating input referred noise from 9.92 scribe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

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Index Terms—Alternating current (AC) coupling, bioamplifier, brain–machine interface (BMI), flicker, integrated, low noise amplifier (LNA), neural, noise, pseudoresistor, subthreshold.

I. INTRODUCTION

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HERE has been a great rise in interest in technologies for neuroscience and neuro-prosthetic applications. These necessarily ask for chronic recording of neural signals from a number of neurons [1]. Advances in micro-electromechanical systems (MEMS) technology has catalyzed the fabrication of miniaturized micro-electrode arrays (MEA), capable of accessing a number of neurons (100–1000) at once [2], [3]. In additions to MEAs, integrated electronics should also be able to withstand the challenges presented by such systems. The neural recording systems [4]–[6] should be fully implantable to record signals from freely moving primates. It requires low power and small area solution for each block of the system. It is difficult to implant a battery inside a body due to size constraint and bio-compatibility issues. Energy has to be supplied to the implant from outside, using inductive coupling [7]. This limits the energy available to the system. The power consumption must be Manuscript received May 28, 2011; revised September 30, 2011; accepted November 14, 2011. Date of current version February 01, 2012. This work was supported by the Department of Information Technology, Ministry of Communication and Information Technology, Government of India. This paper was recommended by Guest Editor P. Mohseni. The authors are with the Electrical and Computer Engineering Department, Indian Institute of Science, Bangalore 560 012, India (e-mail: [email protected]. ernet.in). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JETCAS.2011.2178731

Fig. 1. A typical N-channel neural recording system. VGA can compensate for any gain error in the preceding stages.

minimal as it may cause necrosis of the tissues even by a moderate heat flux [8]. The next generation of these systems must incorporate more on-chip processing capability to record from thousands of neurons and reduce the amount of data to be transmitted. To increase the number of channels, power per channel and area per channel have to be reduced. This motivates the need to design these systems in lower technology nodes where, unfortunately, low noise design is challenging [9], [10]. Fig. 1 presents an N-channel neural recording system. One of the most critical blocks of such a system is the low noise amplifier (LNA). LNAs must be low noise, low power, and low area. Out of various LNAs available in the literature, very LNAs meet all these requirements. The amplifier should be able to reject large dc offsets that may arise due to dc electrode current ( 100 pA) and high impedance at electrode–electrolyte interface [11]. Researchers have come up with many techniques to mitigate this problem. Some have tried dc coupling by accommodating the voltage swing at the input of the amplifier [11], [12]. However, it is difficult to use it in lower technology nodes, with lower supply voltages and smaller input common mode range. AC coupling or dc stabilization has achieved more popularity and acceptance over the years [13]–[16]. The challenge is to achieve a high pass pole around a few Hertz, to pass low field potentials (LFP), without using very large passive devices (resistance and capacitance) due to area constraint. The design of such large time constants in integrated circuit technology is difficult. Researchers have used off-chip components for this purpose earlier [9]. But the use of off-chip components increases the system size which is problematic for a fully implantable solution. The situation exacerbates when recording from a large number of neurons. Many of the previously published designs have used metal–oxide semiconductor (MOS)-bipolar pseudoresistors [13], [14] or MOS in weak inversion [15] to get high resistance in tera-ohm range [11]. Our first contribution is the use of NMOS in deep-depletion region, as pseudo-resistor, to get incremental resistance in the tera-ohm range with less distortion.

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CHATURVEDI AND AMRUTUR: AN AREA-EFFICIENT NOISE-ADAPTIVE NEURAL AMPLIFIER IN 130 nm CMOS TECHNOLOGY

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loop architecture is more suitable here due to its potential advantages. The absence of a stable dc supply [7], [24] necessarily asks for a fully differential architecture with high PSRR for a robust system. Section II discusses the design and implementation of the amplifier. Section II also explains the concept of optimum sizing of input transistors for a given input capacitance and input referred noise. Section III presents experimental results from a UMC 130 nm test chip and Section IV concludes the paper. II. NEURAL AMPLIFIER DESIGN We report a novel noise adaptive neural amplifier in UMC 130 nm 1P8M CMOS technology [25]. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input dc offsets at electrode–electrolyte interface. The power consumption can be adapted based on the background noise. The minimum and max, respectively. imum current consumption is 200 nA and 2 The proposed neural amplifier also minimizes input parasitic capacitance which can adversely affect the input referred noise of the amplifier and employs input coupling capacitance of only 5 pF. Fig. 2. Architectures of Neural LNA. (a) Closed loop neural LNA. (b) Open represents the input parasitic capacitance in both cases. loop neural LNA. C Large resistance R is emulated using pseudo-resistors.

Neural signals are typically low frequency signals (1 Hz– 7 KHz) and are mainly corrupted by the narrowband flicker noise in addition to the wideband thermal noise. Correct sizing and biasing of the devices is very important to mitigate the effect of electronic noise on the weak neural signals. The background noise at the input of such system is dynamic and varies typi[17]–[19]. The background noise is cally between 10 to 30 dependent on firing activity of the distant neurons and the effective electrode–neuron distance [20]. It is disadvantageous to deinput referred noise, when background sign a system with 2 . Our second contribution is the design of a neural noise is 30 amplifier that benefits from noise-power trade-off. In order to be able to monitor extracellular action potential (EAPs) separately from LFPs [21], the high pass cut-off frequency of the amplifier is made tunable. Neural amplifiers, other than being the most power hungry block, are the most area consuming block too ([22, Fig. 12]). The importance of area efficient design has increased with time, due to continuous increase in demand for data from more number of recording sites. But previous works have not really focused on reducing the area of the amplifier except [12]. Very large input transistor sizes are often used to reduce flicker noise have also below thermal noise. Large input capacitance been used in the amplifiers ( 15–50 pF), to compensate for (Fig. 2), noise accentuation due to parasitic capacitance which takes a lot of area [13], [14], [22], [23]. Our third contribution is the optimum sizing of the input pair of the amplifier to reduce the size of the input capacitance ( ) and hence reduce the area, without compromising with the high pass cut off frequency. The intricacies of the application have to be weighed upon to choose the correct amplifier architecture. We find that an open

A. Closed Loop versus Open Loop Neural Amplifier The architecture of the neural amplifier employed in [13] is popular and is accepted by many researchers [14], [22], [26]. It employs a capacitive feedback for ac signals and dc feedback through MOS-bipolar pseudo-resistor. The mid-band gain is given by the ratio of input and feedback capacitance. However the output is taken single ended which might suffer from power supply noise. In addition, a two stage amplifier is used which consumes additional power. The proposed architecture of the neural amplifier is shown in Fig. 2(b). We have used an open loop configuration over closedloop configuration [Fig. 2(a)] for the application, keeping into view its potential advantages. 1) Many neuroscientists have proven that the information is essentially encoded in the spike time-stamps and inter-spike intervals [24], [27]. Hence a small gain error due to process–voltage–temperature (PVT) variations is not detrimental to the information. Also the amplitude of the EAP is strongly dependent on the electrode–neuron distance which is not well controlled [28]. So having a highly deterministic gain in the neural amplifier does not really contribute. 2) Typically an electrode picks up signals from a number of neighboring neurons. These signals are discriminated using special algorithms known as spike sorting algorithms. These algorithms [29] use spike shapes to distinguish different neuronal sources and hence constrain distortion that can be introduced by the amplifier. Pseudo-resistors show good linearity and large resistance for small swings only [13], [26]. In feedback configuration [Fig. 2(a)], pseudo-resistor experiences larger signal swing across it and can cause more signal distortion. 3) Open loop amplifiers consume lower power than closed loop configurations for same accuracy requirements [30]. For same steady state error, an amplifier in closed loop configuration needs large open loop gain which requires

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more than one stage in deep submicron technologies. It may also need compensation for stable operation. 4) In pass-band, the transfer function from signal source to in Fig. 2) can be calculated as the input of the OTA ( (1) (2) Input referred noise of the amplifier is accentuated by the [13]. Closed loop inverse of the transfer function . However the configurations have larger . However it is imperative difference is small as to note that any feedback loop at the input of the LNA for offset or interference cancellation [31], [32] increases . Hence, noise increases more in such configurations over open loop configurations. This also demands the use as explained in Section II-D. of larger Looking at the above reasons, the use of an open loop architecture for neural recording application looks very advantageous. However, open loop architecture does suffer from inaccuracy in gain due to PVT variations. But if the error is not large, this can be compensated for by using a variable gain amplifier (VGA) in subsequent stages (Fig. 1). Open loop architecture also introduces larger offset than closed loop amplifiers. Fortunately, both these errors can be calibrated and corrected digitally [30]. Open loop amplifiers also cause larger distortion than closed loop amplifiers. But this is not a serious issue for this stage as the voltage swings encountered by it are very small.

Fig. 3. Pseudo-Resistors used to emulate large incremental resistance to achieve large time constant. They provide large resistance values for small swing across them. (a) Pseudo-Resistors. (b) Comparison between MOS-bipolar pseudo-resistor and deep depletion NMOS pseudo-resistor time . constants for C

= 10 pF

B. MOS in Deep Depletion as Pseudo-Resistor It is challenging to achieve large time constants ( 10 s) due in 130 nm techto small specific capacitance ( 2–3 nology) and resistance of the passive devices supported in integrated technology. Fortunately this application does not need high accuracy in the position of the high pass pole. The presence of a high pass pole between dc and lowest input frequency suffices. Pseudo-resistors are largely used to emulate tera-ohm resistance for the rejection of dc offsets at cell-electrode interface [13], [27]. Fig. 3(a) (ii) shows the MOS-bipolar pseudo-resistor used by many previous designs. It has worked well in larger technology nodes due to smaller leakage currents. But it is less efficient in deep sub-micron technologies where leakage currents are higher. Simulations [Fig. 3(b)] show a cut-off fre. Moreover, the swing that can quency of 100 Hz for be supported across it is only 0.2 V [13]. Usually 2–4 MOSbipolar devices are used in series to limit distortion introduced by them. We have proposed NMOS [Fig. 3(a) (i)] in deep-depletion and ) to emulate very high resisregion ( tance. It works as two reversed biased diodes in series (Fig. 4). Simulations indicate a cut-off frequency around 10 mHz for , which was 100 Hz for MOS-bipolar pseudo-resistor. It also supports larger swing ( 0.6 V) than MOS-bipolar pseudo-resistor with a distortion of only 0.3% THD. Fig. 3(b) shows the comparison between the two pseudo-resistors with for . Lower distortion in the pseudo-resistor is due to symmetric behavior of the device for

Fig. 4. Equivalent circuit of the pseudo-resistor. The charge density in the depletion region is controlled by the gate which causes modulation of the resistance with the bias.

both positive and negative swings (Fig. 4) whereas MOS-bipolar pseudo-resistor behaves differently for two swings [13]. Also inversion charge is a more nonlinear function of gate voltage than depletion charge in MOSFETs [33]. The resistance of the pseudo-resistor can be tuned through VBIAS. The charge balance equation [33] in MOSFETs is given as (3) where is charge on gate, is effective interface charge, is charge in the semiconductor under the oxide. and as constant and inversion charge as negligible Taking (4) where is the charge in depletion region. The gate terminal controls the charge density in the depletion region which in turn controls minority carrier diffusion current. It helps us modulate


Fig. 5. Tunability in high pass pole by varying VBIAS. An increase in VBIAS increases the high pass pole position.

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Fig. 6. Noise Contribution by input and load transistors at the input. The input ) is given as total output noise current PSD (I ), referred noise PSD (V ), divided by the square of the flowing into the output impedance (R kR transconductance (gm; in) of the input transistor.

the value of the resistance (Fig. 4) emulated by the pseudo-resistor. Device level simulations were also performed to study this phenomenon using Sentaurus Device [34]. The high pass cut-off frequency can be increased to reject LFPs and only pass EAPs. It is also helpful in attenuating the interference due to power line. Fig. 5 shows the tunable high pass pole for different VBIAS. As VBIAS is increased, the high pass cut-off frequency increases due to reduction in the incremental resistance of the pseudo-resistor. The high pass cut-off frequency to 1.4 kHz can be varied from 10 mHz at at . Amplifiers employing MOS-bipolar pseudo-resistors need an additional filter stage for tunability purpose and increase system cost. C. Low Noise OTA Design Neural amplifiers are one of the most power hungry blocks [22] in a neural recording system as they are large in number (one amplifier per recording site) and consume static power. The input referred noise must be very small for efficient acquisition of the signal which demands larger power consumption. Typi. cally the cortical EAPs magnitude varies from 20 to 200 The input referred noise of such amplifiers must be sufficiently lower than smallest input signal. The low noise design needs careful sizing and biasing of the input transistors and the load. We explain the basics of the noise optimization techniques in Section II-C1. 1) Noise Optimization: The input referred thermal noise voltage PSD and input referred flicker noise voltage PSD of a common source amplifier (Fig. 6) can be calculated as [13], [14], [22], [35] (5)

(6)

where is the thermal noise coefficient which depends on the effective mobility and channel length modulation. It is 2/3 for

Fig. 7. Schematic of the proposed neural amplifier. G 0 G architecture is used. I is used to reduce the transconductance of the load transistors and achieve voltage gain.

older technology nodes but is reported to be larger for submicron is Boltzmann Constant, T is the temperature technologies. in Kelvin [33], [36]. is technology dependent flicker noise co-efficient and is lower for PMOS. It is found to be increasing is oxide capacitance per unit gate with technology scaling. are width and length of the area, is the frequency, and transistor, respectively. 2) OTA Architecture: The schematic of the OTA is shown in Fig. 7. PMOS with large gate area is used as the differential input pair to reduce flicker noise contribution by it [37]. The noise contribution of different transistors can be reduced by referring to (5) and (6). Flicker noise contribution of input transistor pair can only be reduced by increasing the gate area. Both product and ratio of the input pair has to be increased, to increase gate area and transconductance respectively. This essentially pushes input transistor pair into the weak inversion region where, fortunately, it possesses maximum current effi) [38]. ciency ( The specific current is given by (7)

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TABLE I SIZING, GM, GM/ID FOR ALL DEVICES

Fig. 8. Input parasitic capacitance accentuates effective input referred of the amplifier. It causes attenuation of the signal from input to the gate of the input transistor, which makes the noise of the transistors look big. A is the voltage gain from gate to drain of the transistor.

TABLE II DOMINANT NOISE CONTRIBUTORS IN THE OTA

where is subthreshold slope coefficient, is thermal voltage [38], [33]. Inversion coefficient ( ) is defined by the ratio where is the drain current. Specific current for giving for input transistor pair is 11.4 . Other than the input transistor pair, all transistors have where current efficiency is inferior than that of weak inversion region [38]. This is a definite requirement for a low noise design. The thermal noise analysis [35] of the amplifier (Fig. 7) gives input referred noise as (8) where BW is the bandwidth. Transistors M3,4 and M7,8, being cascode transistors, do not add significant noise at low frequency [35]. Referring to (8), we can remove the noise contribution of transistors other than that of the input transistors by making . It is usually done by decreasing their ratio for a given bias current. But a limit is superimposed on this method by the maximum device length possible in a technology and output swing availability. We have further reduced the transconductance of load transistors by reducing bias used for this purpose. current through them. Fig. 7 shows This leads to drastic reduction in transconductance of the load, value. The values of W/L, gm, gm/Id giving large , are given in Table I. for different transistors, for Input transistors have which is nearly equal . The input-reto that in the weak inversion region is found to be 3.9 uV. The domferred noise for inant noise contributors in this are listed in Table II. Input pair is really the dominant noise contributor (77%) which supports would have our design technique. An ideal current source made the input-referred noise solely limited to that of the input transistor pair. Simulations indicate that the pseudo-resistors Ma and Mb add negligible noise. The dominant noise source in a diode (Section II-B) is shot noise. The shot current noise PSD where is the charge of is given as: is the average current flowing through the an electron and diode. The current through diode is small in the amplifier

as it is connected to the gate of the input transistor. Hence, it adds negligible noise. The advantage of this noise reduction technique is two-fold. Apart from the noise reduction, we were also able to achieve architecture in the amplifier. The voltage gain using voltage gain can be calculated as (Fig. 7) (9) Taking

, (10)

Equation (10) depicts that the voltage gain for the amplifier is given by the ratio of the transconductances of two PMOS devices. It partially cancels the detrimental effect of PVT varia. It also shows that whole input transconductance tions on does not translate to the voltage gain as some of the small signal branch. Effective input transconductance current is lost in where can be calculated as and are small signal impedances shown in Fig. 7. Note that except for branch, only PMOS transistors are used in the amplifier that reduces flicker noise content in the total output noise. Cascode architecture is used due to its superior current efficiency over the folded-cascode architecture. Transisare used to implement , as shown in Fig. 7. tors D. Input Capacitance Optimization Fig. 8 depicts input coupling in a typical ac coupled neural at the gate is amplifier. The effective parasitic capacitance given by (11) Assuming the transistor is operating in weak inversion region [39] (12) (13) where is the overlap length, is the width of the tranis the oxide capacsistor, is length of the transistor, and itance [40]. First term in (13) shows that is a function of


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input transistor sizing and increases linearly with gate area of the input transistor. Remaining terms in (13) increase with the width of the transistor and illustrates the detrimental effect of Miller capacitance in ac coupled neural LNAs. is defined as The transfer function (14) In pass-band, (15) which is the attenuation that input signal has to go through to reach gate of the input transistor. Hence, the effective input reof the amplifier employing an OTA ferred noise voltage can be calculated as with input referred noise PSD (16)

(17)

where is the resistance emulated by the pseudo-resistor, is the effective output conductance, and is the load capacitance for the amplifier. for an amplifier domThe input referred noise PSD inated by noise from input pair is given by (18) From (5) and (6) (19) (20) And for input transistors operating in subthreshold region,

(21) From (17) and (18), for a constant current consumption, bandwidth, and

(22) where , represents thermal noise floor. Thermal noise just acts as a pedestal for flicker noise, which must be decreased by operating in region and not over-designing bandwidth. Equahighest tions (13) and (22) indicates that a very aggressive increase ) of the input transistor, to tackle flicker in gate area (

Fig. 9. Optimum sizing of input transistor pair minimizes input referred noise for a given C . (a) Input referred flicker noise variation with the gate area of the input pair for different input capacitance C . (b) Input referred noise vari ) for input ation with the gate area in presence of thermal noise (V capacitance C .

= 5 pF

=2 V

noise, will adversely affect the low noise design. A bigger input capacitance is required, to compensate this increase in , effective noise, which is area inefficient. Hence for a given by finding . minimize The variation of input referred noise with the gate area is shown in Fig. 9(a) when flicker noise is the dominant noise . It also tells that a larger input coupling capacitance is required to achieve a lower input referred noise if the input transistors are not optimally sized. Fig. 9(b) depicts that optimum sizing of input pair becomes more important in presence of thermal noise, in addition to flicker noise. also becomes smaller in the The optimum area presence of thermal noise as the extra thermal noise demands smaller input attenuation and hence smaller input transistors. which is smaller than the previous We have used state of the art neural amplifiers [14], [22]. The gate area of input transistors for our design can be found in Table I which is close in Fig. 9(b). , to , and are extracted from simulations and used in Fig. 9. This analysis is valid when noise contribution of other transistors is made negligible via proper biasing of the input transistor should and sizing. The aspect ratio . The length is be optimized, to minimize thermal noise

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Fig. 10. Noise-power trade-off. Input referred noise of the amplifier reduces with increase in power consumption.

chosen based on the value, decided by the swing requirement at the drain. Minimum length is not chosen due to poor output conductance in deep sub-micron technologies. product due to Miller capacitance can The limit on the be relaxed by using cascoding. The attractive property of cascoding for low noise design is that cascode transistor does not contribute to the output noise at low frequencies [35]. But it does eat into the available output swing which is critical for submicron technologies employing lower supply voltage. Hence, we as a trade-off behave used cascoding in one side only tween input signal attenuation and output swing (Fig. 7). E. Noise-Power Trade-Off As shown in the Section II-C, the input referred noise of an OTA can be limited solely to the noise of input transistor using proper sizing and biasing. But other than intrinsic electronic noise of transistor devices, the background noise [18], [19] of the system also limits the dynamic range. The background noise primarily consists of firing activity of the neighboring neurons. The maximum detectable signal strangth can also vary due to change in electrode–neuron spacing. For an amplifier limited by thermal noise, the power con) are related sumption ( ) and input referred noise as (23) Equation (23) clearly states that to lower input referred noise, more power must be consumed and vice versa. Hence for smaller SNR case, we can reduce the power dissipation of the amplifier by using a lower bias current. It increases the input referred noise of the amplifier, but does not hamper the dynamic range of the system. The amplifier proposed can be , based on the dynamic range biased from 200 nA to 2 requirement, modulating input referred noise from 9.92 to , respectively. In Fig. 7, and are controlled to 3.9 vary the bias current. Fig. 10 shows how input referred noise varies with different bias currents.

Fig. 11. Chip fabricated in UMC 130 nm, 1P8M CMOS technology. (a) Die micrograph of the chip. (b) Block diagram of the system fabricated.

III. EXPERIMENTAL RESULTS The neural amplifier was fabricated in UMC 130 nm, 1P8M CMOS technology. Fig. 11(b) illustrates the two configurations of the amplifier that were fabricated: one using MIMCAP as Cin and another using P-MOSCAP as Cin. Since the input signal swing is very small, the distortion caused by putting MOSCAPs in signal path due to their large voltage sensitivity is expected to be negligible. The area of the amplifier was dominated by capacitors, followed by the input transistor pair. AMP block was used as a buffer with voltage gain 5 V/V. A die micrograph of the chip is shown in Fig. 11(a). A. Electrical Characterization 1) LNA With MIMCAP as Cin: Fig. 12 shows the measured ac response of the amplifier. The lower cut-off frequency and higher cut-off frequency are found to be 5 Hz and 7 KHz respectively for . The lower cut-off frequency is found higher than the simulated result which can be attributed to inaccurate modeling of the transistor and the leakage currents in the deep depletion region. But the cut-off is still lower than that of a MOS-bipolar pseudo-resistor. The mid-band gain is found to be 37 dB. Fig. 13 shows the PSD of the LNA output for and . Low frequency noise in Fig. 13 contains 50 Hz power line interference and flicker noise. Even a small pick up of 50 Hz power line [41], capacitively or inductively, is manifested in the output due to large voltage gain. Large input impedance of the amplifier worsens this condition. We made a makeshift Faraday cage using aluminum foil, minimized wire loop sizes and used twisted pair to reduce the interference by power line signal. It has reduced the amount of


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Fig. 12. Measured ac response of the amplifier for Vbias = 0 V and Vbias =

Vdd.

Fig. 13. PSD for LNA output employing MIMCAPs as Cin. , Fin = 500 Hz.

100 uV

V in

=

interference but still its not negligible. The remaining interference is removed while processing the data. PSRR is found to . This be 67 dB. The input referred offset is measured as 65 small value is due to the large size of the input transistor pair (with common centroid layout) and better matching in 130 nm technology. One drawback of using more advanced technology ) and open loop architecture is limited output swing (small and the amplifier achieves 1% THD for input swing of 400 . 2) LNA With MOSCAP as Cin: This configuration of LNA was fabricated keeping area advantage in the mind. MOSCAPs have higher specific capacitance than MIMCAPs. But it is not showing voltage gain as much as LNA employing MIMCAPs. We think it is because the capacitance emulated by the MOSCAP is not large due to some biasing problem. Hence, there is a possibility of large attenuation of the signal from the source to the gate of the input pair. We applied dc offset at and noticed improvement in the the input to modulate response. But the gain is still not appreciable. 3) Noise: Fig. 14(a) shows input referred noise PSD of the . Power line interference and its third amplifier for harmonic can be seen in the plot. The integration of the PSD till gives which is very close to the expected value (Fig. 10). The thermal noise floor

Fig. 14. Noise characterization. (a) Input referred noise PSD. The power line, its odd harmonics and flicker noise can be seen in it. (b) Input referred noise (output noise divided by the voltage gain). The rms value is = 5:5 V . V

is 48 . Fig. 14(b) shows measured input referred noise waveform. Noise efficiency factor (N.E.F) has been largely used to compare different neural LNA architectures. It is basically a figure of merit based on power-noise trade-off. It is defined as (24) For get art neural LNAs.

, and , we which is better than the present state of the [31] comes out to be 9.98.

B. In Vitro Experiment Performance of the proposed LNA is also validated using an in vitro experiment that emulates a neuron-electrode interface in a neural recording system. Fig. 15 explains the test setup used for the experiment. Epoxy-coated Tungsten electrode (UEWLFCSEEN1E from FHC ) was used as the recording electrode B and saline solution as the electrolyte. at 1 KHz. Artificial The impedance of the electrode is 5 spike signals were generated as linear combination of rising 1http://www.fh-co.com

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TABLE III SUMMARY AND COMPARISON OF THE MEASURED RESULTS

Fig. 15. Test set-up for in vitro testing of the chip. The PCB is shielded using thin aluminum foils to protect from interference from 50 Hz power line.

Fig. 16. In vitro acquisition of artificial EAP signal. Input (Fig. 15) is 8 .

mV

and decaying exponential waveforms by programming Agilent 33250A arbitrary waveform generator using Agilent 33503A BenchLink Waveform Builder software and fed to aluminum electrode A. An additional attenuation of 20 dB is introduced using SUHNER 6610.19.AA attenuators to bring the LNA input into the dynamic range of the amplifier. Fig. 16 depicts the faithful retrieval of the action potential from the saline solution. Table III shows the comparison of the measured results with previous state of the art works. IV. CONCLUSION We have presented a novel low-noise fully-integrated neural amplifier in UMC 130 nm, 1P8M CMOS technology. It can to 200 nA, modulating the be biased adaptively from 2 input referred noise, based on the dynamic range requirement. The amplifier can reject dc offsets at electrode–electrolyte interface. We have proposed NMOS in deep-depletion region as

pseudo-resistor which presents high incremental resistance and can withstand larger swing than MOS-bipolar pseudo-resistor. We employed an open loop configuration due to its potential advantages over closed loop architecture for the application. The amplifier shows a band-pass response with lower cut-off frequency being tunable. We also described a low noise design technique to reduce noise contribution of transistors other than the input pair. An analysis, for optimum sizing of the input transistors, to minimize input coupling capacitance size is presented. This significantly reduces area of the amplifier and will enable more number of recording channels for a given area. The input transistor pair is selectively operated in weak inversion to achieve maximum current efficiency for low noise design. In vitro experiments, to record action potentials from saline solution, were performed which validates the usefulness of the amplifier in neural recording system. The amplifier proposed consumes lowest power compared to the published designs till the date and has achieved large time constant of 0.2 s which makes it useful for other low frequency and low noise applications as ECoG, EEG etc. The amplifier presented in this paper achieves which is smaller than the present state of the art designs. ACKNOWLEDGMENT The authors would like to thank N. Mehta, P. K. Das, and Dr. S. P. Arun for help in in vitro experiments. REFERENCES [1] M. A. L. Nicolelis, “Actions from thoughts,” Nature, vol. 49, pp. 403–407, 2001. [2] F. Frey et al., “An 11k-electrode 126-channel high-density micro-electrode array to interact with electrogenic cells,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2007, pp. 158–593. [3] J. Aziz et al., “256-channel neural recording and delta compression microsystem with 3d electrodes,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 995–1005, Mar. 2009. [4] F. Shahrokhi, K. Abdelhalim, D. Serletis, P. Carlen, and R. Genov, “The 128-channel fully differential digital integrated neural recording and stimulation interface,” IEEE Trans. Biomed. Circuits Syst., vol. 4, no. 3, pp. 149–161, Jun. 2010. [5] C. Chestek et al., “Hermesc: Low-power wireless neural recording system for freely moving primates,” IEEE Trans. Neural Syst. Rehabil. Eng., vol. 17, no. 4, pp. 330–338, Aug. 2009. [6] B. Gosselin et al., “A mixed-signal multichip neural recording interface with bandwidth reduction,” IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 3, pp. 129–141, Jun. 2009.


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Vikram Chaturvedi (S’10) received the B.E degree in electronics and telecommunication from S.G.S.I.T.S, Indore, India, in 2006. He is currently working toward the Ph.D. degree in the Electrical Communication Engineering Department, Indian Institute of Science, Bangalore, India. He worked in ERC, Tata Motors Limted on remote keyless entry system from 2006 to 2007. He presented his research work in SRP session of ISSCC 2010. His research interests are in adaptive biomedical systems, energy-efficient data converters and RF front-end design. Mr. Chaturvedi is a recipient of the first student travel grants by SSCS as a recognition of early career accomplishments in the field of solid-state circuits.

Bharadwaj Amrutur (M’08) received the B.Tech. degree in computer science and engineering from Indian Institute of Technology, Bombay, India, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1994 and 1999, respectively. He has worked at Bell Labs, Agilent Labs and Greenfield Networks. He is currently an Associate Professor in the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore, India, working in the areas of VLSI Circuits and Systems.