(Garrison 2006) design, more specifically, evolutionary and self-adaptive circuit .... a software/hardware co-design. ... multiplier, 3 bit sequence detector, and self-repair circuit design for 4 bit ... Techniques Reference Manual (V10.1), Sep. 2008.
SDPS-2011 Printed in the United States of America, June, 2011 2011 Society for Design and Process Science
AN EDUCATIONAL ENVIRONMENT FOR EVOLUTIONARY AND ADAPTIVE CIRCUIT DESIGN Fan Xiong, Murat. M. Tanik Department of Electrical and Computer Engineering University of Alabama at Birmingham Birmingham, AL 35294, USA implement the Evolvable Hardware (EHW) circuit, as well as an interface between the evolvable circuit and the PC. The PC is used for designing an evolvable circuit, automatic generation of the interface logic, programming the FPGA’s and as a debug tool for the designed circuit. The presented environment is planned to be used in the regular educational process and the teaching project plans are summarized.
ABSTRACT In our desire to develop an educational environment, for evolutionary and adaptive circuit design at the university of Alabama at Birmingham we decided to use a Field Programmable Gate Array (FPGA) rapid prototyping environment. As the name implies, a Fieldprogrammable Gate Array is an integrated circuit designed to be configured by a designer in the field. Our goal in developing this educational rapid prototyping environment is that it can used by educators in multiple classes as the teacher sees fit. We feel that the environment can be used in many junior and senior level classes. Therefore, the primary goal was to build an FPGA-based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of evolvable hardware design. In this paper, the environment is described in detail, and the potential projects are described. It is our belief that, the inherent reconfiguration ability of FPGA provides an ideal platform to teach complex projects in a semester time frame. We plan to obtain additional funding to prepare a canned system to be distributed for applications elsewhere.
BACKGROUND The proposed environment is designed for higher level undergraduate/graduate course. Evolvable hardware is a relatively young research area. It is actively researched in the early 1990s. EHW is a bio-inspired approach which is a combination of evolutionary algorithms and reconfigurable hardware. There are two kinds of evolvable hardware. One is evolutionary circuit design, the other is adaptive circuit. The advantages lie in several aspects: 1) Circuit design for layman is possible. One person doesn’t have to have circuit design knowledge to design circuits. The “smart” evolutionary algorithm could do the job; 2) by exploring the search space, EHW could find solutions for those problems couldn’t or hard to be solved, or find an more optimal solution than traditional design; 3) Real design automation is possible. By only giving the inputs and outputs of the circuit, the circuit is automated generated.4) Evolvable hardware could adapt to the new environment by changing its own structure, circuit self-repair is possible. The concept could be illustrated by Fig. 1.
INTRODUCTION In this paper, we present a rapid prototyping educational environment for teaching evolvable hardware (Garrison 2006) design, more specifically, evolutionary and self-adaptive circuit design. Our primary goal was to build an FPGA-based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of evolvable hardware design. Since the system is intended to be used as an experimental and demonstration board to support higher level digital circuit courses, practices as well as research for graduate students. It is simple to use and completely supported by the Electronic Design Automation (EDA) software [ http://en.wikipedia.org/wiki/Electronic_design_automatio n] for automatic implementation of digital circuits. The education environment consists of a PC and the FPGA programmable board. The FPGA is used to
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Fig. 1 Evolvable hardware concept The evolutionary process is shown in Fig.2. The evolutionary algorithms generate random bit-sequences as chromosomes for circuit configuration. Circuit structures and parameters are encoded as chromosomes using one of several predefined encoding methods. A circuit is created based on the encoding method. A fitness value is then
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calculated and used to guide the evolutionary process. Fitness is an indicator of the quality of the solution expressed by a particular chromosome. This is an iteration process. The process stops when the stopping criteria reaches, that could be either a solution is found or the maximum generation reaches.
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Fig. 3 Xilinx XUPV2P board The FPGA Environment The education environment consists of a PC and the XUPV2P FPGA prototyping board, as shown in Fig. 4. The FPGA is used to implement the EHW circuit, and also an interface between the evolvable circuit and the PC. The PC is used for designing an evolvable circuit, automatic generation of the interface logic, programming the FPGA’s and as a debug tool for the designed circuit. An RS232 port facilitates the communication between the PC and the FPGA chip via an on-chip UART IP core module. Configuration and debugging of the FPGA is done through USB port.
Fig.2 Circuit evolutionary process
THE FPGA ENVIRONMENT FPGA selection Xilinx FPGAs are widely used in the EHW research community due to its partially reconfigurable features. Spantan-3 board could be use as an economic platform (www.xilinx.com/support/documentation/spartan-3.htm) although its resource is limited. XilinxTM XUPV2P Virtex-II Pro FPGA prototyping board (Xilinx 2008) is chosen as the result of tradeoff between available resource and cost. In addition, the FPGA has IBM PowerPC 405 hard core embedded. This feature is especially useful for this environment, since the hard core does not take any FPGA resource while Microblaze soft core takes some FPGA resources. The XUPV2P board is shown in Fig. 3. This device contains 13696 slices, 428Kbit distributed RAM, 428Kbit multiplier blocks, 2448 block RAMs, 8 Digital Clock Managers (DCMs), 2 PowerPC RISC embedded processors and 8 multi-gigabit transceivers. The maximum processor speed is 300MHZ.
Fig.4 XUPV2P platform Software platform The evolvable system is built using the XilinxTM Embedded Development Kit (EDK) software (version 10.1) (Xilinx 2008). The implementation can be viewed as a software/hardware co-design. The evolvable circuit
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The design of the EHWBlock uses a “building block” method. The EHWBlock is built by different logic blocks. The blocks could be multiplexers, LUTs, user defined logic operation blocks and flip flops.
design is written in VHDL and communicates with the PowerPC microprocessor using an Processor Local Bus (PLB) bus structure. The C code ran on the processor to generate the configuration chromosome used as a configuration bit-stream for the FPGA. The EDK basic system is shown in Fig. 5.
GRADUATE LEVEL USE EXAMPLES
This tool could be used in multidisciplinary engineering field, electrical engineering and biomedical engineering. Two graduate research projects are described in this section. Electrical engineering example A graduate research project has been done to explore the evolutionary design approach by applying information theory (Xiong 2011a). The mutual information is used as fitness function design, and genetic programming is used as the evolutionary algorithm. A parity 4 check circuit and a random minterm expression circuit were evolved to demonstrate the technique. More optimized circuit structure was obtained compared to traditional design method; also it was the first time to explore finding allNANS solutions to further optimize the circuit from integrated circuit physical design point of view. Biomedical engineering example A research project is going to explore an evolutionary approach as a personalized medical simulation tool in which cardiovascular system is modeled by digital logic circuit based on ECG and ABP signal samples as input and output respectively (Xiong 2011b). The research project investigates the feasibility of creating a digital system model for cardiovascular system. This is based on the understanding that ABP (Arterial Blood Pressure) waveforms are the cardiovascular system responses of the heart pumping impulses (ECG is the close representation of them). The ECG and ABP sample is shown in Fig. 7.
Fig. 5 The EDK basic system view Teaching Plans Four projects are planned to explore the two features of evolvable hardware: evolutionary circuit design and adaptive circuit design. Both combinational logic circuit and sequential logic circuit are taken into consideration. The four projects are: One bit adder/ subtracter, 2 bit multiplier, 3 bit sequence detector, and self-repair circuit design for 4 bit parity check circuit. All the experiments follow the same process. These circuits are all popular circuits in the EHW research community. All the experiments will follow the same system block diagram shown in Fig. 6. The difference of different projects lies in the EHWBlock. Based on the truth table of different combinational logic circuits, different evolvable hardware structures will be designed to carry out the experiments. The sequential logic circuit EHWBlock design is based on the state transition diagram. FPGA
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Fig.6 System Block for the environment
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XilinxTM Inc., 2008, EDK Concepts, Tools, and Techniques Reference Manual (V10.1), Sep. 2008 F. Xiong, Rafla, N.I., 2009, "On-chip intrinsic evolution methodology for sequential logic circuit design," Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on , vol., no., pp.200-203, 2-5 Aug. 2009 F. Xiong and M. M. Tanik, 2011, "An experiment on evolutionary circuit design using information theory." in Proc. IEEE Southeastcon 2011, Nashville, TN. March 2011, pp. 379-383. Fan Xiong, Susan Vasana and Murat M. Tanik, 2011, “A digital circuit model of cardiovascular system based on ECG (electrocardiogram) and ABP (arterial blood pressure) signals”, submitted to SDPS 2011.
This digital system breaks down ECG signal to monotonic pieces which models going through different stages of the heart pumping process and generates the outputs which match with the corresponding ABP signal. This model also can be used to gain insights about human heart function and cardiovascular system in further modeling. This research focuses on analyzing and modeling the cardiovascular system, using raw ECG (Electrocardiogram) and its corresponding ABP (Arterial Blood Pressure) signals. The analog information, ABP and ECG signals, were captured and converted into digital data that could be analyzed and modeled using digital devices. The two signals become data streams sampled simultaneously so that they can be modeled for an input output relationship. Then digital circuits were designed which piece wisely fit with the input-output relationship. In the exploratory experiments, three combinational circuits were extrinsically evolved using MATLAB. The evolved circuits could be downloaded to the FPGA board to see how closely the device can emulate the ABP output based on a know ECG input. Furthermore, the circuit could also be intrinsically evolved on the FPGA board.
CONCLUSION The FPGA environment is a good platform for higher level courses, senior design projects, and research purpose on evolvable hardware area. Students will explore multiple skill sets (hardware software co-design, FPGA design, microprocessor, evolutionary algorithms etc) to implement their project work. Multidisciplinary cooperation also becomes possible. research paper has published based on this platform (Xiong 2009). ACKNOWLEDGEMENTS Dr. Tomas C. Jannett from the Electrical and Computer Engineering Department, UAB gave us valuable suggestions on the revision of this paper. We appreciate his efforts.
REFERENCES Garrison W. Greenwood and Andrew M. Tyrrell,2006, “Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems,” Wiley-IEEE Press, 2006. XilinxTM Corp, 2008, Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual, Apr., 2008
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