An Efficient ABR Service Engine for ATM Network1 Youngin Choi, Sungho Kang Dept. of Electrical Engineering Yonsei University Seoul 120 -749, Korea
[email protected]
Song Chong Dept. of Electronic Engineering Sogang University Seoul 121 -724, Korea
[email protected]
ABSTRACT In recent ATM forum activities, considerable efforts have been focused on an Available Bit Rate (ABR) service, whi ch enables maximal link utilization in the ATM network. In this paper, we present the ABR service engine, which provides optimal hardware solution for all functions of an ABR service algorithm. To compute congestion control information, the ABR service eng ine has three parts. The first part is an ER engine which computes congestion control value. The second part is a Queuing Connection (QC) estimation unit which computes connection numbers used for ER computation. The final part is a cell decoder and encode r to handle cells. To implement the algorithm efficiently, this paper proposes many schemes. The ER is periodically computed in order to provide sufficient computation time. The size of an arithmetic architecture is reduced due to sufficient computation ti me. Thus, this scheme can achieve a low cell delay, when cells pass through the ABR service engine. Also, a QC corrector
can solve
the difficulty of the implementation of the QC estimation unit. The ABR service engine with a register control block efficien
tly
controls internal variables, and an IEEE 754 single precision is used for a precise computation. Therefore the architecture of the ABR service engine is very small in size and provides high speed. In addition, it realizes the computation of the conge
stion
control information without cell delay. Tthe ABR service engine is implemented and verified using an FPGA.
1
INTRODUCTION
Since most network applications cannot predict their own bandwidth requirements, they usually require a service that dynamically shares the available bandwidth among all active users. Such a service is called important characteristics of an efficient congestion control algorithm for
an ABR service [1], [2] . The
the ABR service include fast reaction to momentary
congestion due to bur st traffic, maximal link utilization, fairness, and low hardware complexity requirement. Various flow control schemes have been proposed for the ABR service, and they can be classified into two main classes, namely, the end-to1
This work was supported by Samsung Electronics Inc., Korea.
end rate-based schemes and the link-by-link credit -based schemes. In late 1994, the ATM forum selected the rate -based control [3]-[7] as the flow control scheme for the
ABR service due to its simplicity. The congestion control lies at the heart of the
general problem of traffic manage ment of high-speed switching networks such as the ATM. In this paper, a ABR service engine based on the simple, scalable and stable Explicit Rate (ER) allocation algorithm [3] which prevents an excessive queuing delay or a deadlock when the incoming traff ic to a specific link is heavier than the outgoing link capacity. In this paper , the rate -based control information of
the ABR service engine for congestion control is
an Explicit
Forward Congestion Indication (EFCI) marking , Relative -rate marking s and an Explicit Rate (ER) marking . The Relative -rate markings are a No Increase (NI) and a Congestion Indication (CI) . Many architectures that have been proposed are slow in performance speed and have complex I/O interface due to the access of external memory. In this paper, in order to arrive at a n high performance architecture, the algorithm reduces the complexity of computation, eliminate s the necessity of per -VC accounting and does not access a n external memory. Also, a periodical ER computation obviates a redundant arithmetic unit and diminishes originate from this scheme.
the occurrences of a cell delay. Most ideas for the design
If the ER computation start s when ever the Resource Management ( RM) cell arrives at the cell
decoder, a buffer will store cells duri ng the ER computation . A disadvantage of this scheme is that it make s the architecture complex and causes cell delay. Because the periodic scheme provides sufficient time for an ER computation, these problems can be solved . That is, a small arithmetic arch itecture in size can be adopted. Because the ER is stored after computing, the ABR service engine only writes beforehand the prepared ER in the RM cell without the cell delay whenever an RM cell arrives at the cell decoder. It can achieve simpler and faste r architecture without affecting performance. The remainder of this paper is organized as follows. Section 2 describes the algorithm using a pseudo-code on the ABR service. In Section 3, the architecture of the ABR service engine is presented. Section 4 p resents the implementation issues. In Section 5, the results are summarized. Finally conclusion is given in Section 6.
2
THE ALGORITHM OF THE ABR SERVICE ENGINE
It is very difficult to convert a software completely into a hardware, because a hardware has many limited conditions, such as computation delay, data type and timing , etc. So, the simple, scalable and stable ER allocation algorithm is modified in order to implement the ABR service engine into the hardware. The scheme for a periodical computation and
an additional hardware is
applied to the algorithm. Fig.1 shows the data flow of the ABR service engine. A pseudo-code is divided into four parts, namely,
the ER computation, the prediction of QCs, the comparison process for congestion control, and the wri
ting of the congestion
information in an RM cell. ' # # +
& () *
" #
&
!" # $% #
,- # * . % "(/ 01
Fig. 1 The data flow of the ABR service engine.
2.1
ER computation
Each RM cell contains a rate at which the sender would currently like to transmit data. Such a value is called an Explicit Rate (ER). As the RM cell passes through to the receiver, the congested switches may reduce the ER. That is, the ER value is used to limit the Allowed Cell Rate (ACR) of a source to a specific value. The pseudo code for t he ER computation is shown in Fig.2. if ( every T period ){
QL ave = sum of queue lengths / queue count if ( gTH < queue length ){ if ( system start ){
A = A0,
B = B0
A = A1,
B = B1
} else {
} } QC temp = QC estimation + QC corrector
ER = ER pre −
2 B A (QL ave − q T ) (QL ave − QL ave pre ) − QC temp QC temp
ER is limited between link-speed and 0 }
Fig. 2 The pseudo-code for ER computation.
A QLave is the average of the queue lengths during T seconds , which is a multiple of unit time that takes a cell to pas s through the ABR service engine. A and B are coefficients for the ER formula and have two value s in order to react quickly when starting the ATM, and gTH is the criterion in selecting of A and B. q T is the target of the queue length which must be maintain ed. ERpre is the ER value computed by the ER engine at a previous time. Since the ER is computed by the periodical scheme, the QC correction process is added.
2.2
The Queuing Connection (QC) prediction
The pseudo-code for QC l computation is given in Fig.3. A QC represents the number of the connection that can cause queuing in each switch. The basic interval of all parts for a QC prediction is W. A detailed prediction originates from QC
l,
the source
number of QC. In the prediction phase, the number of forward RM cells is (W × RM(CCR))/N per connection at the input. N RM RM is the number of cells per forward RM cell. After identifying a relation with a queuing connection, the QC can be predicted by continuous summations of inverse values of the average of th e forward RM cells for all connections. CCR and MCR are obtained from the RM cell, and δ×ER is delivered by the ER engine. δ is called a comparison margin and is constant between 0 and 1. if ( receive the forward RM cell sent by source ){ if ( RM (CCR)- RM (MCR) > ER engine (
QCl = QCl_previous +
3
× ER) ){
NRM W × RM (CCR)
} }
Fig. 3 The source number (QC l) computation. If ( every W period ) { QC temp = QC previous + QC corrector QC = QC temp
+ QC l
(1-
),
0
