An Efficient Multiplexer in Quantum-dot Cellular Automata Bibhash Sen1 , Manojit Dutta1 , Divyam Saran1 , and Biplab K Sikdar2 1
CSE Dept, National institute of Technology Durgapur, CST Dept,Bengal Engineering and Science university, shibpur, email:
[email protected] , {nitdmono,divyamsaran}@gmail.com1 ,
[email protected] 2
Abstract. Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state-of-the-art CMOS due to its extra lowpower, extremely dense and high speed structures at nano-scale. Additionally, multiplexer plays an important role for design of digital circuits. Although few designs exist, investigations on the effectiveness of QCA technology in multiplexer based digital design in terms of area overhead, speed and complexity are limited. This paper proposes a novel design of 2:1 multiplexer in QCA, targeting the development of a modular design methodology for complex ALU structures. Comparison of results illustrates the significant improvements in our proposed design as compared to that conventional approaches. Further, the proposed architecture of multiplexer is robust and sustainable to high input frequency, as compared to other designs.
Keywords: Quantum-dot Cellular Automata (QCA), Multiplexer, Nanotechnology, Arithmetic Logic Unit (ALU)
1
Introduction
The current digital design techniques target energy efficient realization of complex CMOS logic circuits. However, the researchers face the physical limits of conventional CMOS technology. The QCA (Quantum-dot Cellular Automata) is considered as a promising technology to meet energy efficient design target [1]. It has major advantages such as low power consumption, high speed and high compaction density. The fundamental unit of QCA based design is the 3-input majority gate [1]. Since the majority gate is not functionally complete, the majority gate with inverter, called M I, is used to realize the QCA designs. The utmost necessity in QCA based design is to address the issue of its high susceptibility to high error rate at nano scale. This open up new research to improve the design of various QCA structures such as memory and multiplexers [2]. The multiplexer plays an important role in variant circuit designs. For example, the realization of FPGA and memory circuits. However, the number of
2
QCA cells, effective area and speed required to realize a QCA design limit the performance of such design. In this context, this work investigates the realization of a 2:1 multiplexer in QCA and proposes a novel design. The performance of proposed multiplexer has been compared with the performance of all other recent designs [2]-[3] in terms of area, speed and complexity. Effectiveness of proposed multiplexer is studied through the realization of basic logic elements such as XOR, D-latch, 4input AND gate and the arithmetic logic unit. Comparison of results illustrates significant improvements as compared to that of existing realizations. In Section-III, the details of proposed 2:1 multiplexer are introduced. In Section IV, the cost-effective designs with the proposed multiplexer are reported. The next section provides the basics of QCA.
2
The QCA Basics
Localised Electron
Junction Tunnel
(a) Structure of a QCA Cell
clock clock zone 3 zone 2
Quantum Well
clock zone 1
Tunnelling Potential
clock zone 0
A quantum dot is a region where an electron is quantum-mechanically confined (F ig.1(a)). A quantum cell consists of such quantum dots at each corner of a square and contains two free electrons [1]. The electrons can quantummechanically tunnel among the dots and settle either in polarization P=-1 (logic 0) or in P=+1 (logic 1) as shown in F ig.1(b). Timing/synchronization in QCA is accomplished by the cascaded clocking of four distinct and periodic phases [1] as shown in F ig.1(c).
P = −1 P = +1 Binary ’0’ Binary ’1’ (b) Representing a binary digit with the help of two different polarization of the localized electronics
Release
Switch 0
Relax
Hold T/4
T/2
3T/4
T
(c) Clocking
Fig. 1. A QCA cell and clocking Table
The basic structure realized with QCA is the 3-input majority gate, MV(A,B,C) = Maj(A,B,C) = AB+BC+CA (Fig.2). Majority gate can be programmed such that it functions as a 2-input AND or a 2-input OR by fixing one of the three input cells to p = -1 or p = +1, respectively as shown in its truth table in (Fig.2). Inverter realized in two different orientations is shown in Fig.3(a). In QCA based logic implementation, two kinds of QCA wires are possible. Fig.3(b) describes the only allowable wire crossing in QCA based design. It requires two different orientations, a 90o (×-cell) and a 45o (+ -cell) structure.
3 A
B
00 11 00 11 00 11 00 11 11 00 00 11 0 1 00 11 0 1 0 1 00 11 0 1 00 10 11 01 10 00 11 01 0 1 00 0 0 11 1 00 1 11 0 1 11 00 11 00 00 11 00 11 C
F
A B C
M
F = AB + BC + CA
F
A
B
C
F
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1
AND Logic A fixed to 0 OR logic A fixed to 1
Fig. 2. A majority gate and its Truth Table
However, manufacturing nano-scale cells with two different orientations is costly.
1 00 0 1 00 0 1 0 11 00 11 00 11 11 11A’ 00 11 00 11 00 11 00 11 00 11 0 00 1 0 1 1 0
A 0 1 0 1 11 00 11 00
11 00 1 11 0 1100 00 1 0 1100 100 0 11 00 11 0 1 0 1 1 0 00 11 0 A’ 1 A 0 100 111 1 0 0 1 0 00 11 0 1 011 1 00 0 1 00 11 0 1 0 1 00 1 11 0 1 0 (a)Inverter
00 11 1 0 00 11 0 1
1 110 00 11 00 0 1 +−cell 00 11 0 1 00 11 0 1 1 0 00 100 0 1100 11 0 100 1100 11 0 1 11 1100 00 11 0 100 1100 11 0 100 11 X−cell 00 11 00 11 1 0 ’X’−cell 00 11 0 1 00 11 0 1 11 ’+’−cell 00 0 1 (b)Wire−crossings
Fig. 3. W ire − crossing and inverter
3
The Proposed Multiplexer Design
A multiplexer makes it possible for several signals to share one expensive device or other resource. The output expression for a 2:1 multiplexer is, Out = I1.Sel + I0.Sel
(1)
where I0 and I1 are the two inputs, Sel is the select line. This can also be represented considering the majority gates (basic elements of QCA logic), F = M 3(M 1(Sel, I0, 0), M 2(Sel, I1, 0), 1)
(2)
It is apparent from (2), that a 2:1 multiplexer can be realized with three majority gates and one inverter. Efforts have been taken to realise multiplexers in QCA [2, 3, 5–7]. This section introduces a cost effective QCA multiplexer structure with the target to achieve betterment in terms of effective area, leading to improved device density and speed. The simple structure shown in Fig.4(a) is the realization of multiplexer with QCA majority gates as described in expression (2). The
4 Clock Zone 0 Clock Zone 1 Clock Zone 2
Sel I0 M1 −1
I1
1
M3
F
M2 (b) Logic Diagram
Fig. 4. Proposed QCA multiplexer (a) cell layout (b) logic diagram
Fig. 5. Simulation result of 2:1 multiplexer
corresponding schematic circuit diagram is shown in Fig.4(b). The simulation result for the multiplexer is shown in Fig 5. All logic elements in Fig.4(b) are coloured indicating the phases used for changing can easily be noted that the clocking phases are traversed in the proper order (0, 1, 2, 0, 1, 2...) so that the required clock phases are always adjacent to each other to allow correct signal propagation. A comparative analysis of the proposed 2:1 multiplexer, with respect to the existing designs is reported in Table 1. It is inferable from Table 2 that the proposed multiplexer can achieve significant improvements over the existing ones.
Table 1. Comparison of recent 2:1 Multiplexer designs Parameters In[2] In[3] In[4] In[5] In[6] Proposed Mux Complexity(Cell Count) 88 66 46 36 27 19 Area(in µm2 ) 0.14 0.14 0.08 0.06 0.03 0.02 Latency(in Clock cycle) 1 1 1 1 0.75 0.75
5
Table 2. The proposed multiplexer improvements in comparison to other previous designs Design Improvement Parameters In[2] In[3] In[4] In[5] Complexity(Cell Count) 78.40% 71.21% 58.69% 47.22% Area(in µm2 ) 85.71% 85.71% 75% 66.66% Latency(in Clock cycle) 25% 25% 25% 25%
In[6] 29.62% 33.33% Equal
Fig. 6. (a) Mux with enable input (b) Quadruple 2:1 Mux
Fig.6(a) describes a 2:1 multiplexer with an enable input. For normal operation of the multiplexer, the enable input is set to high otherwise the output will be always zero. The design, with a cell count of 39, covers an area of 0.04 µm2 [8]. Multiplexers can be combined with common selection inputs to obtain multiple-bit selection logic. As an illustration, we propose a quadruple 2:1 multiplexer (Fig.6(b)). The design, consisting of 111 cells, covers an area of 0.12 µm2 . Fig.7 is a 4:1 multiplexer with its functionality based on the proposed 2:1 multiplexer. With a cell count of 80, the design covers an area of 0.1 µm2 . Similarly, larger multiplexers (8:1, 16:1 and so on) can be constructed using the proposed 2:1 multiplexer.
4
Cost Effective Design With 2:1 Mux
Several logic-gates based on the proposed 2:1 multiplexer are designed. As an illustration, the designs of a two input XOR-gate, a D-latch and a four input AND gate are shown in Fig.8(a), Fig.8(b) and Fig.8(c) respectively.
6
S1 S0 out 0 0
0 1
I0
1 1
0 1
I2
I1 I3
Fig. 7. 4:1 Mux using proposed 2:1 mux
Fig. 8. (a) 2-input XOR (b) D-Latch (c) 4-input AND Logic
A performance analysis of these gates, with respect to the existing designs is presented in Table 3. It is evident from Table 3 that the proposed multiplexer leads to cost effective design. A multiplexer, with n-1 selection inputs (where n ≥ 2), can realize any Boolean function of n-variables [9]. The selection inputs of the multiplexer are connected to the first n-1 variables and the remaining single variable is used to manipulate the data inputs of the multiplexer to obtain the desired n-variable function. This feature of multiplexer is utilised to design an ALU. The two inputs, X and Y, of the ALU are connected to the selection lines (S0 and S1) of the 4:1 multiplexer and four data input lines of the 4:1 multiplexer are used as control inputs of the ALU. Some extra logic is used to incorporate the Carry/Borrow output. The proposed ALU implements 10 basic arithmetic-logic functions.The QCAimplementation of the proposed ALU and its design-schematic are shown in Fig 9(a) and Fig 9(b) respectively. The functions F1 gives carry-out of a half adder and F2 gives borrow-out of a half-subtractor. The QCA-design of the proposed
7 Table 3. Performance analysis of proposed Mux with previous designs Parameters
XOR Gate D-Latch 4-input AND in[6] propo- Improve- in[6] propo- Improve- in[7] propo- Improvesed Mux ment(%) sed Mux ment(%) sed Mux ment(%) Complexity 29 27 6.89 36 26 27.77 25 19 24 (# Cell) Area 0.03 0.02 33.33 0.03 0.02 33.33 0.03 0.02 33.33 (in µm2 ) Latency 1 0.75 25 2 2 equal 1 1 equal (in C.Cycle)
F1 0 A 0 1 0 C 0 1 B
F0
0
S1 F2
1 0 D
S0
Clock zone o Clock zone 2
Clock zone 1 Clock zone 3
Fig. 9. (a)ALU Cell-layout (b) Schematic Logic
ALU consists of 115 cells and covers an area of 0.13 µm2 [8]. The functions realised in the ALU are shown in Table 4. The proposed multiplexer structure and the other logic circuits are simulated using QCADesigner[8].
5
Conclusion
In this paper a novel architecture of a 2:1 multiplexer in QCA is presented considering its primitives (majority voter). The resulting design consists of 19 cells covering an area of 0.02 µm2 only which is substantially lower than existing ones. Complex modular design like quadruple 2:1 mux, XOR gate, latch and 4input AND logic using this 2:1 mux as an elementary building blocks is proposed. It is inferable from experimental results that the proposed multiplexer achieved significant improvements in QCA circuits over existing ones in terms of design complexity, effective area and latency. Besides these improvements, one of the main contributions in this paper is designing robust multiplexer based ALU in
8 Table 4. Different logic function of ALU A 0 0 0 0 0 0 1 1 1 1 1 1
B 0 0 0 1 1 1 0 0 0 1 1 1
C 0 0 1 0 1 1 0 0 1 0 1 1
D 0 1 1 1 0 1 0 1 0 0 0 1
F0 0 S0.S1 S0 S1 S0⊕S1 S0+S1 S0 + S1 S0 S1 S1 S0 S0.S1 1
QCA which implements ten basic arithmetic-logic functions including carry and borrow needed in arithmetic operation.
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