An FPGA-Based Optical Transmitter Design Using ... - OSA Publishing

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 25, NO. 10, OCTOBER 2007

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An FPGA-Based Optical Transmitter Design Using Real-Time DSP for Advanced Signal Formats and Electronic Predistortion Philip Watts, Student Member, IEEE, Robert Waegemans, Madeleine Glick, Member, IEEE, Polina Bayvel, Senior Member, IEEE, and Robert Killey, Member, IEEE

Abstract—Advances in the performance and flexibility of future optical networks will be brought about through the use of high-speed digital signal processing (DSP) for the generation of advanced optical signal formats and the compensation of transmission impairments. The use of field-programmable gate arrays (FPGAs) to implement experimental transceivers employing novel DSP techniques is attractive, as they are of low cost and are reprogrammable. In this paper, the design of a reprogrammable FPGA-based 10-Gb/s optical transmitter using real-time DSP is described and assessed through simulation. Using a single Xilinx Virtex-4 FPGA, digital filtering based on lookup tables with up to 12-bit addressing could be implemented. We also present, for the first time, a simulation technique using industry-standard digital design simulation tools (Mentor Graphics Modelsim) in combination with a simulation of analog microwave components, optical transmission, and bit-error-rate estimation to assess the performance of the full transmission system. This simulation technique is used to demonstrate 10-Gb/s transmission over 550 km of standard single-mode fiber (SSMF) using electronic predistortion (EPD) and the generation of optical single sideband signals. A proof-of-principle experiment is described in which a single 10.7-Gb/s Mach–Zehnder modulator drive signal with 4-bit amplitude resolution and 1-sample/bit temporal resolution was generated. This was used as the input to Monte Carlo simulations to assess EPD transmission performance over SSMF links of up to 640 km. Index Terms—Chromatic dispersion compensation, digital signal processing (DSP), optical modulation, optical transmission.

I. I NTRODUCTION

A

LTHOUGH digital signal processing (DSP) is widely used in wireless systems, its use in optical communications has been limited due to high bit rates. However, the continued rapid development of complementary metal–oxide–semiconductor digital technology has led to increasing interest in DSP for optical transmission, which will allow major advances in the performance and flexibility, and Manuscript received August 23, 2006; revised May 9, 2007. This work was supported in part by the U.K. Engineering and Physical Sciences Research Council and the European Union e-Photon/ONe and NOBEL2 projects. The work of P. Watts was supported in part by an IEEE LEOS postgraduate student fellowship. P. Watts, R. Waegemans, P. Bayvel, and R. Killey are with the Optical Networks Group, Department of Electronic and Electrical Engineering, University College London, WC1E 7JE London, U.K. (e-mail: [email protected]; [email protected]; [email protected]). M. Glick is with Intel Research Pittsburgh, Pittsburgh, PA 15213 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JLT.2007.904028

reductions in the cost, of future photonic networks. Forwarderror correction is an example of DSP, which operates only on detected bits, while other techniques require analog-to-digital or digital-to-analog conversion with resolutions in the range of 3–5 bits, including maximum-likelihood sequence estimation [1], phase/polarization diversity reception [2], generation of advanced signal formats such as optical single sideband (SSB) [3], and electronic predistortion (EPD) [4]–[6]. Examples of integrated circuit implementation at 10 Gb/s have been announced in recent years [7], [8]. While custom integrated circuit designs offer optimum performance, the field-programmable gate array (FPGA) is a useful alternative tool for experimental work in DSP as it is of low cost and is reprogrammable. In the latest digital systems, high-speed serial interfaces are increasingly being used for chip-to-chip signaling in place of parallel buses to reduce signal skew and pin numbers. For this reason, FPGAs with 3–10-Gb/s input/output capabilities are in production or under development [9], [10]. Given current trends, it is likely that high-speed serial transceivers will become the norm for future FPGAs. This capability allows the latest FPGA to be used for high-speed DSP operating on signals at standard optical line rates such as 10 Gb/s. In this paper, we describe, for the first time, the design of a 10-Gb/s optical transmitter with real-time signal processing using an FPGA. The transmitter can be rapidly reprogrammed to compare advanced optical signal formats [11], implement EPD, or investigate novel DSP techniques on optical signals without making any changes to the microwave or optical components. In Section II, the general concept of predistortion transmitters based on lookup tables (LUTs) is discussed. Then, in Section III, a design based on the Xilinx Virtex-4 FPGA is presented, offering 10-Gb/s optical signal generation with 2 sample/bit (Sa/b) time resolution and 4-bit amplitude resolution. In Section IV, a simulation technique is presented using industry-standard digital design simulation tools (Mentor Graphics Modelsim) in combination with a simulation of the analog microwave components, optical transmission, and bit error rate (BER) estimation (using Matlab) to demonstrate the performance of the full transmission system. This technique is used in Section V to predict the EPD performance of the transmitter design. The simulation technique is used to generate optical SSB signals in Section VI as an example of synthesis of advanced modulation formats. Finally, in Section VII, a

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Fig. 1. Digitally programmable transmitter concept using (a) a Cartesian (triple) or (b) a dual-drive MZM.

required to overcome chromatic dispersion in optical fiber was provided in [12]. The Cartesian MZM has separate ports for controlling the in-phase and quadrature components of the optical signal. For predistortion in optical communications, it has the advantage that only linear filtering is required to overcome linear fiber impairments, such as chromatic dispersion [13]. However, nonlinear filtering is required for compensating fiber intrachannel nonlinearities. In addition, it has been shown that the use of the Cartesian MZM reduces the errors due to limited DSP resolution [14]. The dual-drive MZM has the advantages of lower complexity, cost, insertion loss, and drive power requirements [13]. Many modulation formats can be conveniently created using small LUTs or low-complexity transversal filters. However, nonlinear filtering is required for predistortion of both linear and nonlinear fiber impairments. The transmitter architecture that is described in this paper can use either a Cartesian or dual-drive MZM. Filtering using LUTs was selected to allow any arbitrary linear or nonlinear response to be generated. III. T RANSMITTER D ESIGN A. Top-Level Design

Fig. 2. LUT used to create arbitrary, including nonlinear, responses.

proof-of-principle experiment is described in which the currently available Virtex-II Pro FPGA is used to generate a 10.7-Gb/s Mach–Zehnder modulator (MZM) drive signal with 4-bit amplitude resolution and 1-Sa/b temporal resolution. By using the experimentally generated EPD drive waveforms as the input to a Monte Carlo transmission simulation, it is shown that the additional implementation penalty of this type of transmitter is less than 1.5 dB.

II. T RANSMITTER C ONCEPT The concept of the transmitter that was described in this paper is shown in Fig. 1. Either a Cartesian (triple) MZM or a dual-drive MZM can be used to modulate the amplitude and phase of the transmitted optical signal. This allows the input bit stream to be converted to any signal format or predistorted to overcome transmission impairments. In both cases, the input bit stream is digitally filtered and converted into two analog signals that are used to drive the two ports of the MZM. Digital filtering can be either linear or nonlinear, depending on the requirements of the application. A transversal filter is an example of linear filtering. On the other hand, a LUT can be programmed to produce arbitrary, including nonlinear, responses [6]. As shown in Fig. 2, the LUT is stored in memory as 2n words, addressed by n consecutive bits of the input bit stream sequence. Each word contains m bits, where m is the resolution of the digitalto-analog converter (DAC) multiplied by the oversampling ratio. A comprehensive analysis of the LUT memory size that is

Fig. 3 shows the top-level design of the proposed transmitter [15]. An MZM is driven by two drive signals d1 and d2 . For both d1 and d2 signals, eight of the FPGA serial outputs (each nominally 10 Gb/s) are time-division multiplexed to four 20-Gb/s signals. A DAC consisting of attenuators and a 4 : 1 power combiner generates the analog drive voltages, as demonstrated experimentally in [16]. B. FPGA Design The FPGA design was based on the Xilinx Virtex-4 4VFX100 device having 20 serial transceivers with up to 10.3-Gb/s bit rate and 376 × 16 kb blocks of random access memory (RAM). The VHSIC Hardware Description Language (VHDL) was used for circuit specification. Fig. 4 shows a block diagram of the FPGA design. The 4VFX100 device has ten transceivers along the left-hand side of the chip and the remaining ten on the right-hand side. Each side has separate dedicated low-jitter clock inputs for the transceiver serializer/deserializer circuitry. In this design, eight transmitters on the left side of the chip are used to generate the d1 signal, and eight transmitters on the right side are used for the d2 signal. The receivers are disabled and play no part in the design. To ensure synchronization of all transmitters, a single low-jitter 312.5-MHz reference clock is used to drive both sides of the chip. In addition to the serializer clock, two other clocks are derived from the left reference clock: 1) a 312.5-MHz clock to drive the transmitter physical coding sublayer of all the transmitters and 2) a 156.25-MHz clock (subsequently called the DSP clock), which drives the pattern memory, registers, DSP, and transmitter interfaces for both d1 and d2 channels. A 50-MHz clock is used at start up for transmitter phase-locked loop (PLL) calibration and for generating the necessary reset signals.

WATTS et al.: FPGA-BASED OPTICAL TRANSMITTER USING DSP FOR ADVANCED SIGNAL FORMAT AND EPD

Fig. 3.

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Top-level transmitter design showing clock sources, FPGA, microwave, and optical components.

The data input to each transmitter is of 64 bits and parallel, requiring data to be stored and processed in 64-bit blocks. A pattern memory contains the bit sequence to be transmitted in 64-bit words. Words are read out from the pattern memory in turn once per DSP clock cycle into the current word register. For each drive signal, processing is performed using 64 identical RAM-based LUTs, each addressed by n consecutive bits of the sequence. The 64 LUTs require 64 + n − 1 input bits, which are made up of the current 64-bit word and n − 1 bits from the previous word. Each LUT provides the required outputs for one transmitted bit (two samples at 4-bit resolution, giving eight output bits). Hence, as shown in Fig. 5, the first LUT provides the first bit of each of the 64-bit words that were sent to the transmitters. Note that, in a custom design, a more efficient implementation is multiple-port RAM, allowing multiple simultaneous read operations on the same LUT and, hence, avoiding the need for duplicated LUTs. The LUTs send 64-bit parallel data to the transmitter blocks for conversion to serial output. This application requires the skew between all transmitter outputs to be reduced to a small fraction of the bit period. The built-in circuitry on the FPGA does not completely eliminate skew [10]. In addition, skew due to differences in off-chip routing (path lengths between FPGA and connectors on the printed circuit board, cables lengths, and variations in microwave component group delay) must be eliminated. In this design, a skew of more than one bit period is corrected by delay circuits that are implemented on the FPGA at the input to each transmitter, as shown in Fig. 6. A skew of less than one bit period is removed by external microwave phase shifters on each serial output (Fig. 3). The authors are aware that the Virtex 4 FPGA transmitters suffer from reset-dependent skew; in other words, each time the FPGA is switched on, the skew of each transmitter can vary by an integer number of bits. As the variable skew is of integer bit period, no changes to the phase shifters will be required, but an automated alignment

algorithm will be required. In Section VII, we demonstrate a 10.7-GSa/s transmitter based on the design presented here but using the Virtex-II Pro FPGA and 4 : 1 external multiplexers. In this experimental demonstration, neither the FPGA nor the external multiplexers display reset-dependent skew. C. FPGA Design Implementation The Xilinx ISE (version 8.1) package was used for implementation of the FPGA design, including synthesis of the VHDL design code, mapping of the design to FPGA circuit blocks, and the place-and-route operation. A key parameter for the transmitter, particularly, for EPD applications, is the maximum LUT size, which is limited by the amount of RAM on the FPGA and the need for duplicated LUTs. The hard-wired RAM on the FPGA is in 376 blocks, each storing 16 kb. A single RAM block is sufficient to implement a LUT with 11-bit addressing (n = 11). In this case, 128 RAM blocks are used in the FPGA design. Using two RAM blocks per LUT (256 RAM blocks in total), 12-bit LUTs (the maximum possible with this FPGA) can be implemented. Both 11- and 12-bit designs were produced. A key parameter demonstrating a successful design is the timing margin on the DSP clock, which controls all the processing functions. The maximum delay (logic and path) in the DSP clock domain when using 11-bit LUT addressing was found to be 3.4 ns, compared to the clock period of 6.4 ns, giving a 46.9 % timing margin. Using 12-bit LUT addressing, the maximum delay is increased to 3.8 ns, reducing the timing margin to 40.1 %. In both cases, only 11% of the total programmable logic resources of the FPGA were used, allowing other DSP functions such as transversal filters or coding to be implemented at a later date. RAM is also required for the pattern memory. It was found to be possible to increase the pattern memory to 213 64-bit words without reducing the timing margin. This uses 29 RAM blocks and is sufficient to hold a 219 bit length sequence.

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Fig. 4. Block diagram of the FPGA design.

Table I shows the performance results and resource usage on the FPGA using the maximum 12-bit LUTs and 213 word pattern memory. IV. S YSTEM S IMULATION A. Transmitter Simulation The transmitter design that was described in Section III was simulated as follows: a postlayout simulation, which uses realistic timing data for the 4VFX100 chip, was carried out using Mentor Graphics Modelsim software. (Modelsim provides an accurate simulation of all the digital components on the FPGA. However, it cannot be used to simulate analog functions such as the PLLs, which control the transmitters. For this reason, the simulation does not include the deskew procedure that

was described in Section III-B and experimentally verified in Section VII.) The event-driven Modelsim output for each transmitter was imported into Matlab for all subsequent simulations. First, the event-driven data were converted to 64-Sa/b time-driven arrays. The 2 : 1 multiplexers were modeled as ideal selectors with the outputs modeled as raised cosine pulses with 20-ps rise and fall times. The phase shifters, attenuators, and combiners were all modeled as ideal components. The amplifiers were assumed to have a fourth-order Bessel filter response with a −3-dB bandwidth of 18 GHz. The electric field from the triple MZM [Fig. 1(a)] was assumed to be

Eout =

π · d2 π · d1 Ein − i · cos cos 2 Vπ Vπ

(1)


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beat noise can be expressed in terms of measurable quantities as [17] σsig−ASE (t)2 =

2R · I(t) · Iav · Be OSNR · RBW

(4)

where Iav is the mean current, Be is the receiver electrical bandwidth, OSNR is the received signal-to-noise ratio [optical signal-to-noise ratio (OSNR)], and RBW is the resolution bandwidth of the OSNR measurement. The variance of the ASE–ASE beat noise, which is constant for a given configuration, was given by [18] 2 = σASE−ASE

Fig. 5.

where Ein is the electric field input from a continuous-wave laser assumed to be a constant, d1 and d2 are the two generated drive voltages, and Vπ is the modulator switching voltage. The electric field output of the dual-electrode MZM [Fig. 1(b)] was

Eout

iπd1 Vπ

Ein exp + 2

iπd2 Vπ

.

(2)

B. Fiber Transmission and Receiver Simulation A diagram of the optical link and receiver used in the simulation is shown in Fig. 7. The transmission fiber consisted of 80-km spans of standard single-mode fiber with ideal noisefree amplifiers, which exactly compensated for the optical loss of each span. No optical dispersion compensation was used. The split-step Fourier technique [16] was used to simulate chromatic dispersion and intrachannel nonlinear effects. The simulation parameters are listed in Table II. At the receiver, a semianalytic estimate of the BER was made as follows: first, the noise-free optical signal after fiber transmission was converted to an electrical current, i.e., I(t) = R · |ERX (t)|2

(5)

where Bo is the receiver optical bandwidth. The total noise variance was then

DSP for either d1 or d2 channels.

Ein exp = 2

2 · Be · (2 · Bo − Be ) Iav OSNR2 · RBW2

(3)

where R is the detector responsivity, and ERX is the received electric field. Next, the waveform was filtered with a fourthorder Bessel filter having a −3-dB bandwidth of 7 GHz. [As the optical bandwidth is much larger than the electrical bandwidth, filtering the noise-free signal before detection would have negligible effect in this semianalytical simulation. However, the effect of the receiver optical filter is taken into account in the calculation of amplified spontaneous emission (ASE)–ASE beat noise in (5).] Then, calculations of the electrical noise variance due to ASE in the optical amplifiers were made. Signal–ASE and ASE–ASE beat noise were assumed to be the dominant noise sources. The variance of the signal–ASE

2 2 2 (t) = σsig−ASE (t) + σASE−ASE . σtotal

(6)

Although, in practice, it is known that signal–ASE beat noise has a χ2 distribution, the Gaussian approximation is known to give very accurate BER in intensity-modulated direct-detection systems [19]. In this simulation, the total noise was assumed to be Gaussian distributed. The signal and noise were sampled once per bit, and then, the BER was calculated as N aj (sj − IDL ) 0.5 √ (7) erfc BER = N j=1 2σj where sj are the signal samples, σj are the noise samples, IDL is the decision level, N is the total number of bits that were transmitted, and aj = 1 if the transmitted bit was one and −1 if the transmitted bit was zero. The optimum BER was found by searching over the sampling point and decision level space. The performance criterion that was used in the simulations was the OSNR that was required to achieve a BER of 10−5 . V. R ESULT U SING EPD The system simulation technique that was described in Section IV was used to predict the transmitter performance when using EPD to overcome fiber chromatic dispersion for transmission distances of up to 800 km. The Cartesian MZM was used, and the 11-bit LUTs for each transmission distance were calculated as follows [6]: a 10-Gb/s 211 bit DeBruijn sequence was generated with nonreturn-to-zero/on–off-keying (NRZ/OOK) format with 10%–90% pulse rise and fall times of 30 ps. The predistorted field that is required to obtain this signal at the receiver was calculated using i ETX (t) = F −1 F (ERX (t)) · exp − β2 ω 2 L 2

(8)

where ERX is the received electric field, β2 is the fiber dispersion, ω is the angular frequency, L is the transmission distance, and F (·) and F −1 (·) are the Fourier transform and its inverse, respectively. The drive voltages d1 and d2 that are required

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Fig. 6. Delay circuit on each transmitter input to allow deskew of transmitters. The variable “delay” is specified for each transmitter in the VHDL design code.

TABLE I FPGA RESOURCE USAGE AND PERFORMANCE

Fig. 7. Block diagram of fiber transmission consisting of 80-km spans of SSMF and optical amplification, no optical dispersion compensation, and the receiver model. TABLE II SIMULATION PARAMETERS

to generate the predistorted waveform ETX (t) = |ETX (t)| · exp(i · φ(t)) were obtained by rearranging (1) 2 |ETX (t)| · cos φ(t) Vπ cos−1 π |Ein | −2 |ETX (t)| · sin φ(t) Vπ d2 = cos−1 . π |Ein | d1 =

(9)

The predistorted waveform was sampled twice per bit period. As the 211 bit DeBruijn sequence contains every possible combination of 11-bit sequences, the required samples for each LUT address input can be extracted from the sampled data. Each of the 211 = 2048 LUT entries contains an 8-bit word (two output samples at 4-bit resolution) that is calculated as a decimal as follows: s1 − smin LUTn = int 15 · smax − smin s2 − smin · 16 (10) + int 15 · smax − smin where s1 and s2 are the two samples for the LUT word, and smax and smin are the maximum and minimum values over all the samples, respectively. The MZM drive amplifier gain and bias are smax − smin 15 dx bias = smin .

dx gain =

(11)

To test the resulting performance of the system, the pattern memory was then loaded with a 29 bit DeBruijn sequence. For

each transmission distance, the calculated LUT entries were loaded into the FPGA design, and the OSNR sensitivity was found using the simulation technique described in Section V. Launch powers into each span of −3, 0, and +3 dBm were used to demonstrate the effects of intrachannel fiber nonlinearity. The results, as shown in Fig. 8, demonstrate that 550 km of chromatic dispersion can be compensated with less than 2 dB penalty with −3-dBm launch power into each span. The LUTs in this case are calculated to compensate for chromatic dispersion only, hence, the reduced performance at +3-dBm launch power. However, other work has shown that intrachannel nonlinearities such as self-phase modulation can also be compensated using the LUT approach [14], [16], [20], [21]. No further improvement in the required OSNR was found as the launch power was reduced below −3 dBm.


Fig. 8. Performance of the 10-Gb/s transmitter using EPD with 11-bit LUT addressing with −3, 0, and +3-dBm launch power into each span and (inset) eye diagrams at 0, 480, and 720 km for −3-dBm launch power.

Fig. 9. Optical SSB signal spectrum produced by the transmitter with (inset) noise-free eye diagram.

VI. R ESULT U SING O PTICAL SSB S IGNALS Next, the LUTs were modified to demonstrate, by simulation, the generation of optical SSB signals. Advantages of the optical SSB format are the reduced spectral width, allowing increased spectral efficiency in wavelength-division multiplexing applications, and the possibility of efficient electronic dispersion compensation at the receiver, using linear filtering [3], [22]. In this case, the dual-electrode MZM [Fig. 1(b)] with the characteristics given in (2) was used, with the ideal drive waveforms given by [22] Vπ 4 Vπ d2 (t) = xVπ [−m(t) + m(t)] ˆ + 4

ˆ − d1 (t) = xVπ [m(t) + m(t)]

where m(t) is the ac coupled version of the NRZ binary data, m(t) ˆ is the Hilbert transform of the binary data, and x is the modulation depth. LUTs of 4 bits were required, which were calculated as follows: for each of the 16 possible 4-bit sequences, the Hilbert transform was calculated using a fourtap finite-impulse response, i.e., ˆb = 2 b(3) + 2 b(2) − 2 b(1) − 2 b(0) 3π π π 3π

(12)

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Fig. 10. Performance of the 10-Gb/s transmitter generating SSB signals (solid line) with the performance of a typical conventional double-sideband transmitter shown for comparison (dashed line).

where b is the 4-bit binary sequence. Then, two samples for the d1 LUT entry are V π s1 = xVπ b(2) + ˆb − 4 V π . (13) s2 = xVπ b(1) + ˆb − 4 Similarly, the two samples that are required for the d2 LUT entry are V π s1 = xVπ −b(2) + ˆb + 4 V π . (14) s2 = xVπ −b(1) + ˆb + 4 The LUT 8-bit words, gain, and offset were calculated using (10) and (11). The FPGA pattern memory was loaded with a 29 DeBruijn sequence, and the same LUT entries were used for all transmission distances. A modulation depth parameter of m = 0.2 was used, giving an extinction ratio of 6 dB. Fig. 9 shows the transmitted eye diagram and the optical spectrum, showing that the lower sideband is suppressed by 25 dB at 5 GHz from the carrier. Fig. 10 shows the simulated transmission performance (without receiver compensation) with −3-dBm optical power that is transmitted into each span. The required OSNR values for the equivalent double-sideband NRZ signal are plotted in the same figure for comparison. Back-to-back penalties but improved dispersion tolerance compared to the double-sideband signal are observed, which is in agreement with the results that were presented in [22]. In general, the transmitter design, employing the LUT-based digital filters, can be used to create any advanced optical signal format, provided that the baseband signal bandwidth is less than 10 GHz. VII. P ROOF - OF -P RINCIPLE D EMONSTRATION To demonstrate proof of principle, a similar design to the one that was described in Section II was implemented using the currently available Xilinx Virtex-II Pro (XC2VP70) to generate a single 10.7-GSa/s MZM drive signal with 4-bit nominal amplitude resolution and 1-Sa/b temporal resolution. It has been

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Fig. 11. Experimental setup of 10.7-Gb/s signal generator showing a simplified FPGA structure.

shown that a 1-Sa/b DSP can be successfully employed for EPD NRZ/OOK transmission, albeit with reduced performance [6]. The experimental setup is shown in Fig. 11. Three differences, compared to the design that was described in Section III, were required due to differences in structure and performance between the Virtex-4 and Virtex-II Pro devices. 1) The maximum rated output bit rate of the Virtex-II pro is 3.125 Gb/s. In this design, the FPGA transmitters were operated at 2.675 Gb/s, and 4 : 1 external multiplexers were used to generate the 10.7-Gb/s output. 2) The DSP was implemented for 1-Sa/b processing, requiring 16 transmitters, each with 20-bit-wide interfaces. DSP was carried out in 80-bit blocks. The transmitter reference and DSP clocks were therefore both 133.75 MHz. 3) A single MZM drive signal was generated. Thus, only one of the d1 or d2 signals (shown in Fig. 3) was generated at any one time. The RAM that is available on the XC2VP70 device allowed LUTs with 13-bit addressing in this case. The construction of the full system that was shown in Fig. 3 using the XC2VP70 would require two FPGAs (one for generation of d1 and one for d2 ) with synchronized outputs. Using two Virtex-II Pro FPGAs that are connected with a pattern synchronization signal and with a common reference clock, we have confirmed experimentally that it is possible to synchronize the transmitter outputs of the two devices. The reference clock source was set to 5.35 GHz and separated into the four multiplexer clocks using a passive splitter. The FPGA clock was created by dividing the reference clock by 40. A phase shifter was used to control the relative phase of the multiplexer and FPGA clocks. As the pattern to be transmitted must be stored in 80-bit words, a 217 DeBruijn sequence that was truncated to 131 040 bits (1638 × 80 bit words) was used. Initially, for the transmitter deskew procedure, the entries in the LUTs were calculated to transfer the LUT input to the

Fig. 12. Sawtooth output from the experiment with four samples per output level and 500-ms persistance.

output without modification so that each transmitter had an identical output. With all transmitter delay variables set to zero, the delay of each transmitter output (before the phase shifters) relative to transmitter 1 was measured. From these data, the number of integer bit delays that are required to align each transmitter with the most severely delayed transmitter was calculated. The FPGA design was updated with the delay variables for each transmitter correctly set and recompiled. Next, the phase shifters were adjusted until all channels were accurately aligned. It was found that there was no measurable difference in the phase relationship between transmitters each time the FPGA was powered up. Similarly, it was found that the multiplexer outputs were in-phase each time the system was powered up. Care was taken to ensure that all signal and clock paths were of equal length. Hence, realignment was only necessary after major changes to the FPGA transmitter parameters. Our FPGA design included a test mode that generated a sawtooth waveform output to assess the nonlinearity and noise performance of the transmitter. Due to ac-coupled components


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Fig. 13. DAC performance of the experimental signal generator.

in the signal paths, it is not possible to perform static nonlinearity testing. The test signal (shown in Fig. 12) holds each of the 4-bit output levels for 4 bits. By averaging 2675 periods of the sawtooth waveform, information on integral nonlinearity (INL), differential nonlinearity (DNL), and thermal noise can be extracted, as shown in Fig. 13. INL is the variation of each level from the best fit line through all levels, whereas DNL is the difference between each adjacent level. It can be observed that both INL and DNL are less than ±0.4 of the least significant bit (LSB). For comparison, published data for a 22-GSa/s 6-bit amplitude resolution DAC that is designed for EPD shows a maximum INL of 0.9 LSB and a maximum DNL of 0.5 LSB [23]. The thermal noise was constant for all output levels, having a standard deviation of 0.22 LSB. Fig. 12 also shows examples of switching transients and droop, which will have some additional impact on performance. To predict the transmission performance that could be achieved with a complete system, a digital sampling oscilloscope was used to record the output of the experiment, and the resulting waveforms were used as the input to a Monte Carlo simulation. d1 and d2 EPD LUTs were calculated for various transmission distances ranging from 240 to 640 km using the technique that was described in Section V. Each LUT was loaded into the FPGA design in turn, and the output was sampled using a real-time digital sampling scope at 40 GSa/s with 8-bit nominal resolution. The total sample period was 36.74 µs, covering three complete truncated DeBruijn sequences (393 120 bits). Fig. 14(a) and (b) shows short sections of the d1 and d2 outputs for EPD transmission over 480 km with the expected simulated waveforms for comparison. Good agreement between the experimental and simulated waveforms was found. The two sampled waveform files for each transmission distance were used in a Monte Carlo simulation, as shown in Fig. 15. The two waveforms were amplified and biased appropriately and applied to a Cartesian MZM transfer function, followed by linear fiber transmission with a dispersion of 17 ps · nm/km. White Gaussian noise, representing ASE noise, was applied to the resulting signal. The signal was filtered using an optical bandpass filter with first-order Gaussian characteristics and a full-width at half-maximum of 60 GHz, which was detected and filtered with a fourth-order Bessel filter with a cutoff frequency of 7 GHz. Fig. 14(c) shows a

Fig. 14. Comparison of waveforms from experiment and simulation for 480-km EPD transmission. (a) d1 MZM drive, (b) d2 MZM drive, and (c) received signal after simulated transmission.

short section of the received waveform for EPD transmission over 480 km. BER was determined using the Monte Carlo technique of error counting, and the required OSNR for a BER of 10−3 was determined. For comparison, the same simulation was performed at each transmission distance using the ideal simulated d1 and d2 waveforms (for 1-Sa/b 4-bit resolution) as input. The required OSNR results are shown in Fig. 16. Note that the relatively high required OSNR and eye closure were due to the use of only one DAC sample per bit. For transmissions of up to 480 km, the additional implementation penalty of the FPGA-based transmitter compared to the ideal drive waveforms was found to be less than 1.5 dB. These penalties were partly due to the reduced effective resolution of the transmitter (due to the nonlinearity, noise, and transient characteristics that were described earlier) and partly due to the fact that the d1 and d2 waveforms were generated at different times in this experiment and, hence, contain different clock jitter and wander characteristics. For the latter reason, better results would be expected from a complete system in which two signal generators operate simultaneously, as described in Section III. VIII. C ONCLUSION The design of a reprogrammable FPGA-based 10-Gb/s optical transmitter using real-time 2-Sa/b 4-bit-resolution DSP was described. Using a single Xilinx Virtex-4 FPGA, a DSP design based on LUTs with up to 12-bit addressing was presented. By modifying only the entries in the LUTs, the transmitter can be programmed to transmit EPD signals or advanced modulation formats. A simulation technique was presented for the first time, using industry-standard digital design simulation tools (Mentor Graphics Modelsim) in combination with a simulation of the analog microwave components, optical transmission, and BER estimation to demonstrate the performance of the full transmission system. Using this simulation technique, it was predicted that the chromatic dispersion of up to 550 km of standard fiber could be compensated using EPD and 11-bit LUTs. The

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Fig. 15. Monte Carlo simulation flow using experimental waveforms as input.

[6]

[7]

[8]

[9] [10] Fig. 16. Monte Carlo transmission simulation results showing the required OSNR for a BER of 10−3 with MZM drive waveforms either captured from the proof-of-principle experiment (solid line) or simulated with 4-bit amplitude resolution (dashed line). Eye diagrams are shown (inset) at 480 km.

generation of optical SSB signals was simulated as an example of digital synthesis of advanced optical signal formats. A proofof-principle experiment was described in which a 10.7-Gb/s MZM drive signal was produced with 4-bit amplitude resolution and 1-Sa/b temporal resolution. Using Monte Carlo transmission, i.e., a simulation with sampled EPD outputs from the experiment, an additional implementation penalty of less than 1.5 dB was demonstrated for transmissions of up to 480 km of standard fiber.

[11] [12] [13]

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[16]

R EFERENCES [1] H. F. Haunstein, W. Sauer-Greff, A. Dittrich, K. Sicht, and R. Urbansky, “Design of near optimum electrical equalisers for optical transmission in the presence of PMD,” presented at the Conf. Optical Fiber Commun. (OFC), Anaheim, CA, Mar. 2001, Paper WAA4-1. [2] M. G. Taylor, “Coherent detection method using DSP for demodulation of signal and subsequent equalization of propagation impairments,” IEEE Photon. Technol. Lett., vol. 16, no. 2, pp. 674–676, Feb. 2004. [3] P. M. Watts, M. Mikhailov, M. Glick, P. Bayvel, and R. I. Killey, “Single sideband optical signal generation and chromatic dispersion compensation using digital filters,” Electron. Lett., vol. 40, no. 15, pp. 958–960, Jul. 2004. [4] M. M. El Said, J. Sitch, and M. I. Elmasry, “An electronically preequalized 10 Gb/s duobinary transmission system,” J. Lightw. Technol., vol. 23, no. 1, pp. 388–400, Jan. 2005. [5] J. McNicol, M. O’Sullivan, K. Roberts, A. Comeau, D. McGhan, and L. Strawczynski, “Electrical domain compensation of optical dispersion,”

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presented at the Conf. Optical Fibre Commun. (OFC), Anaheim, CA, Feb. 2005, Paper OThJ3. R. I. Killey, P. M. Watts, V. Mikhailov, M. Glick, and P. Bayvel, “Electronic dispersion compensation by signal predistortion using digital processing and a dual drive Mach–Zehnder modulator,” IEEE Photon. Technol. Lett., vol. 17, no. 3, pp. 714–716, Mar. 2005. A. Färbert, S. Langenbach, N. Stojanovic, C. Dorschk, T. Kupfer, C. Schulien, J. P. Elbers, H. Wernz, H. Griesser, and C. Glingener, “Performance of a 10.7 Gb/s receiver with digital equaliser using maximum likelihood sequence estimation,” presented at the 30th European Conf. Optical Commun. (ECOC), Stockholm, Sweden, Sep. 2004, Paper Th4.1.5. M. O’Sullivan, “Electronic equalization applied to optical systems,” in Proc. e-Photon One Workshop Mitigating Linear Non-Linear Opt. Transmission IMpairments Electronic Means 31th Eur. Conf. Opt. Commun. (ECOC), Glasgow, U.K., 2005. RocketIO Transceiver User Guide UG024 (v2.5), Xilinx Inc., San Jose, CA, Dec. 2004. [Online]. Available: www.xilinx.com Virtex-4 RocketIO MultiGigabit Tranceiver User Guide UG076 (v3.2), Xilinx Inc, San Jose, CA, Sep. 2006. [Online]. Available: www.xilinx.com P. J. Winzer and R. Essiambre, “Advanced modulation formats,” Proc. IEEE, vol. 94, no. 5, pp. 952–985, May 2006. P. J. Winzer and R.-J. Essiambre, “Electronic pre-distortion for advanced modulation formats,” presented at the 31st Eur. Conf. Optical Commun. (ECOC), Glasgow, U.K., Sep. 25–29, 2005, Paper Tu4.2.2. D. McGhan, M. O’Sullivan, M. Sotoodeh, A. Savchenko, C. Bontu, M. Belanger, and K. Roberts, “Electronic dispersion compensation (Tutorial),” in Proc. Conf. Opt. Fibre Commun. (OFC), Anaheim, CA, Mar. 2006. C. Weber, J. K. Fischer, C.-A. Bunge, and K. Petermann, “Electronic precompensation of intrachannel nonlinearities at 40 Gb/s,” IEEE Photon. Technol. Lett., vol. 18, no. 16, pp. 1759–1761, Aug. 2006. P. M. Watts, R. Waegamans, M. Glick, P. Bayvel, and R. I. Killey, “An FPGA-based optical transmitter using real-time DSP for implementation of advanced signal formats and signal predistortion,” presented at the 32nd Eur. Conf. Optical Commun. (ECOC), Cannes, France, Sep. 24–28, 2006, Paper We3.P.97. D. McGhan, C. Laperle, A. Savchenko, C. Li, G. Mak, and M. O’Sullivan, “5120 km RZ-DPSK transmission over G.652 fiber at 10 Gb/s without optical dispersion compensation,” IEEE Photon. Technol. Lett., vol. 18, no. 2, pp. 400–402, Jan. 2006. G. P. Agrawal, Fiber-Optic Communication Systems, 3rd ed. Hoboken, NJ: Wiley, 2002. E. DeSuivre, Erbium Doped Fiber Ampliﬁers, Principles and Applications. Hoboken, NJ: Wiley, 1994. D. Marcuse, “Derivation of analytical expressions for the bit error probability in lightwave systems with optical amplifiers,” J. Lightw. Technol., vol. 8, no. 12, pp. 1816–1823, Dec. 1990. R. I. Killey, P. M. Watts, V. Mikhailov, M. Glick, and P. Bayvel, “Electronic precompensation techniques to combat dispersion and nonlinearities in optical transmission,” presented at the 31st Eur. Conf. Optical Commun. (ECOC), Glasgow, U.K., Sep. 25–29, 2005, Paper Tu4.2.1. K. Roberts, L. Chuandong, L. Strawczynski, M. O’Sullivan, and I. Hardcastle, “Electronic dispersion of optical nonlinearity,” IEEE Photon. Technol. Lett., vol. 18, no. 2, pp. 403–405, Jan. 2006.


[22] M. Sieben, J. Conradi, and D. E. Dodds, “Optical single sideband transmission at 10 Gb/s using only electrical dispersion compensation,” J. Lightw. Technol., vol. 17, no. 10, pp. 1742–1749, Oct. 1999. [23] P. Schvan, D. Pollex, and T. Bellingrath, “A 22 GSa/s 6b DAC with integrated digital ramp generator,” presented at the Int. Solid State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2005, Paper 6.7.

Philip Watts (S’04) received the B.Sc. degree in applied physics from the University of Nottingham, Nottingham, U.K., in 1991 and the M.Sc. degree in technologies for broadband communications from the University College London (UCL), London, U.K., in 2003. He is currently working toward the Ph.D. degree with the Optical Networks Group, Department of Electronic and Electrical Engineering, UCL, with research on the subject of electronic dispersion compensation for high bit rate optical communications, in colaboration with Intel Research. From 1991 to 2000, he was with the GEC-Marconi Research Centre, Chelmsford, U.K., on the development of optical systems products, including diode pumped lasers, coherent optical sensors, and adaptive optics. From 2000 to 2002, he was a Senior Optical Hardware Engineer with Nortel Networks, Harlow, U.K., and Ottawa, ON, Canada, with responsibility for next-generation DWDM optical demultiplexer product development. He has more than 20 published papers and patents in the field of optical technology. His research interests are high-speed electronic signal processing for optical fiber transmission and optical interconnect. Mr. Watts was the recipient of the LEOS postgraduate student fellowship in 2006.

Robert Waegemans received the degree in information technology in Belgium and the M.Sc. degree in technologies for broadband communications from the University College London (UCL), London, U.K., in 2005. He was with GTS Carrier Services, Brussels, Belgium. During 1999–2005, he was with Ciena as a Systems, Trials, and Support Engineer, focusing on long-haul DWDM. He is currently a Research Student with the Optical Networks Group, Department of Electronic and Electrical Engineering, UCL researching the use of predistortion, which is generated by field-programmable gate arrays, for optical signals.

Madeleine Glick (S’84–M’87) received the Ph.D. degree in physics from Columbia University, New York, NY, in 1988. Her dissertation work examined the electooptic effects in GaAs-based quantum wells. After receiving her degree, she joined the Department of Physics, Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland, where she continued her research in electrooptic effects in GaAsand InP-based materials. From 1992 to 1996, she was a Research Associate with CERN, Geneva, Switzerland, as part of the Lightwave Links for Analogue Signal Transfer Project. From 1997 to 2001, she was first with GEC Marconi, Caswell, U.K., as a Project Leader, where she worked on highspeed InGaAs photodetectors, and then with the Marconi Research Laboratory, Cambridge, U.K., where she pursued research on optical systems. In 2002, she joined Intel Research, Pittsburgh, PA, where her research interests center on optical systems, including optical switching for high-performance computer interconnects and electronic signal processing for optical communications.

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Polina Bayvel (S’87–M’89–SM’00) received the B.Sc. (Eng.) and Ph.D. degrees in electronic and electrical engineering from University College London (UCL), London, U.K., in 1986 and 1990, respectively. Her Ph.D. work specialized in nonlinear fiber optics and its applications. Following a Royal Society postdoctoral exchange fellowship in 1990 at the Fiber Optics Laboratory at the General Physics Institute, USSR Academy of Sciences, Moscow, Russia, she was a Principal Systems Engineer with STC Submarine Systems Ltd., Greenwich, U.K., and Nortel Networks, Harlow, U.K., on the design and planning of high-speed optical transmission networks. During 1993–2003, she held a Royal Society University Research Fellowship at UCL, during which she started and built up the Optical Networks Group at UCL. She is currently with the Optical Networks Group, Department of Electronic and Electrical Engineering, UCL. She has authored or coauthored more than 200 refereed journal and conference papers. Her research interests include highspeed WDM transmission and wavelength routing, static and dynamic optical network architectures, nonlinear optics and optical and electronic processing including switching and regeneration, and associated devices. More recently, she has also been working in the area of quantum computation and processing techniques and algorithms. Prof. Bayvel is a Fellow of the Royal Academy of Engineering (FREng), IEE (FIEE) and the Institute of Physics (FInstP). She was an Honorary Editor of IEE Electronics Letters, an Associate Editor of OSA’s Journal of Optical Networking, and was the Royal Society’s representative on the European Science Foundation Standing Committee for Physical and Engineering Sciences. She has served on the technical program committees for ECOC, CLEO, and LEOS and was the Technical Co-Chair for ECOC 2005. She was the recipient of the 2002 Institute of Physics Paterson Medal and Prize for her contributions to theoretical and experimental research on the fundamental aspects of nonlinear fiber optics and their understanding and application in optical communications systems and networks.

Robert Killey (M’00) received the B.Eng. degree in electronic and communications engineering from the University of Bristol, Bristol, U.K., in 1992, the M.Sc. degree in microwaves and optoelectronics from University College London (UCL), London, U.K., in 1994, and the D.Phil. degree from the University of Oxford, Oxford, U.K., in 1998. His doctoral work was on InGaAsP Fabry–Pérot optical modulators and their applications in soliton communications, in collaboration with Alcatel Submarine Systems Ltd., Greenwich, U.K. Following this, he was a Research Fellow with the Optical Networks Group, Department of Electronic and Electrical Engineering, UCL, and was appointed Lecturer at UCL in 2000. He has authored or coauthored more than 100 journal and conference papers. His research interests include nonlinear fiber effects in WDM transmission systems, wavelength-routed optical networks, and applications of electronic signal processing in optical communications. Dr. Killey is a member of the IEEE Lasers and Electro-Optics Society and the Institution of Engineering and Technology. He has served on the technical program committees for ECOC, LEOS, and OECC.