An Improved Power-Added Efficiency 19-dBm Hybrid Envelope ...

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 12, DECEMBER 2006

An Improved Power-Added Efficiency 19-dBm Hybrid Envelope Elimination and Restoration Power Amplifier for 802.11g WLAN Applications Feipeng Wang, Student Member, IEEE, Donald F. Kimball, Member, IEEE, Jeremy D. Popp, Annie Hueiching Yang, Student Member, IEEE, Donald Y. Lie, Senior Member, IEEE, Peter M. Asbeck, Fellow, IEEE, and Lawrence E. Larson, Fellow, IEEE

Abstract—A comparison of envelope elimination and restoration (EER) and envelope tracking (ET) is discussed and a “hybrid” wideband EER power amplifier (PA) for the WLAN 802.11g system is proposed. A 60% efficiency (the output envelope signal power/input dc power) DC-20-MHz wideband envelope amplifier is designed for wideband EER and wideband ET (WBET) applications. A design method is developed to optimize the efficiency of the envelope amplifier for a given peak-to-average ratio and average slew rate of the envelope signal. An experimental “hybrid” Class-E EER system shows an overall efficiency (modulated RF output power/envelope amplifier dc input power) of 36% and power-added efficiency (the modulated RF output power/envelope amplifier dc input power plus RF input power) of 28% for a WLAN 802.11g signal at 19-dBm (80 mW) output power at 2.4 GHz. Digital predistortion, time alignment, and memory effect mitigation are implemented. The measured 3% error vector magnitude exceeds the 802.11g specification for 5% for a 54-Mb/s modulation signal. Index Terms—Class E, dc–dc converter, delta-modulation (DM), digital predistortion, envelope elimination and restoration (EER), envelope tracking (ET), hysteresis control, memory effect, modulator, orthogonal frequency-division multiplexing (OFDM), polar transmitter, power amplifiers (PAs), power tracking, pulsewidth modulation (PWM), time alignment, wireless local area network (WLAN).

I. INTRODUCTION IGH-EFFICIENCY radio-frequency (RF) power amplifiers (PAs) are critical in portable battery-operated wireless communication systems because they can dominate the power consumption in the transmit mode (over 50% for a common wireless local area network (WLAN) transceiver including baseband power) [1], [2]. To maximize the efficiency of the PA, a constant envelope modulation scheme is preferred, since the PA can operate in the high-efficiency compression or saturation region (such as Class C, D, E, or F) [3]–[5]. With modern wireless communication systems evolving to a higher data rate, nonconstant-envelope schemes are preferred. For example, the WLAN 802.11g standard employs 64 QAM

H

Manuscript received May 18, 2006; revised August 16, 2006. This work was supported by the Powerwave Corporation, the Ericsson Corporation, and the Conexant Corporation under the UC MICRO and UC Discovery Grant programs. The authors are with the Center for Wireless Communications, Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92092 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2006.885575

modulation and 52 orthogonal frequency-division multiplexing (OFDM) carriers at a 54-Mb/s data rate. This modulation format has a high envelope peak–average ratio (PAR) of 8–10 dB [6], [7]. The nonconstant envelope modulation requires “linear” PAs amplifying the envelope and phase modulation signal to avoid the nonlinear distortion. Traditionally, linear power amplifiers are implemented by “backing off” the Class A or Class AB PA. Unfortunately, this will decrease the average efficiency, since the PA operates in the low-efficiency region most of the time [8], [9]. Therefore, for a high PAR signal, the average efficiency is much lower than the peak efficiency, which demonstrates the inherent tradeoff between linearity and efficiency for the PA designer. This problem has been investigated for many years. Power supply control schemes offer the greatest potential of high average efficiency operation for high PAR signals. However, due to the bandwidth limitations of the dc/dc converter, the traditional dynamic supply control schemes are typically limited to narrow-bandwidth applications such as average power tracking. In this paper, we propose a “hybrid” wideband envelope elimination and restoration (EER) dynamic supply scheme with a wideband envelope amplifier for WLAN OFDM applications. Section II reviews the traditional EER and envelope tracking (ET) systems. Then, a “hybrid” EER structure is proposed for an 802.11g signal. Section III discusses wideband high-efficiency envelope amplifier design for EER and wide-bandwidth ET (WBET) applications. Analysis and simulations demonstrate an optimized design method for the envelope amplifier. Section IV shows the experimental measurements of the wideband envelope amplifier and the “hybrid” EER system for the WLAN 802.11g signal. Digital predistortion and adaptive time alignment are implemented in the system to maintain adequate linearity for WLAN 802.11g applications. II. WIDEBAND EER AND ET ARCHITECTURE A. Comparison of EER and ET Dynamic power supply schemes are usually separated into two types: EER and ET. Fig. 1 shows the principles of traditional EER and ET systems. EER uses a combination of a high-efficiency switch-mode PA with an envelope remodulation circuit [10]–[14]; ET utilizes a linear PA and a controlled supply voltage, which tracks the input envelope. When the supply voltage tracks the instantaneous envelope modulation signal, it is WBET [9], [15]–[17]; when the supply voltage

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WANG et al.: IMPROVED PAE HYBRID ENVELOPE ELIMINATION AND RESTORATION PA FOR 802.11g WLAN APPLICATIONS

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Fig. 1. (a) EER system block diagram [10]–[14]. (b) ET system block diagram.

tracks the long-term average of the input envelope power, it is called average ET (AET) [18], [19]; when the supply voltage switches to different step levels according to the input envelope power, it is called step ET (SET) [20], [21]. The AET and SET are especially useful for dynamic power control schemes such as the reverse link in code-division multiple-access (CDMA) systems where the variation in average power is much greater than 20 dB [8]. In both EER and WBET systems, the biasing point of the RF transistor dynamically changes depending on the input power; therefore, the RF transistor operates in the high-efficiency region (a switch-mode PA in EER) or the compression region (linear-mode PA in ET) over a wide dynamic range of output power. Theoretically, EER is more efficient than ET, since the RF transistor is always operating in a switching mode. In the traditional EER system, the input RF signal is clipped by a limiter (as shown in Fig. 1); usually, the limiter is challenging to realize for a wide-dynamic-range OFDM signal where the peak-to-minimum ratio is infinite [22]. In modern EER systems, the amplitude and phase signals are generated directly in the baseband domain and up-converted to RF. For the complex modulated signal, the baseband signal can and or and as be expressed with (1) where the envelope signal is

Fig. 2. Simulations of: (a) the spectra of the complex baseband and the phase signals and (b) EVM as a function of baseband system bandwidth for the EER system. The required EVM is 5% for a WLAN 802.11g PA.

bandwidth requirement of the phase signal imposes practical challenges and limits the traditional EER transmitter to narrowbandwidth applications [24], [25]. However, the RF signal bandwidth in ET systems is identical to the baseband signal bandwidth, which is much narrower than the phase signal bandwidth in EER systems. In addition, since ET keeps the amplitude information in the RF signal, it requires a lower envelope amplifier bandwidth and less precise time alignment between the envelope and RF paths [17]. Fig. 3 shows a comparison of the envelope amplifier bandwidth requirement between EER and ET for WLAN 802.11g applications. B. “Hybrid” EER

(2) and the phase signal is (3) is much wider than The required bandwidth of phase signal that of baseband signal [23], as shown in Fig. 2. The

To utilize the high efficiency operation of EER and at the same time reduce the stringent requirements of bandwidth and time alignment, the “hybrid” EER structure was proposed recently [26]–[28]. Fig. 4 shows the principle of the hybrid EER system, where the PA input signal is still a complex-modulated signal, but the PA is designed to operate in the switching mode at higher input powers. Compared with traditional EER systems, the hybrid EER provides the following potential advantages:

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Fig. 3. Simulated envelope amplifier bandwidth requirement for an 802.11g signal in ET and EER systems. The required EVM is 5% for WLAN 802.11g PA.

Fig. 4. Hybrid EER structure: RF input signal is both envelope and phase modulated signal and the RF PA is designed as a switch-mode PA.

TABLE I COMPARISON BETWEEN EER, ET, AND HYBRID EER

envelope amplifier is usually realized by a dc/dc converter, and the switching frequency is required to be several times the signal bandwidth [2], [29]. For narrow-bandwidth applications, most high-efficiency switching-mode dc/dc converters are realized by traditional delta modulation [13], [27], [30], [31] or pulsewidth modulation (PWM) [9], [32], [33] modulators. However, the high switching frequency will introduce a significant switching loss for a wideband signal. For example, a 20-MHz envelope bandwidth is required for WLAN orthogonal frequency-division multiplexing (OFDM) signal for low EVM (as shown in Fig. 3), so the switching frequency of the traditional dc/dc converter will be at least 100 MHz, which introduces a significant switching loss [2]. To overcome the tradeoff between the efficiency and bandwidth of the traditional dc/dc converter, a switching-mode envelope amplifier assisted by linearization is proposed in [34] and [35]. The structure is based on feed-forward topology, which requires a time alignment between the switch and linear parts and a power combiner at the output of the envelope amplifier. In this paper, the proposed wideband high-efficiency envelope amplifier uses hysteretic current feedback control. This topology is a derivative of rectangular wave delta modulation (RWDM) [36]–[38] and has been used in audio amplifier applications, where it was originally proposed to improve the fidelity of the class-D audio amplifier [39]–[44]. We revisit this topology in this paper for wideband EER/ET applications. Section III-A characterizes the spectrum of the envelope signal to illustrate the mechanics of the high-efficiency wideband envelope amplifier. Section III-B investigates the principle of the proposed wideband envelope amplifier, and an expression for the average switching frequency is developed. In Section III-C, the design of an envelope amplifier for 802.11g applications is discussed. In Section III-D, the efficiency is analyzed and simulated for the envelope amplifier. The analysis and simulation results are validated in Section IV by experimental measurements. A. Envelope Signal Power Spectrum Characteristic

1) lower RF bandwidth requirement; 2) lower envelope bandwidth requirement; 3) higher gain and therefore higher average power-added efficiency (PAE); 4) lower sensitivity to the time mismatch between envelope and RF paths. An example of wideband “hybrid” EER for a WLAN 802.11g system will be demonstrated in Section IV. Table I shows a comparison between EER, WBET, and “hybrid” EER. III. WIDEBAND ENVELOPE AMPLIFIER DESIGN The use of dynamic supply control in EER and ET can boost the RF PA drain/collector average efficiency, but the total system efficiency is determined by the product of the envelope amplifier efficiency and the RF transistor drain/collector efficiency. Thus, a high-efficiency envelope amplifier design is critical to the EER/ET system. The high-efficiency

Fig. 5 shows the spectra of the WLAN OFDM envelope signal and the signal energy distribution. The nonlinear transformation from and to the envelope signal will expand the envelope signal bandwidth to infinity. However, most of the energy is concentrated from dc to several kilohertz (e.g., more than 85% for an OFDM waveform), and 99% of the energy is concentrated below the signal RF bandwidth of 20 MHz. This characteristic of the signal energy implies that a “split-band” envelope amplifier can achieve a high efficiency over a wide bandwidth. The split-band envelope amplifier is composed of a wideband (but rather low efficiency) linear stage and a high-efficiency narrowband switch stage, where the overall efficiency is a combination of the two efficiencies, i.e.,

(4) (envelope ampliwhere the overall average efficiency fier output power/envelope amplifier input dc power) depen(switch stage output dent on the switch stage efficiency


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Fig. 6. Envelope amplifier design. (a) Ideal circuit model of the voltage-controlled current-parallel envelope amplifier. (b) Circuit implementation.

Fig. 5. (a) Spectrum of OFDM envelope signal. (b) OFDM envelope signal energy cumulative distribution.

limitation of the switch stage. The instantaneous and average slew rates of the switch and load currents are defined as (6a)

power/switch stage input dc power) and linear stage efficiency (linear stage output power/linear stage input dc power), as well as on the power ratio , which is defined as the ratio of the signal power from the switch stage to the total signal power [34].

(6b)

B. Principle of Wideband High-Efficiency Envelope Amplifier Operation

(6d)

A hysteretic current feedback control is used to realize the smooth power split between switch-stage and linear-stage amplification. The topology of the wideband envelope amplifier is in parallel with a composed of a linear-stage voltage source as shown in Fig. 6(a). The load switch-stage current source voltage is controlled by the linear voltage source ; the load is a combination of the linear stage current and current , i.e., the switch stage current when

(5)

Fig. 6(b) shows the circuit implementation of the envelope amplifier using an operational amplifier (op-amp) as the linear voltage source and buck converter as the current source (switch stage). The hysteresis current feedback control is composed of a , which senses the current direction current sense resistor and a hysteresis comparator to control the single-pole-doublethrow switch, consisting of a pMOS device and a diode. When the P-MOSFET switch is turned on, the voltage at the cathode of and thus the diode is off. When the P-MOSFET the diode is switch is turned off, the inductor tends to turn on the diode. The current flowing through the linear stage is minimized as an error signal in the current feedback. This description of the operation is accurate when the switch noise generated in the switch stage is filtered out by the linear stage and the input envelope signal is within the “slew rate”

(6c)

where and are the voltages at the switch node and output node [refer to Fig. 6(b)], is the load resistor, and are the switch and load currents, and are the instantaneous slew rates of the switch and load currents, and are the average slew rates of the switch and load currents, the envelope signal average duty ratio , is the average of the envelope signal , is the supply voltage. and When the load current average slew rate (6d) is much smaller than the switch current average slew rate (6c), we define the envelope signal as “small-signal” and the circuit operates in the linear region; when (6d) is much larger than (6c), the switch stage enters the “voltage saturation” region and the linear stage provides significant signal current to the load, thus the circuit operates in the large-signal nonlinear region; when (6c) is equal to (6d), the circuit operates in the so-called “matched slew-rate” point. The block diagram of the model of the circuit is shown in Fig. 7. To fully understand the circuit behavior, we separate the analysis into the following three cases. Case 1: Linear Operation for Small-Signal Envelope: In this case, the envelope signal slew rate is within the slew rate limitation of the switch current. The simplicity of the single-tone envelope signal eases the analysis, i.e., (7)

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Fig. 7. Block diagram of hysteresis current feedback control.

where is the dc component of the envelope signal, is the amplitude of the sinusoidal signal (note that for an envelope is always greater than ), and is the envelope signal [refer to Fig. 6(b): sinusoidal frequency. At output node

(8)

Fig. 8. (a) Linearized output voltage. (b) AC switch current waveforms for dc input envelope signal.

The switch current (inductor current) is composed of the switch noise current and signal current , , hence where the signal current is defined as

where . From (14), the switching frequency for a dc signal becomes

(9)

(15)

(10)

Note that the switching frequency is not dependent on . Given (15), the switching frequency for a dc-plus-sinusoidal envelope signal is straightforward to develop. In this case, the duty ratio is a function of time

Substituting (9) into (8) yields

if For small-signal operation

(16) (11) where is the hysteresis value of the comparator in Fig. 6(b). Hence, for small values of , we have

Since small-signal linear operation is still assumed here, (16) can be substituted directly into (15) and the instantaneous switching frequency is

(12)

(17)

For the circuit designer, the switching frequency is an important figure of merit since it determines the switch-stage efficiency. To develop an expression for the switching frequency, we set the ac component of the envelope signal to zero. Then, the input envelope signal is

The average switching frequency for the dc plus sinusoidal signal is

(13) is the switch-stage voltage supply and is the duty where ratio, between zero and one for a buck converter. The inductor voltage and current waveforms are shown in Fig. 8: from 0 to , the switch is on (connected to ) the switch current starts to rise; from to , the switch is connected to ground and the switch current decreases, i.e., from from

to to

(14)

(18) where . Note that the average switching frequency is a function of both the dc and ac components of the envelope signal. Fig. 9 shows the circuit behavior for a sinusoidal envelope signal. Fig. 9(a) shows the simulation of the switching and is a output waveforms. The switching frequency function of time as predicted. Note that the error signal is within the hysteresis value of the comparator as predicted from (11). Fig. 9(b) plots the spectra of the current: all of the signal dc and ac components are provided by the switch stage and the switch noise is filtered out by the linear stage, so the load current harmonics are suppressed compared with the switch current.


Fig. 9. Simulation of: (a) switching waveform and error signal voltage = and (b) spectra of waveforms. The input envelope signal is V 1:94 + 1:2 sin(2500 kHz t). The simulated average switching frequency is 6.4 MHz. The calculated average switching frequency from (18) is 6.7 MHz. V = 5:5 V, h = 7 mV, R = 1 , R = 47 , and L = 12 H.

1

Case 2: Nonlinear Operation—Signal Slew Rate Exceeds the Slew Rate Limitation of the Switch Stage: When the load current average slew rate (6d) is much larger than the switch current average slew rate (6c), the input ac signal is beyond the slew rate limitation of the switch stage and the switch stage can only provide the dc signal power. Hence (19) (20) which shows that the linear stage starts to provide the ac signal current to the load. Since , the error signal is still small, but greater than . In this case, the switching frequency is equal to the ac signal sinusoidal frequency (21) Fig. 10 shows the simulated circuit behavior for a large sinusoidal envelope signal. Note that the simulated switching fre-

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Fig. 10. Simulation of: (a) switching waveform and error signal and (b) spectrums. The input envelope signal is V = 1:94 + 1:2 sin(2 5 MHz t). From the simulation, the switching frequency is 4.95 MHz. The calculated switching frequency from (21) is 5 MHz. All of the circuit parameters are identical to those V is determined by the duty ratio D . in Fig. 9. The asymmetry of V

1

0

quency is equal to the sinusoidal frequency as predicted by (21). DC current is provided by the switch stage. The linear stage not only filters out the switch noise, but also provides the ac component of the signal current. Case 3: Transition From Small-Signal Linear Operation to Large-Signal Nonlinear Operation: Fig. 11 shows the simulated circuit transition behavior between the two regions, by sweeping the ac frequency with fixed dc and ac amplitudes. When the circuit transitions from the small-signal linear operation to large-signal nonlinear operation, the average switching frequency decreases. There is a point where the circuit operates at the minimum average switching frequency, called the “minimum switching” point. At this point, the circuit switching frequency equals the signal frequency, and the circuit efficiency reaches a peak value (refer to Section III-C for a more detailed analysis on the circuit efficiency analysis). Note that, at this point, the average slew rate of the switch current is equal to the slew rate of the load current, defined before as the “matched slew rate” point. Therefore, the “minimum

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Fig. 11. Simulation of circuit behavior by sweeping ac frequency f of the envelope signal: (a) average slew rate, (b) average switching frequency, (c) efficiency (refer to Section III-C for more details on efficiency analysis), (d) ac current from linear stage and switch stage, and (e) normalized rms of the voltage error. Input envelope signal V = 1:94 + 1:2 sin(2f 1 t). All of the circuit parameters are identical to those in Fig. 9.

switching” point is the same as the “matched slew rate” point. Fig. 11(d) shows the partition of the ac signal between the linear stage and the switch stage, which illustrates the capability of the split-band envelope amplifier for smooth transition between the switch stage and the linear stage. Fig. 11(e) shows the error signal increasing during the transition to large-signal nonlinear operation region, which is predicted from (11) and (20). Fig. 12 further demonstrates the circuit behavior by sweeping both the ac frequency and amplitude. Fig. 12(a) shows the simulated average switching frequency as a function of ac frequency and ac amplitude. Fig. 12(b) shows that the matched slew rate condition overlays with the minimum switching frequency condition when the ac amplitude is large. When the ac amplitude is small, the ac current following through the current is not large enough to switch the hyssensor resistor teresis comparator; therefore, the switching frequency becomes close to the average switching frequency of the dc envelope signal. Fig. 12(c) shows that the circuit efficiency under the minimum switching condition is at most 5% higher than that under the matched slew rate condition, which implies that the matched slew rate condition can be used to optimize the circuit parameters.

C. Design of the Envelope Amplifier for an OFDM 802.11g Signal For the envelope amplifier designer, the goal is to maximize the circuit efficiency and at the same time to maintain the high fidelity of the signal. Among the five circuit parameters , only and the hysteresis are determined by the circuit designer. The current sense resistor is chosen to be much smaller than for low loss. The is determined by the required PA equivalent load resistor output power and the drain/collector efficiency , i.e.,

(22) is the rms of the envelope signal. For example, where for a 5.5-V supply voltage and 9-dB PAR signal, the equivalent is in the range of 30 60 for a 60%-efficiency PA when the output power is 16 19 dBm. The determination of is a tradeoff issue between the signal fidelity and the average switching frequency; a smaller will lead to a smaller error from (11) but a larger switching frequency


Fig. 12. Simulation of the circuit behavior by sweeping both ac amplitude and frequency. (a) Average switching signal frequency versus ac frequency for different normalized ac amplitudes (the ac amplitudes are normalized to the signal dc component). (b) Combinations of the signal ac amplitude and ac frequency under the minimum switching condition and the matched slew rate condition. (c) Efficiency versus ac frequency under the minimum switching condition and the matched slew rate condition. The circuit parameters are identical to those in Fig. 9.

from (18). From the simulation, the 7-mV hysteresis value gives the optimized switching frequency and a low EVM (lower than 1%) for the 802.11g signal. Fig. 13 shows the simulated values of the optimum inductor value for a sinusoidal signal and for an 802.11g signal. Fig. 13(a)

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Fig. 13. Simulated behavior as a function the inductor value. (a) Average switching frequency versus L. (b) Average slew rate versus L. (c) Efficiency versus L. The simulation parameters are identical to those in Fig. 9. The 10 t); 802.11g signal sinusoidal signal: V = 1:94 + 1:2 sin(2 500 DC = 1:7 V, rms = 1:9 V.

2

shows that, in the small-signal region, for both signals, the average switching frequencies converge to the calculated average switching frequency (18). Fig. 13(b) shows that, with increasing inductor value, the average slew rate of the switch current decreases but the average slew rate of the load current stays constant, thus the circuit transitions from linear operation to nonlinear operation. In the transition region, the average switching frequency decreases and becomes smaller than the calculated

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Fig. 15. Simulation of envelope amplifier efficiency with the OFDM signal probability density function.

Fig. 14. Linear-stage efficiency analysis. (a) Circuit topology of the high-efficiency push–pull class-B linear stage (the load and the switch stage are respectively simplified as a resistor and a dc current source). (b) Comparison of simulation and theory for the linear-stage efficiency. The efficiency of the linear stage is zero at the dc level of the input signal, where the dc power is supplied by the switch stage.

average switching frequency (18). In the large-signal region, the average switching frequency trends close to a constant as predicted from (21). Therefore, there is a crossover point between the circuit average switching frequency and the calculated switching frequency from (18). Note that, since the 802.11g signal can be considered to be a combination of multiple consecutive sinusoidal signals, its transition behavior between smallsignal and large-signal is more gradual than the single-tone sinusoidal signal. The transition behavior from the small-signal to the large-signal operation region is more gradual for an 802.11g signal than a single-tone signal in terms of the average switching frequency [see Fig. 13(a)] and the efficiency [see Fig. 13(c)]. This is because the 802.11g envelope signal is composed of multiple frequency components from dc to 20 MHz, which tends to average the behavior. At the matched slew rate point, the efficiency reaches a peak for the single-tone envelope signal and flattens out for the 802.11g signal (see Section III-D for more details on the efficiency analysis). The inductor value at the matched slew rate point is (23)

Fig. 16. Comparison of the simulated and measured envelope amplifier by sweeping the signal ac frequency: V = 1:94 + sin(2 1 f 1 t). In the simulated efficiency, the quiescent current and the power loss in the comparator is not included. The circuit parameters for the simulation and measurement are identical to those in Fig. 9 except that L is 18 H in this simulation and measurement.

Given the 802.11g signal dc amplitude and its average slew rate , the calculated inductor value from (23) is 3.6 H, which agrees well with the simulated value of 3 H. From the simulation, a larger inductor will produce a slightly higher efficiency for the 802.11g signal. However, a larger inductor value will also introduce a higher parasitic resistor, which will eventually lead to decreasing efficiency in practice. Also, a larger inductor will require more space on the circuit board. Finally, a larger inductor will have greater inter-winding capacitance that could decreases circuit stability. We found experimentally that a 12- H inductor is the optimum value in this case. From the simulation, the average switching frequency is 5.7 MHz, which agrees well with the calculated average switching frequency of 6.2 MHz from (18). The optimized inductor value is chosen to be approximately four times the calculated value from (23), and the average switching frequency can be estimated accurately by (18).


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TABLE II COMPARISON OF PUBLISHED ENVELOPE AMPLIFIERS AND THE WORK PRESENTED IN THIS PAPER

Note: peak efficiency

= peak envelope output power=dc input power, average efficiency = average envelope output power=dc input power.

D. Envelope Amplifier Efficiency Analysis Linear-Stage Efficiency Analysis: A high-efficiency linear output stage can be realized by a rail-to-rail push–pull Class-B configuration as shown in Fig. 14(a). The loss comes from the pMOS and nMOS devices, i.e., (24) (25a) (25b) where is the voltage supply, is the output voltage at the is the switch-stage current, and is the simplified load, equivalent resistance model of RF PA. For simplicity of analysis, we assume that the switch stage provides only dc current , i.e., . Thus, the linear-stage to the output power is

(26) and the linear-stage efficiency is

(27) Fig. 14(b) shows a comparison of the simulated linear-stage efficiency and that calculated from (24)–(27). In this paper, we chose a National Semiconductor LMH6639 Op-Amp for the linear stage. Note that the real op-amp has nonzero quiescent current and nonzero saturation voltage that reduces the efficiency further. Switch-Stage Efficiency Analysis: The switch stage is realized by a buck converter as shown in Fig. 6(b). The resulting switch-stage loss is composed of three sources, given here. loss), when the switcher (PMOS or 1) Conduction loss ( diode) is on (28a) (28b) where

, and duty ratio

.

2) Commutation loss due to the pMOS nonzero turn-on and turn-off time (28c) where is the average switching frequency, and are the switcher turn-on and turn-off time, and is the commutation parameter (assuming for the worst case [45]). Note that the power loss in the output capacitor is included in the commutation loss. and the 3) Driver loss consumed in the input capacitor of the MOSFET Miller capacitor

(28d) is the MOSFET input charge. where ; the low A low conduction loss requires a low resistor driving loss and low switching loss require low input and output capacitance. In our design, we chose a Fairchild Semiconductor FDV302P digital FET for the P-MOSFET switch. The diode is a Zetex ZLLS400 Schottky diode. The comparator is National Semiconductor LMV7219 with a measured hysteresis value of 3 7 mV. There is a measured delay (10 20 ns) along the control loop from the comparator to the switcher. Its effect on the average switching frequency can be included in (18) by adjusting the hysteresis value (the effective hysteresis value is the weighted combination of the comparator hysteresis value and the delay). Fig. 15 shows the simulated efficiency of the envelope amplifier versus the normalized output voltage. Note that the efficiency curve matches the probability distribution function of the 802.11g envelope signal. The calculated average efficiency of the envelope amplifier is 65% and agrees with the experimental result in Section IV. IV. EXPERIMENTAL MEASUREMENTS A. Envelope Amplifier Experimental Measurements Fig. 16 shows the comparison of the simulation and measurement of the envelope amplifier during the transition from small-signal to large-signal operation. Table II summarizes a comparison of this study and the published envelope amplifiers,

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TABLE III ENVELOPE AMPLIFIER PERFORMANCE IN THE “HYBRID” EER SYSTEM

Fig. 18. Spectrum before and after predistortion at Pout = 19 dBm (80 mW). ACPR is improved by 10 dB after the predistortion and memory-effect mitigation. The ACPR improvement is limited by the system bandwidth of 40 MHz.

Fig. 17. Measurement of optimal EER PA efficiency obtained by sweeping input power at different collector voltages (under CW condition at 2.4 GHz). The collector voltage V is swept from 0 to 4 V.

and Table III summarizes the performance of the envelope amplifier. B. Class-E RFPA A high-efficiency low-cost Si BJT Class-E PA [46] was designed for the “hybrid” EER system. A STMicro START499 silicon BJT transistor was used to implement the Class-E RF PA [26]. A collector efficiency as high as 75% and a PAE of were measured. Fig. 17 shows the CW 57% with constant performance of the Class-E PA at different collector voltages at 2.4 GHz. The optimal EER PA efficiency is formed from the efficiency curves. peak efficiency point of each of the fixed C. Hybrid EER Measurements With WLAN OFDM Signal Since the “hybrid” EER system has a nonlinearity associated with the gain variation, baseband predistortion was implemented to improve the system linearity using a previously published approach [17]. Fig. 18 shows a comparison of the measured PA spectrum with and without predistortion, which demonstrates a roughly 10-dB improvement in adjacent channel power ratio (ACPR) (see [47]–[49] for a discussion of memory

Fig. 19. Constellation of 64-QAM OFDM signal at an output power of 19.56 dBm: (a) before predistortion, EVM 6.6%, and (b) after memory-effect predistortion, EVM 3%. The required EVM is 5% by 802.11g specifications.

effect mitigation). Fig. 19 shows the 64-QAM OFDM signal constellation before and after memory-effect predistortion. An adaptive time alignment was implemented in the hybrid EER system to synchronize the RF and envelope paths [17]. Fig. 20


Fig. 20. “Hybrid” EER system time-alignment feature.

TABLE IV SUMMARY OF “HYBRID” EER, WBET, AND CONSTANT CLASS-AB PA WITH OFDM SIGNAL

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been designed and implemented for WLAN 802.11g application. A highly efficient wideband envelope amplifier is designed for wideband EER and WBET applications. The envelope amplifier is analyzed in the small-signal linear operation and large-signal nonlinear operation. A design method is developed to optimize the efficiency of the envelope amplifier for given PAR and average slew rate of the envelope signal. The efficiency of the wideband envelope amplifier is optimized to approximately 60% for a WLAN OFDM envelope signal. The hybrid EER overall efficiency (including the envelope amplifier and the RF power amplifier, but not including digital circuit power consumption relating to the baseband predistortion and time alignment) is 36%, and the PAE (RF modulated output power/envelope amplifier input dc power plus RF modulated input power) is 28% at 19-dBm (80 mW) output power. The linearity meets the WLAN 802.11g standard EVM requirements by implementing baseband predistortion technology, memory-effect mitigation, and adaptive time alignment. Compared with a Class-AB RFPA, the efficiency and PAE are roughly doubled. The proposed wideband “hybrid” EER power amplifier could be suitable for a wideband polar transmitter in WLAN or WiMAX systems. ACKNOWLEDGMENT

Note: the required EVM is 5% by 802.11 specifications. Overall drain/collector efficiency RF modulated output power/envelope amplifier input dc power. Overall PAE RF modulated output power/envelope amplifier input dc power plus RF input power.

=

=

shows the measured EVM with the time mismatch between the RF path and envelope path. Note the similar time-alignment feature between the hybrid EER and ET [17, Fig. 19]. The “hybrid” EER system was measured for an 802.11g signal. The measured Class-E PA collector efficiency (RF modulated output power/envelope amplifier output power) is 66% with an OFDM output power of 19 dBm (80 mW); the measured envelope amplifier efficiency is 55% with an output power 140 mW. As a result, the total “hybrid” EER PA efficiency (RF modulated output power/envelope amplifier input dc power) is 36% and PAE (RF modulated output power/envelope amplifier input dc power plus RF modulated input power) is 28% with an EVM of 2.8% (the required EVM is 5% by 802.11g specification). Table IV summarizes the “hybrid” EER performance for a 54-Mb/s data rate WLAN OFDM signal. Compared with traditional Class-AB PA, the PAE is improved by a factor of more than two for the “hybrid” EER system. V. CONCLUSION A wideband high-efficiency Class-E “hybrid” EER power amplifier employing a high-efficiency envelope amplifier has

The authors would like to acknowledge P. Draxler at Qualcomm and the University of California at San Diego (UCSD) for providing the memory-effect mitigation algorithm. The authors would like to thank to Dr. J. Jeong at UCSD for providing Matlab code to generate and demodulate the 64-QAM OFDM signal. The authors also wish to thank Dr. D. Choi and H. Ng of Nokia, D. Ojo of Broadcom, Dr. D. Qiao of Axiom Microdevices Inc., C. Hsia, Y. Zhao, M. Li, T. Hung, and M. Pan at UCSD for many valuable discussions and help. REFERENCES [1] L. E. Larson, RF and Microwave Circuit Design for Wireless Communications. Boston, MA: Artech House, 1996, pp. 1–15. [2] H. Krauss, C. Bostian, and F. Raab, Solid State Radio Engineering. New York: Wiley, 1980, pp. 432–467. [3] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 1999, pp. 246–248. [4] P. B. Kennington, High Linearity RF Amplifier Design. Norwood, MA: Artech House, 2000, pp. 425–442, pp. 511-512. [5] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [6] Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer Specifications, IEEE Std. 802.11a/b/g, 1999/1999/2003. [7] Making 802.11g Transmitter Measurement Agilent Application Note, AN 1380-4. [8] J. B. Groe and L. E. Larson, CDMA Mobile Radio Design. Boston, MA: Artech House, 2000. [9] G. Hanington, P. Chen, P. M. Asbeck, and L. E. Larson, “High efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999. [10] L. Kahn, “Single-sideband transmission by envelope elimination and restoration,” Proc. IRE, pp. 803–806, Jul. 1952. [11] ——, “Comparison of linear single-sideband transmitters with envelope elimination and restoration single-sideband transmitters,” Proc. IRE, pp. 1706–1712, Jul. 1956. [12] R. H. Raab, B. E. Sigmon, R. G. Myers, and R. M. Jackson, “L-band transmitter using Kahn EER technique,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2220–2225, Dec. 1998.

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[36] M. Rahman, J. E. Quaicoe, and M. A. Choudhury, “Performance analysis of Delta modulated PWM inverters,” IEEE Trans. Power Electron., vol. PE-2, no. 7, pp. 227–233, Jul. 1987. [37] A. H. Chowdhury, A. Mansoor, M. A. Choudhury, and M. A. Rahman, “On-line improved inverter waveform by variable step Delta modulation,” in IEEE Power Electron. Specialists Conf. Rec., Jun. 1994, vol. 1, pp. 143–148. [38] S. C. Li, V. Lin, K. Nandhasri, and J. Ngarmnil, “New high efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for Portable Consumer Electronics,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1767–1774, Sep. 2005. [39] G. B. Yundt, “Series- or parallel-connected composite amplifiers,” IEEE Trans. Power Electron., vol. PE-1, no. 1, pp. 48–54, Jan. 1986. [40] H. Ertl, J. W. Kolar, and F. C. Zach, “Basic considerations and topologies of switched-mode assisted linear power amplifiers,” IEEE Trans. Ind. Electron., vol. 44, no. 1, pp. 116–123, Feb. 1997. [41] N. S. Jung, N. I. Kim, and G. H. Cho, “A new high-efficiency and super-fidelity analog audio amplifier with the aid of digital switching amplifier: Class K amplifier,” in Proc. 29th Annu. IEEE Power Electron. Spec. Conf., 1998, pp. 457–463. [42] R. A. R. van der Zee and E. van Tuijl, “A power-efficient audio amplifier combining switching and linear techniques,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 985–991, Jul. 1999. [43] A. E. Ginart, R. M. Bass, W. M. Leach, and T. G. Habetler, “Analysis of the Class AD audio amplifier including hysteresis effects,” IEEE Trans. Power Electron., vol. 18, no. 2, pp. 679–685, Mar. 2003. [44] G. R. Walker, “A Class B switch-mode assisted linear amplifier,” IEEE Trans. Power Electron., vol. 18, no. 6, pp. 1278–1285, Nov. 2003. [45] P. T. Krein, Elements of Power Electronics. Oxford, U.K.: Oxford Univ. Press, 1998, pp. 462–473. [46] N. O. Sokal and A. D. Sokal, “Class E—A new class of high efficiency tuned single ended power amplifiers,” IEEE J. Solid-State Circuits, vol. SC-10, no. 3, pp. 168–176, Jun. 1975. [47] P. Draxler, S. Lanfranco, D. Kimball, C. Hsia, J. Jeong, J. van de Sluis, and P. Asbeck, “High efficiency envelope tracking LDMOS power amplifier for W-CDMA,” in IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, Jun. 11–16, 2006. [48] P. Draxler, J. Deng, D. Kimball, I. Langmore, and P. Asbeck, “Memory effect evaluation and predistortion of power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Long Beach, CA, Jun. 12–17, 2005. [49] D. Kimball, P. Draxler, J. Jeong, C. Hsia, S. Lanfranco, W. Nagy, K. Linthicum, L. Larson, and P. Asbeck, “50% PAE WCDMA basestation amplifier implemented with GaN HFETs,” in IEEE Compound Semiconductor Integr. Circuit. Dig., 2005, pp. 89–92.

Feipeng Wang (S’04) received the B.S. degree from Xian Jiaotong University, Xian, China, in 1996, and the M.S. degree from the Chinese Academy of Sciences, Beijing, China, in 1999, both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at the University of California at San Diego (UCSD), La Jolla. From 1997 to 1999, he was with the Laboratory for Microwave Remote Sensing and Information Technology, Chinese Academy of Sciences, as a Research Assistant. From 2000 to 2002, he was a Teaching Assistant with the University of Texas at Arlington. His current doctoral research at UCSD is on the design of the high-efficiency linear envelope tracking and envelope elimination and restoration power amplifiers for WLAN OFDM system. His research interests include RF and analog IC design for wireless communications. Mr. Wang was the recipient of “ADI Outstanding Student Designer” from Analog Device Inc. at ISSCC 2006 and the second prize student paper award presented at 2004 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS). He was also the recipient of the CAL(IT)2 Fellowship (2002–2003) presented by University of California at San Diego and Texas Telecommunications Engineering Consortium Scholarship (TxTEC) (2001–2002) and the Rudolph Hermann’s Fellowship (2000–2001) presented by the University of Texas at Arlington.


Donald F. Kimball (S’82–M’83) was born in Cleveland, OH, in 1959. He received the B.S.E.E. (summa cum laude) and M.S.E.E. degrees from The Ohio State University, Columbus, in 1982 and 1983, respectively. From 1983 to 1986, he was with Data General Corporation as a TEMPEST Engineer. From 1986 to 1994, he was with Data Products New England as an Electromagnetic Compatibility Engineer/Manager. From 1994 to 1999, he was with Qualcomm Inc. as a Regulatory Product Approval Engineer/Manager. From 1999 to 2002, he was with Ericsson Inc. as a Research and Technology Engineer/Manager. Since 2003, he has been with the Center for Wireless Communications, University of California at San Diego, La Jolla, as a Principal Development Engineer. He holds four U.S. patents with two patents pending associated with high-power RF amplifiers (HPA). His research interests include HPA envelope elimination and restoration techniques, switching HPAs, adaptive digital predistortion, memory effect inversion, mobile and portable wireless device battery management, and small electric-powered radio-controlled autonomous aircraft.

Jeremy D. Popp received the B.S. degree (with honors) in electrical engineering from Portland State University, Portland, OR, in 1998, and is currently working toward the Ph.D. degree in electrical engineering at the University of California at San Diego, La Jolla. From 1998 to 2006, he has been an RFIC Designer Engineer with the U.S. Navy Space and Naval Warfare System Center, San Diego, CA. His work focuses on development of highly efficient wireless transceivers in SOI CMOS and SiGe technologies for mobile communication applications.

Annie Hueiching Yang (S’02) received the B.S. degree from the University of California (UCI), Irvine, in 2002, and the M.S. degree from the University of California at San Diego (UCSD), La Jolla, in 2004, both in electrical engineering. Her master’s research focused on the investigation and modeling of Envelope Elimination and Restoration and Envelope Tracking systems for WLAN 802.11a/g OFDM signal. She is currently an RF Hardware and System Engineer with the Space and Naval Warfare Systems Center, San Diego, CA. From 2001 to 2002, she was an Undergraduate Student Researcher with the UCI Integrated Nanosystems Research Facility. From 2003 to 2004, she was a Teaching Assistant with UCSD. Her current work focuses on receiver RFIC system block specifications and hardware testing for various transceiver components.

Donald Y. Lie (S’86–M’87–SM’00) received the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 1990 and 1995, respectively. He has held technical and managerial positions at companies such as Rockwell International, SiliconWave/RFMD, IBM, and Microtune Inc., and he is currently the Director, RFIC Design and Test, Dynamic Research Corporation (DRC), San Diego, CA. He is instrumental in bringing in millions of dollars of research funding and has also designed real-world commercial products with millions of dollars in revenue sold internationally. He has also been a Visiting Lecturer with the Electrical and Computer Engineering Department, University of California at San Diego (UCSD), La Jolla,

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since 2002, where he has taught upper-division and graduate-level classes such as “ECE166 Microwave Circuits and Systems” and “ECE265AB Communication Circuits Design.” He is affiliated with UCSD’s Center of Wireless Communications (CWC) and cosupervises several Ph.D. students on their research projects, some of whom have received Best Student Design/Paper Awards. He has authored/coauthored 50 peer-reviewed technical papers and invited book chapters and holds several U.S. patents. Dr. Lie has been on the Executive and RF Design committee member of the IEEE Bipolar/BICMOS Circuits and Technology Meeting (BCTM) and serves on the IEEE VLSI-DAT and IEEE SiRF conferences. He was the recipient of a Best Paper Graduate Student Award and is a past Rotary International Scholar. He currently serves as the Area Editor-in-Chief in the area of “Communications System on Chip, Analog and Mixed Signal IC and RFIC” for the International Journal on Wireless and Optical Communications.

Peter M. Asbeck (M’75–SM’97–F’00) received the B.S. and Ph.D. degrees from the Massachusetts Institute of Technology (MIT), Cambridge, in 1969 and 1975, respectively. His professional experience includes working with the Sarnoff Research Center, Princeton, NJ, and Philips Laboratory, Briarcliff Manor, NY. In 1978, he joined the Rockwell International Science Center, Thousand Oaks, CA, where he was involved in the development of high-speed devices and circuits using III-V compounds and heterojunctions. He pioneered the effort to develop HBTs based on GaAlAs–GaAs and InAlAs–InGaAs materials. In 1991, he joined the University of California at San Diego, La Jolla, as a Professor with the Department of Electrical and Computer Engineering, where he is currently the Skyworks Chair in Electrical Engineering. His research has led to over 220 publications. Dr. Asbeck is a Distinguished Lecturer of the IEEE Electron Devices Society and the IEEE Microwave Theory and Techniques Society. He is recipient of the 2002 IEEE Sarnoff Award for his pioneering development of GaAs-based HBT technology.

Lawrence E. Larson (S’82–M’86–SM’90–F’00) received the B.S. and M.Eng. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1979 and 1980, respectively, and the Ph.D. degree in electrical engineering and the M.B.A. degree from the University of California at Los Angeles (UCLA) in 1986 and 1996, respectively. From 1980 to 1996, he was with Hughes Research Laboratories, Malibu, CA, where he directed the development of high-frequency microelectronics in GaAs, InP, and Si/SiGe and MEMS technologies. In 1996, he joined the faculty of the University of California at San Diego (UCSD), La Jolla, where he is the Inaugural Holder of the Communications Industry Chair. He is currently Director of the UCSD Center for Wireless Communications. During the 2000–2001 academic years, he was on leave with IBM Research, San Diego, CA, where he directed the development of RF integrated circuits (RFICs) for third-generation applications. During the 2004–2005 academic year, he was a Visiting Professor with the Delft University of Technology, Delft, The Netherlands. He has authored or coauthored over 225 papers, and he holds 31 U.S. patents. Dr. Larson was the recipient of the 1995 Hughes Electronics Sector Patent Award for his work on RF MEMS technology. He was corecipient of the 1996 Lawrence A. Hyland Patent Award of Hughes Electronics for his work on lownoise millimeter-wave high electron-mobility transistors, the 1999 IBM Microelectronics Excellence Award for his work in Si/SiGe HBT technology, and the 2003 IEEE Custom Integrated Circuits Conference “Best Invited Paper” Award.

An Improved Power-Added Efficiency 19-dBm Hybrid Envelope ...

An Improved Power-Added Efficiency 19-dBm Hybrid Envelope ...

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