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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
An Improved PSFB PWM DC–DC Converter for High-Power and Frequency Applications A. Faruk Bakan, Nihan Altintas¸, and ˙Ismail Aksoy
Abstract—In the phase shifted full bridge (PSFB) pulse width modulation (PWM) converter, external snubber capacitors are connected in parallel to insulated gate bipolar transistors (IGBTs) in order to decrease turn-off losses. The zero voltage transition (ZVT) condition is not provided at light loads, thus the parallel capacitors discharge through IGBTs at turn on which causes switching losses and failure risk of the IGBTs. Capacitor discharge through IGBT restricts the use of high-value snubber capacitors, and turnoff loss of the IGBT increases at high currents. This problematic condition occurs especially at the lagging leg. In this study, a new technique enabling the use of high-value snubber capacitors with the lagging leg of the PSFB PWM converter is proposed. As advantages of the proposed technique, high-capacitive discharge current through IGBT is prevented at light loads, the turn-off switching losses of the IGBTs are decreased, and the performance of the converter is improved at high currents. The proposed PSFB PWM converter includes an auxiliary circuit, and it has a simple structure, low cost, and ease of control as well. The operation principle and detailed design procedure of the converter are presented. The theoretical analysis is verified exactly by a prototype of 75 kHz and 10 kW converter. Index Terms—DC–DC converters, phase shifted full bridge (PSFB) PWM converter, soft switching, zero voltage switching (ZVS).
I. INTRODUCTION EW techniques are proposed in order to decrease switching losses and to increase power density in dc–dc converters at high power and frequencies [1]–[4]. The applications of soft-switching methods are expanding. The most remarkable method in high-power isolated applications is Phase Shifted (PS) Zero Voltage Switching (ZVS) method, which provides all of the switches to operate with ZVS without any additional auxiliary switches. The parasitic capacitance energy is discharged by the leakage inductance, and the MOSFET turns on with zero voltage transition (ZVT). Insulated gate bipolar transistor (IGBT) is preferred over MOSFET at high voltage and high-power levels in industrial applications. Low RDSON MOSFETs are quite expensive compared to the IGBTs with equivalent current and voltage ratings. The choice of IGBT over MOSFET is mandatory due
N
Manuscript received October 30, 2011; revised January 6, 2012 and March 12, 2012; accepted April 11, 2012. Date of current version September 11, 2012. This work was supported by the Scientific and Technical Research Council of Turkey (TUBITAK) under Grant 107E149. Recommended for publication by Associate Editor R. Redl. The authors are with the Yildiz Technical University, Electrical Engineering Department, Esenler/Istanbul 34220, Turkey (e-mail:
[email protected];
[email protected];
[email protected]). Digital Object Identifier 10.1109/TPEL.2012.2196287
to nonavailability of high voltage and high-current MOSFET devices in some applications. An external snubber capacitor is connected in parallel to each IGBT in order to decrease turn-off losses, in case the IGBT is used in the phase shifted full bridge (PSFB) pulse width modulation (PWM) converter [5]–[26]. When the ZVT condition is not provided at no load and at light loads, the parallel capacitors discharge through IGBT at turn on and this causes increase in switching losses and failure risk of the IGBTs. This condition causes problems at especially the lagging leg [5]–[26]. Capacitor discharge through IGBT restricts the use of high-value capacitor in parallel to IGBT. Therefore, the selection of the parallel capacitor value is very important. The parallel snubber capacitor value should be selected according to the speed and the maximum current of the IGBT [5]. The performance of the converter decreases rapidly at high-current levels because of the turn-off switching losses. At the leading leg, the required energy for discharging the parallel capacitor is supplied from the load current, so the use of high-value capacitor in the leading leg has no drawback. In PSFB PWM dc–dc converters, some problems arises such as variation of duty cycle with load current, hard switching because of insufficient energy in leakage inductance at light loads, and high-voltage peaks and oscillations at the output diodes, and increment in the conduction losses because of the primary current flowing in the freewheeling interval. It is possible to encounter many studies in the literature about these converters and solution for the problems [5]–[26]. In [6], the required large resonant inductor is replaced with linear variable inductor (LVI) which is controlled by output current. The required energy for ZVS operation at low-current levels is obtained by means of the high value of the LVI. The value of LVI decreases approximately linearly with increasing current. The soft-switching operation range is extended and dependency of ZVS operation on the load current is decreased. In [7], an auxiliary circuit which includes two MOSFETs and a serial inductance is proposed. The inductance current is increased before the IGBT devices on the lagging leg are turned off. The ZVS conditions of the FB converter are improved, but the losses in the auxiliary circuit reduce the efficiency. The auxiliary circuit does not operate with soft switching. Main IGBTs are subjected to the current stress before turn off and this increases the switching losses in the turn-off process. The proposed method is not preferred due to low efficiency, high cost, and control difficulty. In [8], the ZVS operation is achieved over the entire conversion range in the PSFB PWM converter for an ohmic load. The proposed converter is suitable for the applications, where load current proportionally increases with output voltage. When
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BAKAN et al.: IMPROVED PSFB PWM DC–DC CONVERTER FOR HIGH-POWER AND FREQUENCY APPLICATIONS
Fig. 1.
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Proposed PSFB PWM converter.
duty ratio is low and output current is high, soft switching is not provided. In this study, a novel auxiliary circuit for the PSFB PWM converter using IGBTs is proposed. The proposed circuit enables the use of high-value capacitors with the lagging leg of the PSFB PWM converter without any problems. At no load, detrimental effects of the surge current to the IGBT due to the snubber capacitors are prevented, and turn-off switching losses of the IGBTs are decreased. This novel converter requires resonant inductance much less than conventional PSFB PWM converter. The proposed method decreases the turn-off switching losses at high currents and improves the performance of the converter. Besides, parasitic oscillations and conduction losses of output diodes are decreased. The theoretical analysis of the proposed converter is given and verified exactly by a prototype of 75 kHz and 10 kW converter. II. OPERATION PRINCIPLES AND ANALYSIS A. Definition and Assumptions The proposed converter is shown in Fig. 1. It consists of a conventional PSFB PWM converter and an auxiliary circuit connected to the lagging leg. The auxiliary circuit contains two IGBTs with reverse recovery diodes and two capacitors C1A , C2A . At low-output currents, converter operates as the conventional PSFB PWM converter. Low-valued snubber capacitors are connected at the lagging leg. These capacitors provide ZVS operation at light loads and improve the turn-off behavior of the IGBT until a current level. Discharge of these capacitors does not bring about a problem at no-load condition and low currents. In the proposed converter, auxiliary circuit is operated only at high-output currents. By means of the auxiliary circuit, highvalue capacitors are connected to the lagging leg and the turnoff performance of the lagging leg switches is improved. The IGBTs used in the auxiliary circuit operate under soft-switching conditions. The conduction loss of the auxiliary switches is very low because they conduct current for a very short time. The operation of the auxiliary circuit starts when primary current IP is larger than boundary current level Ia . This level depends on the characteristics of the IGBTs used in the circuit and nominal current of the converter. The following assumptions are made to simplify the steadystate analysis of the circuit during one switching cycle:
Fig. 2. Key waveforms concerning the operation stages in the proposed PSFB PWM converter.
1) input voltage Vd is constant; 2) equivalent series inductances of the parallel snubber capacitors are neglected; 3) the blocking capacitor CS is large enough to be neglected at high-frequency operation; 4) the effect of the saturable inductors used to prevent parasitic oscillations at the secondary are neglected. B. Operation Stages The basic operation of the proposed soft-switching converter has six operating stages within each half cycle. The operation waveforms are shown in Fig. 2. The equivalent circuits for each operating stage are shown in Fig. 3(a)–(f).
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Stage 1 ([t0 < t < t1 : Fig. 3(a)]): At the beginning of this stage, Q1 and Q4 are conducting, input voltage Vd is applied to the transformer’s primary and power is transferred to the output. Output current flows through the diode Do1 . The initial voltage of VC is equal to Vd . At t = t0 , drive signal VGE4 is removed and Q4 starts to turn off. At the beginning of the turn-off process there exists a delay defined as tdoff . In this interval IQ1 = IQ4 = IP , Q4 is still in the on-state and current flows through the transistor. Stage 2 ([t1 < t < t2 : Fig. 3(b)]): In the turn-off process of Q4 two intervals occur which are defined as current fall time tf , and tail current time ttail . The current of Q4 begins to decrease after t1 and it falls to Itail value at the end of tf . In this interval, there is little increase on the voltage of Q4 because of the parallel capacitors. The turn-off loss of the IGBT is very low in comparison to the hard switching case. In this stage, the parallel capacitor CP is the sum of C3 and C4 . The leakage capacitor of the transformer is neglected in respect of parallel capacitor. If ttail is neglected, the parallel capacitor is assumed to charge linearly. The voltage of Q4 is given by vQ4
Ip = tf . Cp
(1)
When the voltage of Q4 reaches to Vd , D3 starts to conduct. The turn-off loss of Q4 is approximated as Eoff
Ip2 t2f = . 24Cp
(2)
Stage 3 ([t2 < t < t4 : Fig. 3(c)]): This interval starts at t = t2 , when D3 diode turns on. Q1 and D3 are conducting in this freewheeling interval. After the diode D3 turns on, the drive signal of Q3 can be applied. The signal should be applied before the primary current IP becomes zero. At t = t3 , drive signal VGE1 is removed and this interval begins. At the beginning of the turn-off process there exists a delay defined as tdoff . The transistor is still in the on-state and current flows through the transistor. Stage 4 ([t4 < t < t5 : Fig. 3(d)]): At t = t4 , lagging leg transition begins. The initial value of primary current is IP 0 . In this stage two different operation modes occur depending on the primary current level. If the primary current is smaller than Ia , auxiliary circuit is not activated (Mode-1). This mode of the converter would have conventional operation. Proposed converter waveforms are the same as the conventional one’s except VGE1A , VC , and IAUX . In this case, the parallel capacitor, CP is the sum of C1 and C2 . The inductance energy is enough to charge the low-valued snubber capacitors, and soft switching is obtained. If primary current is larger than Ia , auxiliary circuit is operated (Mode-2) as shown in Fig. 3(d). In this case, the parallel capacitor, CP is the sum of C1 , C2 , C1A , and C2A . Due to additional high-valued capacitors, soft switching is obtained at high-current levels. The waveforms given in Fig. 2 are drawn for Mode-2. This interval is completed with discharge of the capacitor (C2 //C2A ) through the resonance between LS and CP , and primary current falls to IP 1 level.
Stage 5 ([t5 < t < t7 : Fig. 3(e)]): When D2 diode turns on at t = t5 , negative voltage is applied to LS , and current falls to zero linearly. After the diode D2 turns on, the drive signal of Q2 can be applied. The auxiliary switch drive signal is removed at t = t6 . This interval is completed when the primary current falls to zero. Stage 6 ([t7 < t < t8 : Fig. 3(f)]): In this interval, primary current decreases from 0 to -Io /a. At t = t8 , the current of Do1 falls to zero and output current is commutated to Do2 . After t8 , normal PWM operation takes place and power is transferred to the output. The operation in the second half cycle is symmetrical to the first one, and a new TS period starts after the second half cycle. III. MAIN FEATURES AND DESIGN PROCEDURE In this section, the design procedure of the proposed converter is given. The component values for implementing the converter are determined according to the design procedure. A. Selection of the Boundary Current Ia The boundary current level Ia that auxiliary circuit starts to operate is CP . (3) Ia = Vd LS The ZVS operation range of the lagging leg switches is increased with decreasing Ia . Low Ia value is obtained by selecting low CP value and high LS value. In the case of low CP value, the turn-off losses increases. High value of LS is not appropriate because it increases conduction and duty cycle losses. Besides, the selection of Ia also depends on the characteristics of the IGBTs, and nominal current of the converter. B. Control Signals and Dead-Time Requirements The required dead time between Q3 and Q4 switches of the leading leg, tdleading , should provide tdleading > tdoff + tf + ttail
(4)
where, tdoff is turn-off delay time, tf is fall time of the current to the tail current level, and ttail is the tail current time. The required dead time between Q1 and Q2 switches of the lagging leg, tdlagging , should provide following condition: tdlagging > tdoff + tf + ttail .
(5)
The required dead time between lagging leg switches varies depending on the primary current. In order to turn off lagging leg switches with ZVS, the stored inductance energy should be sufficient to charge/discharge parallel capacitors 1 1 LS IP2 ≥ CP Vd2 . (6) 2 2 From this equation, the minimum current level IP m in required to provide ZVS is given by CP . (7) IP m in = Vd LS
BAKAN et al.: IMPROVED PSFB PWM DC–DC CONVERTER FOR HIGH-POWER AND FREQUENCY APPLICATIONS
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Fig. 3. Equivalent circuits of the operation stages in the proposed converter. (a) Stage 1 (t0 < t < t1 ). (b) Stage 2 (t1 < t < t2 ). (c) Stage 3 (t2 < t < t3 ). (d) Stage 4 (t3 < t < t5 ). (e) Stage 5 (t5 < t < t7 ). (f) Stage 6 (t7 < t < t8 ).
For the complete charge/discharge of the parallel capacitor, primary current should be larger than IP m in . When IP 0 = IP m in , resonance duration is maximum and capacitor charges to Vd in quarter resonance period. Primary current falls to 0 and VC p reaches to Vd at the end of tZVS m ax =
π LS CP . 2
(8)
If the parallel capacitor is not discharged at the end of tZVSm ax , reverse resonance occurs and soft switching is lost. The primary current fall time from IP 0 to 0 is defined as tP 0 . Depending on IP 0 value two different cases occur. Case 1 ([IP 0 > IP m in ]): tP 0 consists of two intervals, tZVS and tlinear
The parallel capacitor voltage VC p increases from 0 to Vd in tZVS duration. tZVS duration can be derived as CP Vd tZVS = LS CP arcsin . (10) IP 0 LS At the end of tZVS duration, the primary current falls to IP 1 . The value of IP 1 can be calculated as LS I2P0 − CP Vd2 IPl = . (11) LS During the tlinear duration, negative voltage is applied to LS , and current falls to zero linearly. This duration is given as tlinear = LS
IPl . Vd
(12)
The dead time between Q1 and Q2 switches should provide tP 0 = tZVS + tlinear .
(9)
tZVS < tdlagging < tP 0 .
(13)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Fig. 4. Parallel capacitor voltage and primary current waveforms, control signals, lagging leg transition intervals, and definitions in Mode-1 (a, b) and Mode-2 (c, d). (a) Mod-1, IP 0 = IP 1 . (b) Mod-1, IP 1 < IP 0 < Ia . (c) Mod-2, IP 0 = IP 2 = Ia . (d) Mod-2 Ip 0 > Ia .
If tdlagging < tZVS , then lagging leg capacitors is not fully charged/discharged. Thus, ZVT is not provided. If tdlagging > tP 0 , then current changes direction, reverse resonance starts and Q2 turns on with hard switching. The energy of the snubber capacitor is dissipated in the transistor. Case 2 ([IP 0 = IP m in ]): The required dead time between Q1 and Q2 switches is given as tdlagging = tZVS m ax = tP 0 .
(14)
As described in stage 2, two different operation modes occur depending on primary current level in the turn-off process of the lagging leg switches. In Mode-1, CP = C1 //C2 , and in Mode-2, CP = C1 //C2 //C1A //C2A . The related CP value should be taken into account in (7), (8), (10), and (11) equations. Parallel capacitor voltage and primary current waveforms, control signals, lagging leg transition intervals, and definitions are shown in Fig. 4. In these waveforms subscripts 1 and 2 are used for Mode-1 and Mode-2, respectively. Lagging leg transition for the minimum primary current IP m in1 that provides soft switching is shown in Fig. 4(a). At the end of the tZVSm ax1 , the primary current falls to zero, the capacitor voltage reaches to Vd . If the primary current is below this
value, parallel capacitor is not fully charged/discharged. ZVT turn on is not provided, and the capacitor discharges through IGBT. For current values lower than IP m in1 or at no load, there is no risk for destruction of IGBT by discharge, because the capacitor value is low. The waveforms for IP m in1 < IP 0 < Ia in Mode-1 are shown in Fig. 4(b). With the increasing primary current, tZVS decreases and tlinear increases. In Mode-1, the required dead time between Q1 and Q2 should provide (5) and (13). In Mode-2 the auxiliary circuit is operated. Lagging leg transition at the minimum primary current (IP 0 = IP m in2 = Ia ) that provides soft switching is shown in Fig. 4(c). The waveforms for IP 0 > Ia are shown in Fig. 4(d). The required dead time between the lagging leg switches and auxiliary circuit control signals are shown in Fig. 4(c) and 4(d). Dead time tdlagging is inserted between Q1 and Q2 drive signals. Q1 and Q1A drive signals overlap during ta 1 duration. In this overlap duration, auxiliary transistor Q1A turns on under zero voltage and it is ready for soft switching of Q1 . When the signal of Q1 is removed the current is commutated to Q1A directly. Q1A signal should be removed and Q2 signal should be applied in tlinear interval.
BAKAN et al.: IMPROVED PSFB PWM DC–DC CONVERTER FOR HIGH-POWER AND FREQUENCY APPLICATIONS
Dead time tdlagging is selected as tZVSm ax1 and tZVSm ax2 in Mode-1 and Mode-2, respectively. This selection also ensures soft-switching conditions at higher current levels. ta 2 is inserted between Q1A and Q2 drive signals to prevent capacitive discharges. In the transition from Mode-1 to Mode-2 in order to prevent chatter, hysteresis band should be included in the control circuit. Depending on the initial voltage of auxiliary capacitors the different charge transfer cases may occur. At start up, the initial voltage of C1A is Vd /2. In the transition from Mode-1 to Mode2, C1A discharges from Vd /2 to 0, and C2A charges from Vd /2 to Vd . In this case, the voltage of Q1 initially increases to Vd /2 through parallel combination of C1 and C2 . Then it charges to Vd through (C1 //C2 //C1A //C2A ). In normal operation of the converter, the initial voltage of C1A in Mode-1 can be zero or Vd . When the initial voltage of C1A is zero, the auxiliary capacitors are connected in parallel to IGBT, and this can be considered as ideal case. When the initial voltage of C1A is Vd , the first VGE1A pulse does not provide soft turn off for Q1 . In the next half period, the auxiliary circuit starts to operate with VGE2A , and normal operation would continue until Ip > Ia . C. Duty Cycle Loss One of the major problems of the conventional PSFB PWM converter is the duty cycle loss. The duty cycle loss interval is shown in Fig. 2 (t84 = t8 −t4 ). Duty cycle loss ΔD and equivalent duty cycle De are given as t8 − t4 = tZVS
LS Io +2 = TS ΔD aVd
De = D − ΔD.
(15) (16)
In these equations, Io is the output current, a is the transformation ratio, and TS is the switching period. At high currents, tZVS is small so that tZVS duration can be neglected, ΔD and Vo can be given as 2LS Io ΔD ∼ = aVd TS Vo =
D.Vd 2LS Io Vd (D − ΔD) = − 2 . a a a TS
(17) (18)
As it can be seen from (17), high-value resonant inductance increases the duty cycle loss, decreases output voltage and circuit efficiency. Additionally, oscillations occur at the output voltage. In order to decrease the duty cycle loss, LS value should be chosen as small as possible. Especially, at high-frequency applications and at high-current levels, minimizing the inductance value is very important. D. Converter Design The dc–dc converter is designed according to the following specifications: output voltage Vo = 48 V, input voltage Vd = 360 V, primer current IP = 0−40 A, switching frequency fS = 75 kHz, transformation ratio a = (NP /NS ) = 5/1, and ΔDm ax = 20%. The selection procedure of circuit components is given from Step 1 to Step 4.
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1) Step 1 (Selection of C3 and C4 Capacitors): It is accepted that ZVS turn-off condition is provided, if the parallel capacitor charging time is longer than the IGBT turn-off time at maximum load. For the selection of the parallel capacitor, the (19) given in [24] and [27] is used. In this equation, capacitor value is selected according to the assumption that the capacitor voltage is charged from 0 to half of input voltage during the duration of fall time of the IGBT CP =
IP tf . Vd /2
(19)
The CP value is calculated as approximately 20 nF according to tf . The equivalent parallel capacitor is CP = C3 //C4 , thus C3 and C4 are selected as 10 nF. 2) Step 2 (Selection of C1 and C2 Capacitors): Capacitor selection in the leading leg is different from lagging leg, because C1 and C2 discharge with resonance. The selection of the parallel capacitor value is very important to prevent the damage of IGBTs. When the energy in the resonant inductance is not enough to discharge parallel capacitor, the parallel capacitor is directly discharged through the Q1 /Q2 in the turn-on process, and collector current will rise excessively. The parallel snubber capacitor value should be selected according to rise time tr of IGBT and the maximum current ICM in its datasheet. The lagging leg parallel capacitor is selected according to CP ≤
ICM tr . Vd
(20)
By substitution of Vd , tr , and ICM values in the (20), the parallel capacitor value for the lagging leg is obtained as 5 nF. 3) Step 3 (Selection of C1A and C2A Capacitors): The turnoff behavior of the selected IGBT is explained in detail in [5], and according to various capacitor values the turn-off losses of the IGBT are given in Fig. 5. It is observed that the turnoff switching losses of an IGBT, although it is not proportional, is decreased with increasing capacitor value and it is also dependent on tail current of the IGBT. It is aimed to decrease the turn-off losses 90% as compared to the conventional PSFB PWM converter. From Fig. 5, the parallel capacitor CP = C1 //C2 //C1A //C2A that should be connected to the lagging leg is determined as 25 nF. Thus, the C1A , C2A capacitor values of the auxiliary leg are found as 10 nF. According to (3), (8), and (9), increasing the CP value increases Ia and the dead time. Thus, very high CP values would not be appropriate. 4) Step 4 (Selection of LS ): The characteristics of the proposed PSFB PWM converter in Mode-2 are obtained by simulation using MATLAB software. In simulations, 0 < IP < 40 A, and Vd = 300 V are selected. Minimum value of LS is selected as 1 μH to avoid very small dead time, and maximum value of LS is selected as 8 μH because of duty cycle loss limitations. If the inductance value is selected higher, boundary current Ia decreases. At high-current levels, current reversing time and duty cycle loss increases. In this figure, tZVSm ax curves determine the boundary current Ia of the auxiliary circuit. According to (5), considering the speed and time delays of the IGBT and drive circuits, the safe dead-time limit between the drive signals of
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TABLE I CALCULATED VALUES OF Ia , tZ V S m a x , tP 0 AND ΔD FOR 5 μH < LS < 8 μH Calculated Values
L S =5µH
L S =6µH
L S =7µH
L S =8µH
Equation
Ia
21.21A
19.36A
17.92A
16.77A
(3)
t ZVSmax
555ns
608ns
657ns
700ns
(8)
t P0 (I P =40A)
750ns
861ns
1064ns
1180ns
(9)
ΔD(I P =40A)
20%
24%
28%
32%
(17)
TABLE II COMPONENTS USED IN THE EXPERIMENTAL PROTOTYPE
Fig. 5.
Fig. 6.
Eo ff according to CP .
Characteristics of the proposed converter for CP = 25 nF.
the switches on the lagging leg tdlagging is selected as 500 ns. Dead-time duration should also ensure (13). As seen from Fig. 6, for LS values smaller than 5 μH, minimum dead-time requirement (500 ns) is not satisfied. As a result, LS inductance can be chosen between 5 μH and 8 μH. The calculated Ia , tZVSm ax , tP 0 , and ΔD variables for the values of LS between 5 μH and 8 μH are given in the Table I. From Table I, it is seen that, the lower value of LS , the higher value of Ia , and the smaller value of dead time. It is aimed 20% duty cycle loss at full load, so the value of LS inductance is selected as 5 μH. Auxiliary circuit starts at medium current levels, so the required energy for discharging high-valued snubber capacitors is always available. The value of LS is selected as low as possible in the proposed converter. Due to low-duty cycle loss, transformer conversion ratio can be selected higher, thus resulting in lower conduction losses. The parasitic oscillations
S 1 , S 2 , S 3 , S 4 , S 1A , S 2A
IGBTs 600 V, 60A (with diode)
C 1A , C 2A
Auxiliary circuit snubber capacitors
IXGH60N60C2D1 10 nF-630 V
C1, C2
Lagging lag snubber capacitors
2.2 nF-630 V
C3, C4
Leading lag snubber capacitors
10 nF-630 V
LS
Resonant inductance
CS
DC blocking capacitor
5 μH (50A) 4 x 470 nF-630 V
Trf
High frequency power transformer
2xE65-N87 a=5:1
D o1 , D o2
Output diodes 200 V, 160 A
DSEI 2x121-02A
Lo
Output inductance
30 μH (160A)
L S1 , L S2
Saturable inductance
10 μH (I sat =10A)
that occur between LS inductance and parasitic capacitors of output diodes decrease and efficiency increases. In the proposed converter, the selected values of CP and LS provide ZVT operation from 8.9 to 40 A primary current for the IGBTs in the lagging leg. The use of the same component values in the conventional PSFB PWM converter results in ZVT operation from 21.21 A to 40 A primary current. In order to start ZVT operation at the same primary current in conventional PSFB PWM converter, 25 μH inductance value is required which results an increase in duty cycle loss as much as five times. The selected parallel capacitor value (25 nF) in the proposed converter is not proper for the conventional converter. In the conventional converter, parallel capacitor value should be lower than 5 nF due to high current at turn on. Thus, in the proposed converter, turn-off loss of the lagging leg switches is four times lower than that of the conventional converter, at full load. If the operation frequency is higher this advantage becomes more evident. IV. EXPERIMENTAL RESULTS A prototype of a 10 kW and 75 kHz IGBT-based PSFB PWM dc–dc converter with auxiliary circuit is given in Fig. 7, and the photograph of the experimental circuit is given in Fig. 8. The nominal values of the components used in the converter are listed in Table II. It has been assumed that the converter input voltage is provided by the PFC front-end stage. The input voltage is selected as Vd = 360 V. In order to prevent the saturation of transformer at transient state, a dc-blocking capacitor Cs is serially connected to
BAKAN et al.: IMPROVED PSFB PWM DC–DC CONVERTER FOR HIGH-POWER AND FREQUENCY APPLICATIONS
Fig. 7. Experimental circuit schematic of 10 kW and 75 kHz proposed PSFB PWM dc–dc converter.
Fig. 8.
Photograph of the experimental circuit.
transformer. To decrease the leakage inductance of the parallel capacitors, the snubber capacitors are connected in parallel, and the distance between IGBT pins and the capacitors are kept small. There is no need to employ high-speed IGBT in the auxiliary circuit, and low-speed IGBTs with low-conduction losses can be selected. The conduction losses of the auxiliary switches are very low, and the switching losses can be neglected. Thus, rated current of the auxiliary switches can be selected lower than the main switches. Auxiliary switch drive signal, VGE1A , is started just before high-to-low transition of VGE1 signal, and continues until D2 diode turns on. Auxiliary switch drive signal, VGE2A , is started just before high-to-low transition of VGE2 signal, and continues until D1 diode turns on. To prevent chatter in the transition from Mode-1 to Mode-2, 5 A hysteresis band is included in the control circuitry of the proposed converter. VAB and IP waveforms are given in Fig. 9(a) for 10% load. VGE1 , IS 1 , and VS 1 waveforms are given in Fig. 9(b) for 10% load (I0 = 20 A). The initial value of the primary current is 4 A, and it decreases to zero at the end of the lagging leg transition.
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The equivalent parallel capacitor value in the lagging leg is 5 nF. The snubber capacitor is not discharged completely because the energy of LS is not sufficient. Snubber capacitor is discharged through Q1 as seen in Fig. 9(b). Parasitic oscillation occurs in the VGE1 gate signal due to the hard switching. IGBT switching loss and the parasitic oscillation are quite low because the value of snubber capacitance is small. VAB and IP waveforms are given in Fig. 9(c), and VGE1 , IS 1 , and VS 1 waveforms are given in Fig. 9(d) for 80 A output current (IP 0 = 16 A). The lagging leg resonance duration is 200 ns, and at the end of this time current falls to zero. In this interval, the snubber capacitor voltage rises from zero to input voltage by means of the energy in LS . After D2 diode turns on with ZVS, primary current falls to zero linearly. The turn-on signal of Q2 is applied after D2 turns on. As soon as the diode turns off Q2 turns on with ZVS. VAB , VC , IP , and IAUX waveforms are given in Fig. 9(e), and VGE1 , IS 1 , and VS 1 waveforms are given in Fig. 9(f) for 110 A output current. The auxiliary circuit starts to operate at 105 A output current. For Io = 110 A, parallel capacitor voltage VC falls to zero as shown in Fig. 9(e). It can be seen that from Fig. 9(f), Q1 switch turns on with ZVT and turns off with ZVS. VAB , VC , IP , and IAUX waveforms are given in Fig. 9(g), and VGE1 , IS 1 , and VS 1 waveforms are given in Fig. 9(h) for 180 A output current. At the beginning of the lagging leg resonance, primary current value is 36 A. Auxiliary switches are operated with soft switching. The conduction losses of auxiliary switches are quite small. High-value capacitor is connected to Q1 in parallel thus the turn-off switching loss of the Q1 switch is decreased. The high-frequency noise in the waveforms partially originates from measurement system. The voltage probe (1 MΩ, 100 X) used to measure the voltages is affected from the noise due to high-output current in the circuit. Besides, the distances allocated for current measurement increased parasitic inductance on the PCB and increases parasitic oscillations. Parasitic oscillations on output diodes are decreased to acceptable levels by using saturated inductance. From Fig. 9(g) it is seen that the current changes direction in 1.5 μs for Io = 180 A. For 75 kHz operating frequency, the duty cycle loss ΔD at nominal output current is calculated as 22%. Efficiency curves of the IGBT-based proposed converter, MOSFET-based converter, and conventional IGBT-based converter for the full power range are given in Fig. 10. The input voltage is selected as Vd = 360 V. The losses of the PFC frontend stage are not included in the efficiency curves. The calculated efficiency values are primarily based on IGBT and diode losses. The transformer, inductor, and other circuit losses could not be taken into account precisely in the calculations. Thus, there is a small difference between the theoretical and experimental efficiency values as seen in Fig. 10. The experimental efficiency can be increased by decreasing the transformer and inductance losses. The calculated loss distributions are given for nominal output power in Fig. 11. It is seen that the highest loss in the converter is due to the output diodes, and auxiliary circuit loss percentage is quite low. Using MOSFET instead of IGBT increases converter efficiency along with cost increase.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Fig. 9. Experimental waveforms from the proposed converter. (a) V A B and Ip waveforms at Io = 20 A. (b) V G E 1 , IS 1 and V S 1 waveforms at Io = 20 A. (c) V A B and Ip waveforms at Io = 80 A. (d) V G E 1 , IS 1 and V S 1 waveforms at Io = 80 A. (e) V A B , V c , IP and IA U X waveforms at Io = 110 A. (f) V G E 1 , IS 1 and V S 1 waveforms at Io = 110 A. (g) V A B , V c , IP and IA U X waveforms at Io = 180 A. (h) V G E 1 , IS 1 and V S 1 waveforms at Io = 180 A.
BAKAN et al.: IMPROVED PSFB PWM DC–DC CONVERTER FOR HIGH-POWER AND FREQUENCY APPLICATIONS
Fig. 10.
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2) It is possible to select resonant inductance smaller and to decrease duty cycle loss. Auxiliary circuit is started at high currents, so the required energy for discharging high-valued snubber capacitors is available. 3) Transformer conversion ratio can be selected higher, thus resulting in lower conduction losses. 4) At no load, detrimental effects of the surge current to the IGBT and snubber capacitors are prevented, and turn-off switching losses of the IGBTs are decreased. 5) All semiconductor devices in the circuit are switched under soft switching at wide load range. The main switches are perfectly turned on and turn off with ZVT and ZVS, respectively. The auxiliary switches are turned on and turn off with ZVS. 6) At very low-current levels soft switching is lost but in this case, the switching losses are negligible. The operation principles and theoretical analysis of the new converter were completely verified by a prototype of a 10 kW output power, 200 A output current, and 75 kHz switching frequency. At full load, conventional PSFB PWM converter requires five times higher resonant inductance than that of the proposed converter. The duty cycle loss of the proposed converter is much lower than the conventional PSFB PWM converter. Thus, the proposed PSFB PWM converter can be operated at higher frequencies than conventional PSFB PWM converter.
Efficiency curves.
REFERENCES
Fig. 11. Power loss distribution for nominal output power. (a) Proposed IGBT based converter. (b) MOSFET based converter. (c) Conventional PSFB converter.
V. CONCLUSION In this study, a new method enabling the use of high-valued snubber capacitors with the lagging leg of the PSFB PWM converter is developed. Thanks to the new method, the turnoff switching losses are decreased, and the performance of the converter is improved at high currents. In the proposed PSFB PWM converter, IGBTs are used instead of MOSFETs due to their low cost and low-conduction losses. Auxiliary circuit is operated only during charging/discharging of capacitor at the lagging leg thus conduction loss is low. The control and design principles are similar to the conventional PSFB PWM converter. The proposed topology has the following advantages compared to the other PSFB PWM converters presented in the literature: 1) Turn-off losses of the lagging leg IGBTs are decreased by the use of high-valued snubber capacitors.
[1] H. Bodur and A. F. Bakan, “A new ZVT–ZCT–PWM DC–DC converter,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 676–684, May 2004. [2] A. F. Bakan, H. Bodur, and ˙I. Aksoy, “A novel ZVT-ZCT PWM DC-DC converter,” presented at the 11th Eur. Conf. Power Electron. Appl. (EPE), Dresden, Germany, Sep. 2005. [3] H. Bodur and A. F. Bakan, “An improved ZCT-PWM DC-DC converter for high-power and frequency applications,” IEEE Trans. Ind. Electron., vol. 51, no. 1, pp. 89–95, Feb. 2004. [4] I. Aksoy, H. Bodur, and A. F. Bakan, “A new ZVT–ZCT–PWM DC–DC converter,” IEEE Trans. Power Electron., vol. 25, no. 8, pp. 2093–2105, Aug. 2010. [5] A. F. Bakan, ˙I. Aksoy, N. Altıntas¸, and H. Bodur, “An experimental investigation of switching losses of the IGBT in PSFB PWM DC-DC converters depending on the parallel snubber capacitor,” presented at the Electron., Telecommun. Artificial Intell. (ETAI) Conf.: [E4-2, CD ROM], Ohrid, Macedonia, Sep. 26–29, 2009. [6] A. F. Bakan, “A new LVI assisted PSFB PWM DC-DC converter,” in Proc. 6th Int. Conf. Electr. Electron. Eng. (ELECO), Bursa, Turkey, Nov. 5–8, 2009, pp. 230–233. [7] J. G. Cho, “IGBT based zero voltage transition full bridge PWM converter for high power applications,” IEE Trans. Electr. Power Appl., vol. 143, no. 6, pp. 475–480, Nov. 1996. [8] M. Borage, S. Tiwari, S. Bhardwaj, and S. Kotaiah, “A full-bridge DC–DC converter with zero-voltage-switching over the entire conversion range,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1743–1750, Jul. 2008. [9] S. Hamada and M. Nakaoka, “Analysis and design of a saturable reactor assisted soft-switching full-bridge dc–dc converter,” IEEE Trans. Power Electron., vol. 9, no. 3, pp. 309–317, May 1994. [10] S. Jeon and G. H. Cho, “A zero-voltage and zero-current switching full bridge DC–DC converter with transformer isolation,” IEEE Trans. Power Electron., vol. 16, no. 5, pp. 573–580, Sep. 2001. [11] E. Kim and Y. Kim, “A ZVZCS PWM FB DC/DC converter using a modified energy-recovery snubber,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1120–1127, Oct. 2002. [12] Y. Jang, M. M. Jovanovic, and Y. Chang, “A new ZVS-PWM full-bridge converter,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1122–1129, Sep. 2003.
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[13] Y. Jang and M. M. Jovanovic, “A new family of full-bridge ZVS converters,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 701–708, May 2004. [14] G. Koo, G. Moon, and M. Y. Youn, “New zero-voltage-switching phaseshift full-bridge converter with low conduction losses,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 228–235, Feb. 2005. [15] B. Lin, H. Chiang, and C. Chen, “Analysis and implementation of a ZVS-PWM converter with series-connected transformers,” IEEE Trans. Circuits Syst.—II: Express Briefs, vol. 54, no. 10, pp. 917–921, Oct. 2007. [16] W. Chen, X. Ruan, and R. Zhang, “A novel zero-voltage-switching PWM full bridge converter,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 793–801, Mar. 2008. [17] J. A. Sabat´e, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “Design considerations for high-voltage high-power full-bridge zero voltageswitching PWM converter,” in Proc. IEEE APEC Conf. Rec., 1990, pp. 275–284. [18] R. Redl, N. O. Sokal, and L. Balogh, “A novel soft-switching full-bridge dc/dc converter: Analysis, design considerations, and experimental results at 1.5 kW, 100 kHz,” IEEE Trans. Power Electron., vol. 6, no. 3, pp. 408– 418, Jul. 1991. [19] J. G. Cho, J. A. Sabat´e, and F. C. Lee, “Novel full bridge zero voltagetransition PWM dc/dc converter for high power applications,” in Proc. IEEE-APEC Conf. Rec., 1994, pp. 143–149. [20] R. Redl, L. Balogh, and D. W. Edwards, “Optimum ZVS full-bridge dc/dc converter with PWM phase-shift control: Analysis, design considerations, and experimentation,” in Proc. IEEE APEC Conf. Rec., 1994, pp. 159– 165. [21] X. Ruan and Y. Yan, “A novel zero-voltage and zero-current switching PWM full-bridge converter using two diodes in series with the lagging leg,” IEEE Trans. Ind. Electron., vol. 48, no. 4, pp. 777–785, Aug. 2001. [22] G. Hua, F. C. Lee, and M. M. Jovanovic, “An improved full-bridge zerovoltage-switched PWM converter using a saturable inductor,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530–534, Oct. 1993. [23] A. F. Bakan, H. Bodur, ˙I. Aksoy, and N. Altıntas¸, “A review of the full bridge PSFB PWM DC-DC converters,” in Proc. Electr.-Electron. Comput. Eng. Conf. (ELECO), Bursa, Malaysia, Nov. 2008, pp. 366–370. [24] J. Dudrik, P. Sp´anik, and N. Trip, “Zero-voltage and zero-current switching full-bridge DC–DC converter with auxiliary transformer,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1328–1335, Sep. 2006. [25] C. Bo-Yuan and L. Yen-Shin, “Switching control technique of phase-shiftcontrolled full-bridge converter to improve efficiency under light-load and standby conditions without additional auxiliary components,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 1001–1012, Apr. 2010. [26] Z. Xin, H. S. Chung, R Xinbo, and A Ioinovici, “A ZCS full-bridge converter without voltage overstress on the switches,” IEEE Trans. Power Electron., vol. 25, no. 3, pp. 686–698, Mar. 2010. [27] S. Bontemps, “Turn-off snubber design for high frequency modules,” Advanced Power Technology Europe, Application Note APT0404, Dec. 2004, France.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
A. Faruk Bakan was born in Istanbul, Turkey, in 1972. He received the B.S. degree in electronics and communication engineering, the M.S. degree in electrical engineering, and the Ph.D. degree in electrical engineering from Yildiz Technical University, Turkey, in 1994, 1997, and 2002, respectively. Since 2002, he has been an Assistant Professor in the Department of Electrical Engineering, Yildiz Technical University. He has published 20 journal and conference papers in the area of power electronics. He was also employed in seven research projects concerning power electronics. His research interests include direct torque control, photovoltaic inverters, welding machines, and soft switching techniques in power electronics.
Nihan Altintas¸ was born in Balikesir, Turkey, in 1980. She received the B.S. and M.S. degrees in electrical engineering from Yildiz Technical University, Turkey, in 2004 and 2007, respectively, she is working toward the Ph.D. degree in electrical engineering. She is also a Research Assistant in the Department of Electrical Engineering, Yildiz Technical University. Her research interests include dc–dc converters, welding machines, and soft switching techniques in power electronics. She was also employed in two research projects concerning power electronics.
˙ Ismail Aksoy was born in Cologne, Germany, in 1977. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Yildiz Technical University, Yildiz, Turkey, in 1999, 2001, and 2007, respectively. From 1999 to 2008, he was a Research Assistant in the Department of Electrical Engineering, Yildiz Technical University. Since 2008, he has been an Assistant Professor in the Department of Electrical Engineering, Yildiz Technical University. He has published more than 15 journal and conference papers in the field of power electronics. He was also employed in three research projects concerning power electronics. His research interests include power factor correction, switching power supplies, high-frequency power conversion, and active and passive snubber cells in power electronics.
