An Improved Zero-Voltage-Switching Inverter Using Two Coupled

An Improved Zero-Voltage-Switching Inverter Using Two Coupled Magnetics In One Resonant Pole Wensong Yu, Jih-Sheng Lai and Sung-Yeul Park Virginia Polytechnic Institute and State University Future Energy Electronics Center Whittemore Hall, Blacksburg, VA 24061-0111, USA

[email protected], [email protected], [email protected] Abstract-A novel soft switching inverter using two small coupled magnetics in one resonant pole is proposed to guarantee the main switches operating at zero-voltage-switching (ZVS) from zero load to full load and the auxiliary switches at zero-currentswitching (ZCS) with load adaptability and small current stress. Since independent magnetics structure avoids the unwanted magnetizing current freewheeling loop, the size of the coupled magnetics can be minimized with low magnetizing inductance and the saturable inductor is eliminated. Detailed circuit operation is described and voltage-second balance condition of the magnetics is expressed mathematically. A 4-kW hardware prototype has been designed, fabricated and tested to verify the validity of the novel circuit and the improved performs of the proposed soft switching inverter. Experimental results show excellent agreement with analytical results.

(2) use of commercially half-bridge module, (3) reduced peak current for the auxiliary switches and diodes because both transformer primary and secondary windings are supplying or sinking the resonant current during the switching transition, (4) simplified gate timing control because of possible non-unity turns ratio for coupled magnetics [4], and (5) no limitation on commutations in any number of phases. However, the problem in the basic ZVS inverter using coupled magnetics is that the magnetizing inductor cannot be reset [6]. Fig. 2 shows the unexpected loop of freewheeled magnetizing current when the load current is positive. If the magnetizing current cannot be reset before the next commutation, it is accumulated and might cause the saturation of the magnetic core.

Index Terms-Inverter, zero-voltage switching, zero-current switching, load adaptability, coupled magnetic.

I.

This material is based upon work supported by the U.S. Department of Energy (DOE) under Award Number DE-FC26-07NT43214.

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DC+

Q1

DX1 DX4

INTRODUCTION

C1 TX1

Zero-voltage switching (ZVS) inverters on ac side using either split capacitors or coupled magnetics to reset resonant current have been around for more than two decades [1]-[10]. The auxiliary resonant commutated pole (ARCP) inverter is well known for its use of split capacitors to reset the resonant current [1]-[3]. The main switches of this type of inverters turns on at ZVS, and the auxiliary switches only operate during the switching transition with ZCS. However, the split capacitors suffer from such problems as capacitor charge balance and requirement of reverse voltage blocking device for the auxiliary switch. In addition, this soft-switching inverter has issues in gating control complexity and auxiliary devices protection. As shown in Fig. 1, the soft-switching inverters using coupled magnetics have been proposed to avoid capacitor voltage balance issue and reverse voltage blocking device requirement [4]-[8]. The auxiliary power circuit consists of two active switches (QX1, QX2), one transformer (TX1) with its leakage inductance as the resonant inductor, and four diodes (DX1-DX4). The distinctive features of this coupled magnetics ZVS inverter are (1) no limitation on capacitor charge balance,

*

QX1

Load Q2

QX2

C2

DX2 DX3

DC-

Fig. 1 Basic Circuit of the ZVZCS inverter using coupled magnetics

QX1

C1

C QX2

B TX1

DX2 DX3

DC+

Q1

DX1 DX4

A

Load

Q2 C2 DC-

Fig. 2 Unexpected loop of freewheeled magnetizing current at positive load current.

The state-of-the-art approaches to solving the magnetizing current reset problem are shown in Fig. 3 [6]. The first approach is to break the unwanted loop at point A in Fig. 2 with the use of a saturable inductor, as shown in Fig. 3 (a). This approach maintains all the basic features of original

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coupled-magnetic ZVS inverter, except that it needs a largesize transformer to reduce the magnetizing current so that the saturable current is larger than the magnetizing current. In this case, it is difficult to cool the saturable inductor due to a large core loss in a small volume. The second approach to break the unexpected loop at point B in Fig. 2 is to insert two diodes (Dx5, Dx6), as shown in Fig. 3(b) [6], to provide a reset voltage during resonance. Because these added diodes do not share resonant current, the auxiliary switches current equals the resonant current, which is much higher than the case in the original coupled magnetic inverters. The added diodes circulate the reset current, which introduces a voltage across the transformer that reduces effective resetting voltage, and thus requiring longer resonant interval, which equivalently reduces the effective duty cycle. QX1

DC+

Q1

DX1 DX4

DX6

C1

TX1

DC-

DX1 DX4 DX5

Load

DX2 DX3 DX6

Lr = Lr1 = Lr 2 = 2 ⋅ Llk , pri ⋅ (

C2 DC-

n 2 ) n +1

(1)

where Llk,pri is the primary side leakage inductance.

(b) Fig. 3. ZVZCS inverter with (a) saturable inductor or (b) with separated secondary winding to reset magnetizing inductor

DX6

II. IMPROVED CIRCUIT TOPOLOGY AND OPERATING PRINCIPLE Fig. 4 shows the single-leg circuit configuration of the proposed ZVS inverter. The upper switch Q1 and its body diode pair and lower switch MOSFET Q2 and its body diode are the same switch pairs in a conventional hard-switching inverter and are the main switches that conduct the load

QX1 DX1

Q1

DX3

GX1

In this paper, a novel soft-switching inverter topology is proposed to keep all the advantages of the basic coupledmagnetic type ZVS inverter and to solve magnetizing current resetting problem by using two small auxiliary coupled magnetics in one resonant pole. To verify the proposed approach, a 4 kW hardware prototype has been designed, fabricated and tested. The experimental results verify the effectiveness of the proposed approach in resetting the magnetizing current and Z.

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DC-

Fig. 5 shows the complete equivalent transformer circuit for the coupled magnetics. The equivalent resonant inductance, which has been derived in [4], is shown in (1).

Q2

QX2

C2

Fig. 4. Circuit configuration for the proposed ZVZCS inverter

C1

Lr

Q2 TX1 DX5 DX4

GX2

DC+

Q1

TX1

C1

QX2 DX2

C2 (a)

QX1

DC+

Q1

DX3

Load

Q2

DX2 DX3

QX1 DX1 GX1

Load M1

QX2

current during pulse-width-modulated (PWM) cycle. Q1 is to conduct the positive load current, and body diode of Q1 is to conduct the negative freewheeling current. Q2 is to conduct the negative load current, while the body diode of Q2 is to conduct the positive freewheeling current. Gate signals G1 controls Q1, and G2 controls Q2. The dc bus voltage Vdc across DC+ and DC– rails can be supplied by a power supply or battery. The auxiliary resonant current can be established by turning on the auxiliary switch that conducts the resonant current through the respective coupled resonant inductor. Resonant capacitors C1 and C2 are connected across the main switches to slow down the device voltage slew rate and to reduce the turn-off loss. In order to have wider range of zero-voltage period, the proposed coupled inductors should have a turns ratio of n > 1, where n is the turns ratio of the secondary winding and the primary winding.

Lr2 Lm2 TX2 v T Lm1+ Lm1- iLm1X1 QX2 DX2 GX2

G1

Load ir

Lr1 Q 2 DX5 DX4

+ DC+ vDS1 C1 -

G2

iL C2 DC-

Fig. 5. Equivalent circuit for the proposed ZVZCS inverter

The auxiliary resonant circuit operation can be explained by the gate timing sequence and associated key voltage and current waveforms. Fig. 6 shows the basic operation for the positive large load current. This figure assumes that initially the load current is positive, and the bottom freewheeling diode D2 conducts the load current IL. In the proposed gating timing control, the auxiliary switch gate Gx1 or Gx2 is controlled by the

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PWM command with dead time. The rising edge of the main switch gate G1 or G2 is controlled by zero-voltage (ZV) logic and PWM command. The falling edge of the main switch gate G1 or G2 is controlled by a fixed-time delay logic. PWM

PWM

Gx1 ZV logic

Delay logic

G1 PWM

PWM Gx2 Delay logic

ZV logic

G2 IL Ir VDS1 VLm1 iLm1 t0 t1 t2 t3

t4

t5 t6 t7 t8 t9

Fig. 6. Gate timing diagram and key voltage and current waveforms

From circuit topological changes, the complete circuit operation can be divided into the following ten time intervals. Their corresponding circuit operation diagrams are shown in Fig. 7. [t0, t1]: At t0, the bottom main switch Q2 turns off at zerovoltage condition. Because its anti-paralleled diode conducts initially, the turn-off action does not create any change in voltage and current waveforms. [t1, t2]: At t1, the upper auxiliary switch gate Gx1 is turned on by the PWM command. The auxiliary switch Qx1 and the auxiliary diode Dx4 are conducting and producing a resonant current iLr through Lr1. Initially the resonant current rises linearly with a slope proportional to the dc bus voltage and anti-proportional to the inductance of the coupled magnetics, Lr. Simultaneously, a magnetizing current iLm1 is established and increased with a constant slope. [t2, t3]: At t2, iLr exceeds the load current, and its excess portion will charge and discharge the resonant capacitors C2 and C1, respectively. With C1 being discharged, switch voltage VDS1 starts falling, and with C2 being charged, bottom switch voltage VDS2 starts rising. [t3, t4]: At t3, C1 and C2 are fully discharged and charged. When the VDS1 falls to zero, the upper main switch gate G1 is turned on by zero-voltage logic and Q1 can then be turned on under zero-voltage condition. The resonant current starts falling, and its slope depends on the secondary inductance of the coupled magnetic. With turns ratio larger than 1, the slope can be gentler, and the zero-voltage crossing period can be

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widened. [t4, t5]: At t4, the auxiliary diode Dx4 is turned off. The resonant current ILr falls to the magnetizing current. Magnetizing current remains constant after this point because the voltage across the winding is zero. [t5, t6]: At t5, the auxiliary switch Qx1 turns off by PWM command. The auxiliary diode Dx5 is turned on, and the magnetizing current starts resetting. Because the resetting voltage is the dc bus voltage, the time to fully reset the magnetizing current is very short. [t6, t7]: At t6, the magnetizing current is fully reset, and the auxiliary diode Dx5 is turned off. From t6 to t7, the upper main switch Q1 is conducting the total load current. [t7, t8]: At t7, Q1 is turned off by the delay logic. The current in Q1 starts shifting out to charge and discharge C1 and C2. With C1 being charged, switch voltage VDS1 starts rising, and with C2 being discharged, the bottom switch voltage VDS2 starts falling. [t8, t9]: At t8, capacitor C1 is fully charged, and VDS1 rises to the dc bus voltage. Meanwhile, capacitor C2 is fully discharged, and VCE2 falls to zero. The load current is conducted in the bottom freewheeling diode D2. [t9, t0]: At t9, the main switch Q2 is turned on by PWM command under zero-voltage condition, and Q2 and its body diode conduct the freewheeling load current. When the bottom auxiliary switch Qx2 is turned off by PWM command under zero-current condition, the turn-off action does not create any change in voltage and current waveforms. III. ANALYSIS AND DESIGNING OF THE MAGNETIZING INDUCTOR The calculation of reset time trst for the coupled magnetics is based on the fact that the integral of the applied magnetic inductor voltage must be zero in every switching period. The voltage-second balance condition can be expressed as:

∫

Ts

0

vLm (t )dt = 0

(2)

The magnetizing inductor voltage shown in Fig. 7 can be obtained from the equivalent circuit shown in Fig. 8. The equation (1) can be rearranged as:

∫

t4 ⎛

t1

N1 ⋅VDC ⎞ ⎜ ⎟ dt + ⎝ N1 + N 2 ⎠

∫

t6 ⎛

t5

Lm ⋅VDC ⎞ ⎜− ⎟ dt = 0 ⎝ Lm + Lr ⎠

(3)

Here N1 is the number of turns of the primary winding connected with the auxiliary active switch, N2 is the number of turns of the secondary winding, VDC is the dc link voltage, Lm is the magnetizing inductance, and Lr is the equivalent resonant inductance. Timing points t1-t6 are shown in Fig. 6. From the equivalent circuit shown in Fig. 8, the total resonant current interval ΔTr can be derived as ΔTr =

2⎤ ⎡ ⎛N ⎞ ⎛N ⎞ Lr ⎢ L ⎛ N N ⎞ π − cos −1 ⎜ 1 ⎟ + 1 − ⎜ 1 ⎟ ⎥ + V r ⋅ ⎜ 2 + 1 + 2 ⎟ (4) DC ⎥ Zr ⎢ N N N N1 ⎠ 2 ⎝ 2⎠ ⎝ 2 ⎠ ⎥ I Load ⎝ ⎣⎢ ⎦

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Dx 6

Qx1 Gx1

Dx1

Dx 3 TX 2 Lm 2

Lm1

Qx 2

Dx 5 Gx 2

+

VLm1

Lr

DC + + VDS 1 − C1 Load

Q1 G1

− iLm1

ir

TX 1 Dx 4

Dx 6

Gx1

Dx1

Lm 2

iL

Qx 2 Q2 G2

Dx 3 TX 2

Lm1

Lr

Dx 2

Qx1

Dx 5

C2

Gx 2

DC −

+

VLm1

Qx1 Gx1

Dx1

Dx 3 TX 2 Lm 2

Lm1

Qx 2

Dx 5 Gx 2

+

VLm1

ir

TX 1 Dx 4

Lr

DC + + VDS 1 − C1 Load

Q1 G1 ir

Dx 6

Qx1 Gx1

Dx1

Lm 2

iL

Qx 2 Q2 G2

Dx 3 TX 2

Lm1

Lr

Dx 2

Qx1 Gx1

Dx1

Dx 3 TX 2 Lm 2

Lm1

Qx 2

Dx 5 Gx 2

+

VLm1

Dx 5

C2

Gx 2

DC −

+

VLm1

Lr

DC + + VDS 1 − C1 Load

Q1 G1 ir

Dx 6

Gx1

Dx1

Dx 3 TX 2 Lm 2

Lm1

Qx 2 Dx 5 Gx 2

+

VLm1

ir

Qx1 Gx1

Dx1

Lm 2

Qx 2 Q2 G2

Dx 3 TX 2

Dx 5

C2

Gx 2

DC −

+

VLm1

Lr

DC + + VDS 1 − C1 Load

Q1 G1

ir

Gx1

Dx1

Dx 3 TX 2 Lm 2

Lm1

Qx 2

Dx 5 Gx 2

+

VLm1

Dx 6

ir

TX 1 Dx 4

Qx1

iL

Q2 G2

Gx1

Dx1

Lm 2

Qx 2 Q2 G2

Dx 3 TX 2

Lm1

Lr

C2 DC −

Dx 5

C2

Gx 2

DC −

+

VLm1

Lr

DC + + VDS 1 − C1 Load

Q1 G1

− iLm1

ir

iL

Lr

TX 1 Dx 4

Q2 G2

Dx 2

C2 DC −

[t6, t7]

Lr

DC + + VDS 1 − C1 Load

Q1 G1 ir

Dx 2

Q1 G1

Lr

Dx 2

iL

− iLm1

TX 1 Dx 4

Lr

DC + + VDS 1 − C1 Load

[t7, t8]

Dx 2

Qx1

C2 DC −

− iLm1

[t3, t4] Dx 6

iL

Q2 G2

Dx 2

iL

− iLm1

TX 1 Dx 4

Q1 G1

Lr

TX 1 Dx 4

Lm1

Lr

Dx 2

Qx1

Lr

DC + + VDS 1 − C1 Load

− iLm1

[t2, t3] Dx 6

C2 DC −

[t8, t9]

− iLm1

TX 1 Dx 4

Q2 G2

Dx 2

[t1, t2] Dx 6

iL

Lr

[t9, t0]

− iLm1

TX 1 Dx 4

Q1 G1

− iLm1

[t0, t1] Dx 6

Lr

DC + + VDS 1 − C1 Load

Dx 6

Qx1 Gx1

Dx1

Lm 2

Lm1

iL

Lr

Qx 2 Q2 G2

Dx 3 TX 2

Dx 5

C2

Gx 2

DC −

[t4, t5]

+

VLm1

Lr

DC + + VDS 1 − C1 Load

Q1 G1

− iLm1

TX 1 Dx 4

ir

iL

Lr Q2 G2

Dx 2

C2 DC −

[t5, t6]

Fig. 7 Topological circuit changes in each operating interval for the proposed ZVZCS inverter

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im

N1 iVDC N1 + N 2

N1 iVDC N1 + N 2

Lm v m

N 2 iVDC N1 + N 2

ir

Lr

Main power board

Lm v m i r Lr

N 2 iVDC N1 + N 2

im L m vm ir

VDC

Lr

[ t3, t4 ]

Cr

vm i m L m ir

MOSFET

Lr

Fig. 9. Photograph of the proposed single-phase soft-switching inverter.

[ t5, t6- ]

B. Experimental Results

Fig. 8 Equivalent circuit during magnetic setting and resetting period

Here Z r =

Lr

( C1 + C2 )

, N2>N1, ILoad is load current.

Equation (4) shows that the total resonant current interval ΔTr is a function of resonant circuit parameters, number of turns of coupled magnetics, DC link voltage, and the load current. From (2) and (3), the reset time trst for the coupled magnetics can be derived as

trst

DSP board

Coupled magnetics

[ t2, t3 ]

[ t1, t2 ]

N1 iVDC N1 + N 2

im

L + Lr N1 ≥ ( t6 − t5 ) = m ⋅ ⋅ ΔTr Lm N1 + N 2

Fig. 10 shows experimental waveforms of output currents, iLoad, and output voltage vo at 400 V input voltage and full-load 4 kW operation. The output current rms value is 18.2 A, the output voltage rms value is 220 V, and the line frequency is 60 Hz. With 20 kHz switching frequency, the ripple of output voltage and current is quite small.

vo (100V/div)

(5)

iLoad (20A/div)

Here ΔTr is the total resonant current interval in the worst case under the maximum load current and minimum dc link voltage.

t (2ms/div)

Fig. 10. Experimental output current and output voltage

IV. EXPERIMENTAL VERIFICATION

A. Prototype Description Fig. 9 shows the photograph of the prototype single-phase full-bridge ZVZCS inverter using four magnetics in two resonant poles. A digital control board with a Texas Instruments TMS320F2808 DSP has been used to generate sinusoidal PWM signals. Eight channels of MOSFET/IGBT gate drivers are provided by using MC33153 with variable ZVS timing and magnetizing reset timing control circuit in the main power board. The main devices are Cool MOSFET, IPW60R045 (650 V/60 A, 45 mΩ @Tj = 25 °C) with TO247 package, the auxiliary devices are IGBT, SKW30N60 (600 V/30 A), and the auxiliary diodes are ultrafast diodes MUR460 (600 V/4 A). The resonant capacitors are polypropylene type, rated at 6.8 nF, 600 V, and the resonant inductance is 6 µH, as the leakage part of the coupled magnetics. The coupled magnetics are made with ETD-39 ferrite 3C94 cores, with a magnetizing inductance of 700 µH. The turn ratio N2/N1 is 1.4:1. A low-pass filter (Lf = 1.26 mH, Cf = 10 µF) is used as the output filter. Specifications of the inverter are as follows: dc link voltage VDC = 400 V; output power Po = 4 kW; output voltage Vo,RMS = 220 V; modulation index M = 0.9; switching frequency fsw = 20 kHz.

978-1-422-2812-0/09/$25.00 ©2009 IEEE

Fig. 11 shows experimental waveforms of auxiliary gate voltage vGE, device voltage vCE and device current iQx1. Before the auxiliary switch gate is turned off, the device current iQx1 is zero, so the auxiliary switch clearly operates at ZCS condition, and the coupled magnetics is reset. It also can be seen that the noise signal on gate voltage is very small.

vCE (100V/div) vGE (10V/div) ZCS iQx1 (20A/div) t (10µs/div)

Fig. 11. Experimental auxiliary switch ZCS waveforms of gate voltage, device current and voltage

The complete fundamental cycle auxiliary switch current iQx1 and load current iLoad are shown in Fig. 12. The peak auxiliary switch current follows the load current with clear load adaptability. It can be seen that the smaller load current,

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the smaller auxiliary switch current. During the half cycle of the negative load current, the auxiliary switch current remains zero. Therefore, the auxiliary switch rms current stress is very low.

iQx1 (20A/div)

iLoad (20A/div) t (2ms/div)

Fig. 12. Auxiliary switch ZCS load adaptability experiments of device and load current

Fig. 13 shows the experimental verification of main switch ZVS operation with load current adaptability. Fig. 13(a) shows the device voltage vds and gate voltage vgs at zero current condition, and Fig. 13(b) shows vds and vgs at rated load current condition (24 A). Both figures clearly indicate that ZVS is achieved by observing that vds drops to zero before vgs turns on at different output current levels. The gate voltage is +15 V for turn-on and –5 V for turn-off. The noise in this case is very small, and both gate and drain voltages are very clean.

structure. The distinctive features of the proposed design can be summarized as follows. 1. Independent two coupled magnetics structure avoids the unexpected magnetizing current circulating loop to eliminate the need for saturable inductor. 2. With magnetizing current reliably reset in every PWM switching cycle, the size of the coupled magnetics can be minimized with low magnetizing inductance. 3. The auxiliary switch current follows the load current adaptively and is zero in the entire negative fundamental cycle, thus the rms-current stress of the auxiliary switch is half of that in a single coupled magnetics per resonant pole case. The proposed inverter has been designed, implemented, and tested for a 4 kW system. Experimental results agree with analytical results very well. REFERENCES [1] [2] [3] [4]

vDS (100V/div)

[5]

vGS (10V/div)

[6] io=0

ZVS

[7] t (2µs/div)

(a)

[8]

vDS (100V/div)

[9]

vGS (10V/div)

[10] ZVS io=24A

[11] t (2µS/div)

(b) Fig. 13. Main switch ZVS load adaptability experiments under 400 V dc bus voltage with different load conditions: (a) zero load; (b) full load Io = 24 A.

[12]

V. CONCLUSION

[13]

A novel inverter has been proposed using two small coupled magnetics in one resonant pole to have the main switches operating at ZVS condition and the auxiliary switches operating under ZCS condition. The auxiliary switch RMS current stress is small with such a two coupled-magnetic

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[14]

W. McMurray, “Resonant Snubbers With Auxiliary Switches,” in Proc. IEEE Ind. Appl. Soc., San Diego, CA, Oct. 1989, pp. 829-834. R. W. DeDoncker and J. P. Lyons “The auxiliary resonant commutated power converters,” in Proc. IEEE Ind. Appl. Soc., Oct. 1990, pp. 12281235. D. M. Divan, G. Venkataramanan, R. W. DeDoncker, “Design Methodologies for Soft Switched Inverters,” IEEE Trans. Ind. Appl., Vol. 29, no. 3, Jan./Feb. 1993, pp. 126-135. J.-S. Lai, J. Zhang, H. Yu, and H. E. Kouns, “Source and Load Adaptive Design for a High-Power Soft-Switching Inverter,” IEEE Trans. Power Electron., Vol. 21, no. 6, Nov. 2006, pp. 1667-1675. I. Barbi and D. C. Martins, “A true PWM zero-voltage switching pole with very low additional RMS current stress,” in Proc. IEEE Power Electron. Spec. Conf., 1991, pp. 261–267. X. Yuan and I. Barbi, “Analysis, designing, and experimentation of a transformer-assisted PWM zero-voltage switching pole inverter,” IEEE Trans. Power Electron., vol. 15, no. 1, Jan. 2000, pp. 72-82. J. P. Gegner and C. Q. Lee “Zero-voltage-transition converters using inductor feedback techniques,” in Proc. IEEE Appl. Power Electron. Conf., 1994, pp. 862-868. S. Frame , D. Katsis , D. H. Lee , D. Borojevic and F. C. Lee “A threephase zero-voltage-transition inverter with inductor feedback,” in Proc. VPEC Sem. Blacksburg, VA, 1996, pp. 189-194. J.-S. Lai, R. W. Young , J. McKeever and F. Z. Peng “A delta configured auxiliary resonant snubber inverter,” IEEE Trans. Ind. Appl., vol. 32, May/Jun. 1996, pp. 518-524. J. S. Lai, “Practical design methodology of auxiliary resonant snubber inverter,” in Proc. IEEE Power Electron. Spec. Conf., Baveno, Italy, Jun. 1996, pp. 432-437. H. Yu, X. Huang and J.-S. Lai, “A novel load adaptive zero voltage switching utilizing diode reverse recovery current for soft-switching choppers and inverters,” in Proc. IEEE Power Electron. Spec. Conf., Vancouver, BC, Jun. 2001, pp. 146-151. W. Dong, D. Peng, H. Yu, F. C. Lee, and J.-S. Lai, “A simplified control scheme for zero voltage transition (ZVT) inverter using coupled inductors,” in Proc. Power Electron. Spec. Conf., Galway, Ireland, vol. 3, Jun. 2000, pp. 1221-1226. F. R. Salberta, J. S. Mayer, and R. T. Cooley, “An improved control strategy for a 50-kHz auxiliary resonant commutated pole converter,” in Proc. Power Electron. Spec. Conf., 1997, pp. 1246-1252. A. Toba, T. Shimizu, G. Kimura, M. Shioya, and S. Sano, “Auxiliary resonant commutated pole inverter using two internal voltage-points of DC source,” in IEEE Trans. Ind. Eletron., vol. 45, Apr. 1998, pp. 200206.

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