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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006

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An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing Alberto Valdes-Garcia, Member, IEEE, Faisal Abdel-Latif Hussien, Student Member, IEEE, José Silva-Martínez, Senior Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE

Abstract—Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35- m technology employs only 0.3 mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip. Index Terms—Analog testing, algorithmic ADC, analog multiplier, built-in testing, CMOS circuits, design for testability, multivibrator.

I. INTRODUCTION

T

HE development of modern systems-on-chip (SoC) and systems-in-package (SiP) has witnessed a continuous increase in the amount and diversity of the integrated components, which include memory, processor cores, sensors and analog/RF circuits. As the complexity of these systems has grown, their testing at both, the product development and mass-production phases, has become increasingly challenging and one of the major portions of the overall cost. While solutions for the automated test of very large memory and digital cores are relatively well established, the challenges associated with the observability and test-cost of embedded analog/RF blocks remain an important bottleneck to guarantee the cost efficiency of contemporary and future integrated systems. Conscious of these evolving challenges for the semiconductor industry, the most recent (2003) edition of the International Technology Roadmap for Semiconductors (ITRS) [1] calls for Manuscript received December 7, 2006; revised May 20, 2006. This work was supported in part by the Semiconductor Research Corporation (SRC) under Task Id# 957.000. A. Valdes-Garcia was with the Analog and Mixed Signal Center, Electrical Engineering Department, Texas A&M University, College Station, TX 778433128 USA. He is now with the Wireless System Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. F. A.-L. Hussien, J. Silva-Martínez, and E. Sánchez-Sinencio are with the Analog and Mixed Signal Center, Electrical Engineering Department, Texas A&M University, College Station, TX 77843-3128 USA. Digital Object Identifier 10.1109/JSSC.2006.881561

the development/improvement of solutions for different test issues. Some of the most important are: 1) development of SoC test methodology, including test reusability and analog/digital built-in self-test (BIST); 2) design-for-test (DfT) methods to localize failures and enable both development and production testing; 3) wafer-level test and known good die (KGD) test methodologies; and 4) analog DfT and BIST techniques that simplify test interface requirements and slow ever increasing instrument capability trends. Several BIST and DfT techniques for analog circuits have been developed in recent years; [2]–[4] present a comprehensive summary of these efforts. The majority of these reported techniques have been discussed only through simulation or board-level results and important issues related to their integrated implementation have not been addressed. Few on-chip testing schemes have been demonstrated experimentally with integrated prototypes [5]–[8]. Some of the first devices for the test of RF circuits in the gigahertz range that have been evaluated with measurements employ bipolar transistors on a SiGe process [8]. Pure CMOS built-in test solutions with small area overhead, low off-chip data processing and high frequency of operation are required. A robust technique for magnitude and phase response characterization based on an analog multiplier was introduced in [9]. Based on that approach, this work presents a complete integrated frequency response characterization system (FRCS). The goal of this system is to test the most important specifications of integrated analog circuits (gain and phase shift at different frequencies) by using very compact and simple test circuitry that communicates with automatic test equipment (ATE) through a low-speed digital interface. The application focus is on continuous-time circuits operating in the range of tens to hundreds of MHz which are the most common building blocks for baseband signal processing in SoCs. Section II describes the architecture and operation of the proposed system. The design of the building blocks developed for this test architecture (analog multiplier, multiplexer, frequency synthesizer, and algorithmic ADC) is discussed in Section III. Section IV presents the experimental results for the individual building blocks as well as for the application of the entire system in the characterization of two fourth order OTA-C filters. Finally, conclusions are drawn in Section V. II. FREQUENCY RESPONSE CHARACTERIZATION SYSTEM A general analog system, such as a line driver, equalizer or the baseband chain in a transceiver consists of a cascade of building each stage is expected to show blocks. At a given frequency

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Fig. 1. Architecture of the proposed frequency response characterization system.

a gain or loss and a delay (phase shift) within certain specifications; these characteristics can be described by a transfer func. An effective way to detect and locate catastrophic tion and parametric faults in a given analog system is to test the magof nitude and phase responses over frequency each one of its building blocks. However, the observability of embedded analog blocks is very limited and the required equipment adds extra cost to the test process. It is desirable to add on-chip testing circuitry such that the entire SoC (both analog and digital sections) can be tested with a single digital ATE. The proposed system is meant to perform these functions as shown in Fig. 1. The test architecture consists of a frequency synthesizer, an amplitude and phase detector (APD), a multiplexer that serves as an interface between the circuit under test (CUT) and the APD, and an ADC that digitizes the output of the APD which consists of DC voltages. A block diagram of the proposed APD is depicted in Fig. 2. The array of switches within the dashed-box is implemented in the multiplexer shown in Fig. 1. An analog multiplier is employed to perform, in succession, three different multipliand output cation operations between the input signals from the CUT. For each operation, a DC voltage and a frequency component at are generated; the latter is suppressed by a low-pass filter (LPF) at the output of the multiplier. The following three DC voltages are obtained sequentially:

(1) (2) (3)

where is the gain of the multiplier, and are the amplitude of the signals at the input and output of the CUT, respectively, and is the phase-shift introduced by the CUT at . From these DC outputs, the ATE can evaluate the phase and magnitude by performing the following simple responses of the CUT at operations: (4) (5) Since is proportional to the cosine of the phase, it is the absolute value of the phase what is obtained. Notice that the ) are computed using only parameters of interest ( and , , and . Neither the amplitude of the test signal nor play an important role in the computhe multiplier’s gain tations and hence do not need an accurate control. Any static DC-offset that the multiplier may have can be measured when no signals are present and then cancelled before the computaof the LPF should be only tions. The cut-off frequency small enough to suppress the high frequency components generated at the output of the analog multiplier and does not require tuning. In this way, the proposed technique is inherently robust to the effect that process variations can have on the main performance characteristics of the building blocks of the APD. A self-verification of the entire system can be performed by multiplying the output of the on-chip signal generator by itself and then reading the resultant digitized DC voltage. This operation does not involve the CUT and can be performed at all of the frequencies of interest. Moreover, this procedure does not represent an overhead in terms of time since the resultant values are a vector for , as described in (1). The effect of the spectral content of the test signal is now analyzed. Let , be the relative amplitude of the th harmonic

VALDES-GARCIA et al.: AN INTEGRATED FREQUENCY RESPONSE CHARACTERIZATION SYSTEM WITH A DIGITAL INTERFACE FOR ANALOG TESTING

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Fig. 2. Operation of phase and amplitude detector.

component with respect of the amplitude of the fundamental tone. In the pessimistic assumption that the CUT does not introduce any attenuation or phase shift to neither of these frequency components, the DC error voltage ( ) introduced by the harmonic distortion components to each of the voltages , , and is given by

(6) where THD is the total harmonic distortion of the signal generator. If THD is as high as 0.1 (10%), even in this pessimistic scenario the error voltage would be equivalent to only 0.01 (1%) of . This tolerance to harmonic components is an important advantage since it eliminates the need for a high-precision sinusoidal signal generator. III. BUILDING BLOCKS FOR ON-CHIP ANALOG TESTING A. Analog Multiplier for Amplitude and Phase Detection Fig. 3(a) presents a block diagram of the four-quadrant analog multiplier with cascaded LPF employed for the phase and amplitude detector shown in Fig. 2. The core of the four-quadrant multiplier (transistors M1 and M2) is based on the multiplier of [10, Fig. 7(c)]. In the one-quadrant cell shown in Fig. 3(a), the and and the output is the current inputs are the voltages IM. Transistor M1 operates in the triode region; the multiplication takes place between its gate-to-source and drain-to-source voltages. The result of this operation is the drain current of transistor M1, which is equivalent to the current at the drain of M2. Transistor M2 acts as source follower. Ideally, the voltage at the source of transistor M2 should be just a DC shifted version of . However, the drain the voltage signal applied to its gate current of transistors M1 is the result of the multiplication, and

its variations affect the operation of the source follower, introducing an undesired phase shift on the voltage signal applied to the drain of transistor M1. This effect significantly degrades the phase detection accuracy of the multiplier. To overcome this problem, the addition of transistor M3 to the original multiplier core is introduced. M3 provides additional DC current (IDC) to the source follower, improving its transconductance and reducing its sensitivity to the AC current variations. Simulation results show that this modification reduces the error in phase detection from more than 10 to less than 1 . The complete four-quadrant multiplier circuit schematic is presented in Fig. 3(b). The output currents from four branches are combined to realize the four-quadrant operation. The first pole of the LPF is implemented at the current output of the multiplier core with capacitor C1 and the active resistors formed by transistors M4. M5 operates as a DC source that provides most of the bias current consumed by the multiplier core; this prevents that unnecessary DC current is mirrored to the output stage. Transistors M6–M7 operate as a differential to single-ended converter. The second pole of the LPF is implemented by the capacitor C2 and the passive resistor R1. The DC operating point of VOUT can be set directly through VBO. B. Multiplexer-Buffer for Interface With Cut An important component of the proposed system is the interface between the CUT and the APD. As shown in Fig. 1, through a multiplexer, the frequency response at different stages of the CUT can be characterized. This is a relevant feature of the system since it allows to identify the location of a fault within the analog core under test, and this information is important for yield enhancement. The multiplexer should present a high input impedance (so that the performance of the CUT is not affected) and provide the appropriate DC bias voltages to the phase and amplitude detector. The proposed circuit to comply with these functions is depicted in Fig. 4. The differential pair with active load composed by transistors M8 and M9 form a buffer with

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Fig. 3. Analog multiplier optimized for magnitude and phase detection. (a) Conceptual description (b) Circuit schematic.

Fig. 4. Multiplexer-buffer schematic.

unity gain. The output of the buffers (differential voltages VA and VB) are connected to the corresponding inputs of the APD. The DC operating point of the output is set through the bias voltages VBA and VBB. The switches are implemented with nMOS transistors. The input capacitance of the multiplexer, as seen from the input of the switches in the on state, is approximately 50 fF.

C. Frequency Synthesizer and VCO The employed frequency synthesizer for the generation of the input signal to the CUT is a type-II phase-locked loop (PLL) with a 7-bit programmable counter, spanning a range of 128 MHz in steps of 1 MHz. The block diagram is shown in Fig. 5(a). One of the main advantages of employing a PLL


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Fig. 6. Multivibrator-based VCO schematic. Fig. 5. (a) Implemented PLL-based frequency synthesizer. (b) Alternate implementation.

in this application is that to generate the internal stimulus, only a relatively low-frequency signal ( MHz in this case) is required as a reference. In contrast, a sigma-delta based signal generator requires a clock that runs at a significantly higher speed than the generated signal [5]. In this PLL design, the loop filter is implemented with off-chip elements to reduce the silicon area. These passive components can be easily incorporated into the test board of the chip. Moreover, in an SoC implementation, the reference signal can be obtained from an internal clock. An alternate implementation is shown in Fig. 5(b), in this case the loop is closed externally. The ATE receives the output of the divider and sets the control voltage of the voltage-controlled oscillator (VCO). This approach uses the same number of pins (a 1-MHz digital signal and a DC voltage) but further reduces the amount of on-chip components and enables an independent verification of the loop operation. The tolerance of the proposed amplitude and phase measurement technique to the amplitude variations and harmonic distortion of the test signal allows the use of a simple on-chip oscillator. The proposed VCO is shown in Fig. 6; it employs only three pairs of transistors (M11–M13) and one capacitor (C1). It is based on a source-coupled multivibrator topology [11]. The control voltage VC is applied through a source follower (not shown for simplicity) to have a suitable voltage range (between 1.5 and 2 V) for the output of the charge pump. This oscillator shows an exponential frequency versus voltage characteristic, which results in a frequency tuning range of more than two decades. Simulation results with process corners show that the VCO can have a tuning range of at least 0.8 to 130 MHz. Moreover, from simulations it was also observed that, if discrete tuning is introduced by implementing C1 as a bank of two capacitors, the tuning range can be extended to 0.1 to 180 MHz. A differential, tunable first-order LPF is added to the VCO. The LPF is formed by transistors M14–M15 and capacitor C2. The VCO oscillation frequency and the LPF cutoff frequency are tuned simultaneously through VC to keep a THD of less than 10% over most of the frequency tuning range.

D. Algorithmic Analog-to-Digital Converter As discussed earlier, the output of the APD is a DC voltage hence, a low-speed ADC can be used. A DC-ADC can be used for various on-chip testing and calibration purposes such as monitoring the DC operating points at different nodes of an SoC [12]. A successive approximation architecture can attain a low area and power consumption and hence is suitable for these applications. Equation (7) describes the basic operation per cycle of a successive approximation ADC. (7) where is the analog input, is the analog equivalent for the estimated digital output, and denotes the comparison operation. The subtraction in (7) is done through the two inputs of a comparator, which usually requires offset compensation techniques. In the ADC architecture introduced in [13], the subtraction is done inherently in a resistor ladder, thus the non-inverting input of the comparator has a constant voltage. This facilitates the offset cancellation of the comparator, by proper bias at its input. resistors, In that reported architecture, comparators, output buffers are used to form the -bit ADC. and Based on the described concept of inherent subtraction [13], a compact algorithmic architecture is proposed here; the number of components is reduced to decrease its power consumption and improve its robustness. In this architecture for an -bit ADC, only one comparator, one resistor ladder with resistors, switches, and a simple digital controller are used. Fig. 7(a) shows the implemented 7-bit ADC. The control signals for the switches are shown in Fig. 7(b). These time-shifted pulses and the end of conversion (EOC) signal are generated by a 3-bit binary counter with a 3-to-8 decoder. Equation (8), shown at the bottom of the next page, represents the general operation of the proposed ADC using different control lines to generate the different bits in a recursive manner. is generated first by comparing the input The MSB signal with half the input dynamic range. Then, the second bit is resolved by using the information from , and so on

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Fig. 7. (a) Proposed ADC architecture. (b) Control signals.

until the LSB is detected. By changing the status of the control signals, the resistor ladder is reshaped to calculate the corresponding bit. Fig. 8(a) and (b) show the first and the second and , respectively. In this way, time intervals to calculate the digital output is taken serially and eight clock periods are needed for a complete 7-bit conversion process. The proposed ADC operates up to 100 kHz clock frequency corresponding to 12.5 kHz conversion rate. The employed comparator uses an input stage, a regenerative comparator, and an SR latch in a similar way as the comparator proposed in [14]. Large resistor values are used in the resistor ladder (150 k ) to make the effect of the switch on-resistance negligible, thus preserving accurate resistance ratios and better accuracy. By using the high resistivity n-well layer, these resistors can be implemented in an insignificant area. Due to its reduced number of components, this ADC architecture can make use of the existing circuitry in an IC compliant with the IEEE 1149.1 standard for a mixed-signal test bus [15]. In this standard, each test pin has an analog boundary module

(ABM) through which its DC voltage can be set, shorted to the supply, or compared with a threshold and latched as a logic value by the boundary scan test. The ABM consists of a comparator, switches and a set of storage cells (flip-flops) [15]. By incorporating simple programmability, these components can be used together with a resistor ladder to form this compact ADC for DC signals using only one ABM. This modification in the ABM leads to more accurate results in testing, where each voltage value is digitized ( -bit ADC) rather than compared with a single threshold (1-bit ADC). The presented ADC design is meant to show that the proposed system can have a complete implementation with fully digital interface in a compact area. Naturally, a more complex, highresolution ADC could be used instead if it is already available in the SoC or the ATE. IV. EXPERIMENTAL RESULTS The proposed system is implemented in standard TSMC CMOS 0.35- m technology and fabricated through the MOSIS

if where

otherwise and

(8)


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Fig. 8. ADC operation: (a) MSB detection; (b) second bit detection.

service. Two different fourth order OTA-C filters are included as CUTs: a bandpass filter (BPF) with a center frequency of 11 MHz and a low-pass filter (LPF) with a cutoff frequency of 20 MHz. These filters’ characteristics are common in the baseband section of communication systems. The chip microphotograph is shown in Fig. 9. The total area of the testing circuitry (frequency synthesizer, ADC and APD) is 0.3 mm . Table I presents an area overhead analysis for the FRCS with respect to reported analog systems [16]–[18], which are suitable CUT candidates. Note that this area comparison is a pessimistic estimation since it is made with respect to circuits that are fabricated in technologies with smaller minimum feature sizes. Sections IV-A–IV-E present the obtained experimental results. A. Amplitude and Phase Detector The performance of a standalone APD is evaluated using two phase-locked external signal generators for frequencies up to 120 MHz. The relative difference between the amplitude of two signals can be measured in a range of 10 to 450 mV (33 dB) with an error of less than 1 dB. That is, the 1-dB compression point of the detection characteristic is at an input amplitude of 450 mV. The relative phase between the two input signals is swept across 360 and the phase measurement performed with the APD is

Fig. 9. Chip microphotograph.

compared against the measurement with a digital oscilloscope. Fig. 10 shows the resultant phase error as a function of the phase difference at 50 and 80 MHz. In general, up to 120 MHz the phase difference can be measured with an error of less than 1 in 95% of the overall 360 range with a peak error of less than 5 .

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TABLE I AREA OVERHEAD ANALYSIS

Fig. 11. Tuning range of the VCO.

Fig. 10. Measured error performance of the phase detector as compared with an external measurement using a digital oscilloscope at (a) 50 MHz and (b) 80 MHz.

The complete APD with the input multiplexer occupies an area of 310 m 180 m and draws 3 mA from the 3.3-V supply. B. Frequency Synthesizer and VCO Figs. 11 and 12 present the experimental results for the VCO. The measured frequency tuning range is 0.5 to 140 MHz and the amplitude variations in the range of interest (1–128 MHz) are within 3.5 dB. Fig. 13 presents the harmonic distortion measurements for an output frequency of 15 MHz. Throughout the tuning range, the harmonic distortion components are always below 20 dBc. According to the analysis presented in Section II, this distortion does not affect the operation of the APD significantly. The frequency synthesizer covers a range from 1 to 128 MHz in steps of 1 MHz; the output spectrum in the locked state at 128 MHz is shown in Fig. 14. The reference spurs are below 36 dBc. The area of the entire synthesizer is

Fig. 12. Measured VCO amplitude over its tuning range.

380 m 390 m and the current consumption changes from 1.5 to 4 mA as the output frequency increases. C. Algorithmic Analog-to-Digital Converter For the test of the ADC, a 2-V input dynamic range is considered. Fig. 15 shows the measured peak integral nonlinearity (INL) and differential nonlinearity (DNL) versus input clock frequency. The ADC operates at a 100 kHz clock frequency (80 s conversion time) with a peak INL of 1.4 LSB and a peak DNL of 0.45 LSB. Fig. 16 shows an oscilloscope screen capture showing the end of conversion signal, the 10 kHz clock signal,


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Fig. 15. Measured peak INL and DNL of the ADC versus clock frequency. Fig. 13. Fundamental tone, and second and third harmonic components of the signal generator.

Fig. 16. ADC waveforms: EOC, CLK, and serial output data.

Fig. 14. PLL output spectrum in the locked state at 128 MHz.

and the serial output data. An average power of 200 W is consumed by the ADC and its area is 380 m 390 m. D. Frequency Response Characterization System Fig. 17 describes the experimental setup for the evaluation of the entire system in the test of the integrated CUTs. Each fourth order filter consists of two OTA-C biquads, and each biquad has two nodes of interest, namely bandpass (BP) node and low-pass (LP) node. In Fig. 17, the filter configuration corresponds to the 11-MHz BPF (CUT 1 in Fig. 9), in which the output of each biquad is the BP node. For the 20-MHz LPF (CUT2 in Fig. 9), the outputs are the LP nodes. A buffer is added at the output node of each biquad so that their frequency response can be evaluated with external equipment. The buffers are designed to show a constant frequency response up to 200 MHz while driving a 50- differential load through an off-chip balun.

Fig. 17. Experimental setup for the evaluation of the proposed system.

The results of the operation of the entire FRCS in the magnitude response characterization of the 11-MHz BPF at its two BP outputs are shown in Fig. 18. These results are compared against the voltage gain characterization performed with a commercial vector network analyzer. In this measurement, the dynamic range of the test system is limited by the resolution of the ADC. With 7 bits, the digitized DC voltages can take values

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Fig. 19. Phase response test of the 11-MHz BPF. (a) Results for the first biquad (second-order filter). (b) Results for the complete fourth-order filter. Fig. 18. Magnitude response test of the 11-MHz BPF. (a) Results for the first biquad (second-order filter). (b) Results for the complete fourth-order filter.

TABLE II PERFORMANCE SUMMARY

of 1–128 and, as a result, the highest measurable CUT attenuation (B/A ratio as described by (5) is about 21 dB). The phase response of the filter as measured by the FRCS is shown in Fig. 19. The corresponding results for the characterization of the 20-MHz LPF are presented in Figs. 20 and 21. In this case, the DC output of the APD is measured through a data acquisition card with an accuracy of 10 bit. As it can be observed, the APD is able to track the frequency response of the filter and

perform phase measurements in a dynamic range of 30 dB up to 130 MHz. On average, in the test of both CUTs, the magnitude response measured by the off-chip equipment is about 2 dB below the estimation of the FRCS. This discrepancy is good agreement with the simulation results from the cascaded insertion loss of the output buffers and baluns. Table II presents the performance summary of the proposed test system. It is worth mentioning that even though some target CUT may have specifications in a dynamic range greater than 30 dB, the significant amount of information provided by the system (phase and magnitude responses at different nodes and frequencies) will suffice in most cases to establish correlations to faulty behavior and guarantee a high fault coverage through an appropriate test optimization methodology. E. Summary of Current On-Chip Test Solutions In order to place the achieved results into perspective, Table III presents a summary of the on-chip testing techniques that have been so far (up to the author’s knowledge) demonstrated experimentally with CMOS integrated prototypes. It is important to emphasize that Table III is presented only with the


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Fig. 21. Phase response test of the 20-MHz LPF. (a) Results for the first biquad (second-order filter). (b) Results for the complete fourth-order filter. Fig. 20. Magnitude response test of the 20-MHz LPF. (a) Results for the first biquad (second-order filter). (b) Results for the complete fourth-order filter.

purpose of providing an overview of the current state-of-the-art; the built-in test systems discussed have diverse characteristics and cannot be compared directly. The mixed-signal test core presented in [5] is versatile, mostly digital and has the advantage of capturing signals in the gigahertz range through subsampling. Nevertheless, due to the use of oversampling techniques for its signal generator, frequency response measurements with this system are limited to only a fraction of the employed clock frequency (20 MHz). It is worth mentioning that the required analog filter for the signal generator is not included in the reported area and that supplemental fast Fourier transform (FFT) processing is required to perform the frequency response characterization. Oscillation-based test (OBT) is a well-documented strategy in the literature [2]. The CUT is reconfigured in an oscillation mode and its performance is estimated from the characteristics of the obtained signal; [6] presents a technique to evaluate the characteristics of the output

waveform from the CUT on-chip. The on-chip spectrum analyzer presented in [7] has the advantages of having a digital control and the capability of performing harmonic distortion measurements in addition to frequency response characterizations. The use of switched capacitor techniques improve the robustness of the system but limit its potential application to the range of a few megahertz. The main drawbacks of the proposed system as a test core are that it has an application space limited to continuous-time circuits, and a limited portability since some of the main analog building such as the multiplier and the VCO cannot be transferred directly from one technology to another. V. CONCLUSION A compact integrated system for analog testing has been developed and evaluated experimentally. The magnitude and phase responses over frequency of an analog circuit or subsystem can be evaluated without the use of analog instrumentation. The simplicity and low bandwidth of its digital interface make the proposed test core suitable for wafer-level

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TABLE III CURRENT STATE-OF-THE-ART IN INTEGRATED SOLUTIONS FOR ANALOG TEST

test and compatible with the IEEE 1149.4 test standard. With respect to existent on-chip test solutions implemented in similar technologies, this system presents a small area, a high frequency range in terms of frequency response characterization, and the advantage of presenting a low processing overhead. From an area overhead analysis, it is estimated that this system requires less than 10% of extra area for typical analog signal processing subsystems such as an ADSL driver or the baseband section of a transceiver, which are suitable test candidates. The proposed system is an effective and area-efficient solution for low-cost testing of analog circuits. ACKNOWLEDGMENT The authors thank the MOSIS service for the IC fabrication and Dr. A. Y. Valero-Lopez for his assistance in the design and layout of the PLL. REFERENCES [1] The International Technology Roadmap for Semiconductors 2003. [Online]. Available: http://public.itrs.net/Files/2003ITRS/ Home2003.htm [2] L. S. Milor, “A tutorial introduction to research on analog and mixed-signal circuit testing,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 10, pp. 1389–1047, Oct. 1998. [3] J. L. Huertas, Ed., Test and Design-for-Testability in Mixed-Signal Integrated Circuits, 1st ed. Norwell, MA: Kluwer, 2004. [4] S. S. Akbay, A. Halder, A. Chatterjee, and D. Keezer, “Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs,” IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 352–363, May 2004. [5] M. M. Hafed, N. Abaskharoun, and G. W. Roberts, “A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 499–514, Apr. 2002. [6] D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda, and J. L. Huertas, “On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits,” Analog Integr. Circuits Signal Process., vol. 33, pp. 201–211, Nov. 2002. [7] M. G. Mendez-Rivera, A. Valdes-Garcia, J. Silva-Martinez, and E. Sánchez-Sinencio, “An on-chip spectrum analyzer for analog built-in testing,” J. Electron. Testing: Theory Appl., vol. 21, no. 3, pp. 205–219, Jun. 2005. [8] Q. Yin, W. R. Eisenstadt, R. M. Fox, and T. Zhang, “A translinear RMS detector for embedded test of RF ICs,” IEEE Trans. Instrum. Meas., vol. 54, no. 5, pp. 1708–1714, Oct. 2005.

[9] A. Valdes-Garcia, J. Silva-Martinez, and E. Sánchez-Sinencio, “An on-chip transfer function characterization system for analog built-in testing,” in Proc. IEEE VLSI Test Symp., May 2004, pp. 261–266. [10] G. Han and E. Sánchez-Sinencio, “CMOS transconductance multipliers: A tutorial,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 12, pp. 1550–1563, Dec. 1998. [11] I. G. Finvers and I. M. Filanovsky, “Analysis of source-coupled CMOS multivibrator,” IEEE Trans. Circuits Syst., vol. 35, no. 9, pp. 1182–1185, Sep. 1988. [12] P. Confalonleri, M. Zarnprogno, F. Girardi, G. Nicollini, and A. Nagari, “A 2.7 mW 1 MSps 10 b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges,” in Proc. IEEE 30th Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 255–258. [13] L. Chi-Sheng and L. Bin-Da, “A new successive approximation architecture for low-power low-cost CMOS A/D converter,” IEEE J. SolidState Circuits, vol. 38, no. 1, pp. 54–62, Jan. 2003. [14] G. M. Yin, F. O. Eynde, and W. Sansen, “A high-speed CMOS comparator with 8-b resolution,” IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208–211, Feb. 1992. [15] IEEE Standard for a Mixed-Signal Test Bus, IEEE std. 1149.4-1999, 1999. [16] P. Orsatti, F. Piazza, and Q. Huang, “A 71-MHz CMOS IF-baseband strip for GSM,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 104–108, Jan. 2000. [17] B.-S. Song, T. Cho, D. Kang, and S. Dow, “A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicer,” in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 431–434. [18] A. Bicakci, C.-S. Kim, S.-S. Lee, and C. Conroy, “A 700 mW CMOS line driver for ADSL central office applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2003, pp. 414–503. Alberto Valdes-Garcia (S’00–M’06) received the B.S. degree (Highest Honors) in electronic systems engineering from the Monterrey Institute of Technology (ITESM), Campus Toluca, México, in 1999, and the Ph.D. degree in electrical engineering from Texas A&M University, College Station, in 2006. In 2000, he was a Design Engineer with Motorola, Broadband Communications Sector. From 2001 to 2004, he was a Semiconductor Research Corporation (SRC) Research Assistant at the Analog and MixedSignal Center, Texas A&M University, working on the development of analog and RF built-in testing techniques. In the summer of 2002, he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004, he was with the Mixed-Signal Communications IC Design Group at IBM Research, where worked on the design and analysis of


millimeter-wave SiGe power amplifiers. Since January 2006, he has been a Research Staff Member with the Wireless System Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY. His present research work is on integrated millimeter-wave communication systems. From 2000 to 2005, Dr. Valdes-Garcia was the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He is the winner of the 2005 Best Doctoral Thesis Award presented by the IEEE Test Technology Technical Council (TTTC).

Faisal Abdel-Latif Hussien (S’03) received the B.Sc. and M.Sc. degrees in electronics and electrical communications engineering from Cairo University, Cairo, Egypt, in 2000 and 2003, respectively. He has been working toward the Ph.D. degree as a Research Assistant in the Analog and Mixed-Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, since January 2003. From July 2000 to January 2003, he was with the Electronics and Electrical Communications Engineering Department at Cairo University as a Teaching Assistant. He held an internship at Texas Instruments Incorporated, Dallas, TX, from September 2005 to December 2005. His current research interests include mixed-signal circuits, receiver RF front-end, and communication system architectures.

José Silva-Martínez (SM’98) received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica, Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven, Belgium, in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autónoma de Puebla, where he remained until 1993. He pioneered the graduate program in opto-electronics in 1992. In 1993, he rejoined the Electronics Department, INAOE, and from May 1995 to December 1998 was the Head of the Electronics Department. He was a co-founder of the Ph.D. program on electronics in 1993. He is currently with the Analog and Mixed Signal Center, Department of Electrical and Computer Engineering, Texas A&M University, College Station, where he is an Associate Professor. He is a co-author of 50 journal papers and over 115 conference papers. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical applications. Dr. Silva-Martínez has served as IEEE Circuits and Systems Society (CAS) Vice President Region 9 (1997–1998) and as Associate Editor for IEEE

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TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II from 1997 to 1998 and 2002 to 2003, and for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I from 2004 to 2005. He was the main organizer of the 1998 and 1999 International IEEE CAS Tour in Region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications from 1997 to 1999, and was Conference Chairman of the 2006 IASTED International Conference on Circuits, Signals and Systems. He has been a member of the IEEE CAS Analog Signal Technical Committee since 2001. He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University, and recipient of the 2005 Outstanding Professor Award by the Department of Electrical and Computer Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.

Edgar Sánchez-Sinencio (F’92) was born in México City, México. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of México, México City, the M.S.E.E. degree from Stanford University, Stanford, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1966, 1970, and 1973, respectively. In 1974, he held an industrial post-doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983, he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, México. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983–1984. He is currently the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He is a co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold, 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press, 1999). His present interests are in the area of RF communication circuits and analog and mixed-mode circuit design. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (1985–1987), and an Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS. He is the former Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He is a former IEEE Circuits and Systems Society (CAS) Vice President–Publications, and was the IEEE CAS Representative to the Solid-State Circuits Society (2000–2002). He was a member of the IEEE Solid-State Circuits Society Fellow Award Committee from 2002 to 2004, and is currently a member of the IEEE CAS Society Board of Governors. In November 1995, he was awarded a Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, México, the first honorary degree awarded for Microelectronic Circuit Design contributions. He is a co-recipient of the 1995 Guillemin–Cauer award for his work on cellular networks. He was also a co-recipient of the 1997 Darlington Award for his work on high-frequency filters. He received the Circuits and Systems Society Golden Jubilee Medal in 1999.