Abstract. In rhis paper: we propose a Soft lP Generator which can add or remove PCM Codec modules arbitrarily. It can be applied ro PCM Codec IP designs ...
An Optimal PCM Codec Soft IP Generator and Its Application Gwo-Yang Wu, Liang-Bi Chen, Yuan-Long Jeang, and Gwo-Jia Jong Graduate Institute ofElectronic & Information Engineering National Kaohsiung Universify ofapplied Sciences Kaohsiung, Taiwan, R.O.C. E-mail: nico@,bcp.url.com.tw
Abstract In rhis paper: we propose a Soft lP Generator which can add or remove PCM Codec modules arbitrarily. It can be applied ro PCM Codec IP designs rhat need to change their related modules corresponding to different working environments. It also can help us to easily manage our Soft IP modules, produce optimized modules, and remove unnecessary modules, in order ro reduce the intplenienration cosr. I n addition, users can implement their own Verilog HDL code o f P C M Codec by following our predefined interface specification, and integrate it with our Optimal PCM C o d a module to produce users' O W optimized system.
Keywords Soft IP Generator, Modeling, Verilog HDL, PCM Codec
1. Introduction For IC design engineers, shorten development time is extremely important in terms oftime to market and maximizing profit. How to shotten IC development time? Good CAD tools play an important role. There are many VLSl CAD tools on the market. No tool fits current design. Therefore, customizing a CAD tool becomes an important lesson. Customizing a CAD tool not only requires a software engineering background. but also requires VLSl related knowledge. To my best knowledge, there is no papers about 1P Generator of PCM codec yet. Therefore, in this paper, we propose a PCM codec IP Generator and introduce its features, implementations, algorithms, sample, and the results after synthesis, in details. We hope this design can help PCM codec design colleagues to quickly and precisely generate commonly used encodingidecoding IP, and also quickly integrate their own encodingldecoding methods in order to shorten the time to market.
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provided PCM modules. When users remove the unwanted codec modules, their related internal modules will be removed automatically, in order to save the implementation cost. Users can use PN code test vectors to efficiently test the fixed data length signal. We also provide an IETS that can be dynamically switched depending on the transmission environments.
1.2 Functions This software provides several common PCM encoding methods [1,2]: (a)RZ, (b)Manchester, (c)AMI, (d)NFZ(L), (e)NRZ(M), (f)NRZ(S), (g)Miller. Users can quickly generate needed PCM codec IP according to their demands. The main features are : -Automatically generates a single PCM encoding method IP. -Automatically generates a single PCM decoding method IP. - Automatically generates several PCM codec IP and plus an optimized IETS. -Automatically generates a PN code IP for PCM codec test.
2. Description of an optimal PCM Codec 2.1 Functional Description and Architecture Our Optimal PCM Codec includes several PCM encoderidecoder, and Optimal IETS PCM selection function. The IETS function will be able to select a PCM encoding method with the lowest error rate to perform transmittion. In addition, We integrate the IP Generator with IP's design parameter to achieve better demand. IP's design parameters table is shown in Table 1: Design
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parameters
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Selection of PCM enc,oder type, one or
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1.1 Features In this paper, we propose a Soft IP Generator of Verilog HDL module, which can be applied in various working environments. It can help us to manage our Soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost and to produce users' own optimized system. On the hardware module side, we provide two hardware functionality modules. One is the Optimal PCM codec that can automatically switched depending on the transmission environments. We call it IETS(1ntelligent Encoder Type Selector). It can automatically select the PCM encoding method that has the lowest error rate to transmit. The other is PN code test Vector. Its main function is to efficiently test the transmission of fixed data length signals. Therefore, using IP Generator can automatically generate codecs, IETS, and test vectors and reduce design time. Therefore, this paper proposes the following features: - Users can easily add or remove the provided PCM modules. Users can design their own PCM modules by following the standard interface and easily integrate them with the
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working type. Use IP generator's default CMD ASO
Used to select the optimal codec. Record the relationships ofvaries PCM types.
2.1.1 Encoder Before data being encoded to PCM code, because base band PCM digital signal's transmission distance is not long, it has to be modulated in order to transmit. Before PCM signals sent to a modulator, it should be converied to different signal type. However, how to choose these different binary digital types depends on modulaion method, demodulation method, bandwidth limit, and receiver types. Therefore, we provide IETS to select an optimal PCM encoding method. The PCM coding models are described as follows [1,2,5]:
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Rz: the signal level representing bit value 1 lasts for the first half of the bit interval, after which the signal r e h " to the reference level (0) for the remaining half of the bit interval. A 0 is indicated by no change, with the signal remaining at the reference level. - Manchester: the signal bit value 1 is represented by a positive pulse followed by a negative pulse, with both pulses being of equal amplitude and half-symbol width. For bit value 0, the polarities of these two pulses are reversed. - AMI: uses three amplitude levels. Positive and negative pulses of equal amplitude are used altemately for bit value 1, and no pulse is always used for bit value 0. NRZ(L): it is the most common mode of NRZ transmission, duo to the simplicity of the transmitter and receiver circuitry. NRZ(M): a level change is used to indicate a mark(that is, a 1) and no level change for a space (that i s , a 0). NRZ(S): it is similar except that the level changes is used to indicate a space or zero. Miller: the signal bit value 1 represents transition in the middle of bit. The signal bit value 0 represents no transition if followed by a bit value I, transition at end of bit if followed by a bit value 0.
3. Implementation 3.1 The flow chart In this paper, we choose C language to implement an Optimal PCM IP Generator, and use Verilog HDL to describe PCM's IP. We not only produce basic PCM encoding methods, but also provide an interface for users to add extra codec circuits. Furthermore, we pack up the users' own codes with the IETS module in order to tcst and figure out the best codec module. An Optimal PCM codec IP Generator's system flow chart is shown in Figure 2.
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2, .2 PCM Decoder Since, the input signal an the transmission channel end is a sequential signal, we design a multiplexer and demultiplexer pair lo select an encoding method with related signals as decoder's input signal and decode it. RX end received the digital signal from TX end.
2.1.3 IETS As shown in Figure 1, IETS chooses an encoder, which can produce higher correct rate with real-time selection under current environment. It includes an Error Detector. an Error Counter, an Error Comparator, and a Feedback Select Controller: - Error Detector: to detect the position of error bit according to the encoding method. - Error Counter: to concretize and digitize the system performance. It is very important for raising the confidence of communication systems. Through an error counter, we can clearly record the number of occurrences of error for each PCM encoding method. - Error comparator: by comparing error rate, we can understand which encoding method provided highest correctne~~ rate and is the optimal encoding method under current environment. - Feedback Select Controller: according to the result of Error Comparator, the Feedback Selection Controller can be used to select a PCM encoding method of transmission.
Figure 2. The flaw chart ofthe Optimal PCM codec IP Generator
3.2 Algorithm We first briefly describe the functions of the O & m l PCM codec IP Generator, and discuss its algorithm later -Selecting PCM function module. -Selecting PCM encoding or decoding mode. -Multiple selections of PCM encodingldecading including what users have defined. -Generate PCM module. The Algorithm of An Optimal PCM codec IP Generator is shown in Figure 3.
4. Experimental results 4.1 Test output Our Optimal PCM codec IP Generator generates synthesisable Vedog HDL code. It includes (a)RZ, (b)Manchester, (c)AMI, (d)NRZ(L), (e)NRZ(M), (f)NRZ(S),(g)Miller, encoding methods, IETS, PN code test file, and necessaty hardware structures. Users only need to select their desire encodingtdecading method, and the IP Generator will automatically partition the Verilog codes according to users' need and save them to files.
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4.2 Result Analysis We first use our Optimal PCM codec IP Generator to generate IP core, and then synthesize and implement it. Figure 4 and Figure 5 show the wave that produced from logic analyzer. In lhe figure, the CLOCK is FPGA demo board's working clock speed, the PCNODE is the generated vimal binary sequential signal, while RZ, Manchester, A M I 4 AMIA, NU&), NRZ(S), NRZ(M), MILLER are the binary sequential signal
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Figure 1 The stmcture ofthe IETS
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corresponding to each PCM encoding method. The RX is the receiving end. The S2-SO are the current selected encoding method which are used to inform receiving end to turn to conesponding PCM decoding mode. The resulting Area, Power, ite level design produced by Synopsys Design Analyzer is own in TableZ.
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Algorithm: An Optimal PCM Codec IP Generator Input Several options of PCM codec methods Output: An Optimal PCM codec IP begin Check user’s selection of function names, and record them; for (n=O;n
