An Ultra-Low-Power Monitoring System for. Inductively Coupled Biomedical Implants. Kamyar Keikhosravy, Pouya Kamalinejad, Shahriar Mirabbasi, Kenichi ...
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An Ultra-Low-Power Monitoring System for Inductively Coupled Biomedical Implants Kamyar Keikhosravy, Pouya Kamalinejad, Shahriar Mirabbasi, Kenichi Takahata, and Victor C.M. Leung Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, V6T 1Z4 E-mail:{keikhosr, pkamali, shahriar, takahata, vleung}@ece.ubc.ca
Abstract—In this paper, an ultra-low-power system for wireless monitoring of inductively coupled biomedical implants is presented. The system is fully integrated and composed of custom rectifier, alignment and monitoring circuits with enhanced performance. The proposed system is described in the context of a smart-stent system that monitors the re-narrowing of blood vessels at the smart-stent site. The building blocks of the system are designed and simulated in a 0.13-µm CMOS technology. Simulation results for the monitoring system show that the proposed rectifier provides 53% power conversion efficiency (PCE) for 10.36 dBm input power (in the alignment mode) and 62% PCE for 4.06 dBm input power (in the monitoring mode). The alignment unit is capable of operating by drawing a 12 µA from a supply voltage as low as 0.6 V and the monitoring circuit consumes as low as 176 µW.
I. I NTRODUCTION The rapid growth in sensor technology combined with ultra-low-power operation of emerging deep-submicron CMOS processes have significantly facilitated the development of biomedical implants and biotelemetry devices. The sensory data includes a variety of parameters from temperature to pressure to fluid flow. In many applications, the use of battery-powered implants is impractical due to the size limitation and/or required longevity of operation. Therefore, in such cases the power is wirelessly transferred to the implant site for the operation of the implant and/or recharging of a small local battery. For short distance power transmission (e.g., a few cm), inductively coupled links are commonly used. However, inductive coupling requires a proper alignment of the primary (external) and the secondary (internal) coils. In other words, if the primary and secondary inductors are not aligned the induced power on the secondary coil may drastically drop resulting in failure of the internal rectifier circuit and thus the overall implant. The adverse effects of insufficient power delivery in wireless links for implantable devices have been reported in [1]. Recent studies indicate that there is a direct relation between the frequency of radio-frequency (RF) incident waves and the power efficiency of the transmission link [2]. As shown in [2], the power transfer efficiency of an inductive link can improve This research is funded in part by the Natural Sciences and Engineering Research Council of Canada (NSERC), a Collaborative Health Research Project (CHRP) grant, and the Institute for Computing, Information and Cognitive Systems (ICICS) at UBC. CAD support and access to technology is facilitated by CMC Microsystems.
978-1-4673-5762-3/13/$31.00 ©2013 IEEE
Figure 1.
Block diagram of the proposed monitoring system
by almost 30 dB if the power is transmitted in the GHz range (instead of MHz range). In this work, the main focus is on the design of a highly efficient ultra-low-power transponder integrated circuit (IC) for tele-monitoring in implantable devices. The proposed architecture offers techniques to significantly reduce the power consumption of the overall system including a rectifier that provides two optimum power efficiency points for two different operation modes of the system, namely, alignment mode and monitoring mode. An example circuit is designed and simulated and its performance is compared with state-of-the-art designs. The organization of the paper is as follows. Section II describes the proposed transponder IC. Section III introduces the proposed rectifier circuit and Section IV provides the simulation results of an example design. Finally, Section V concludes the paper. II. T HE P ROPOSED T ELE - MONITORING A RCHITECTURE We present the proposed system in the context of a specific application, namely, monitoring blood flow through a smart-stent (a stent with embedded sensors) for screening of in-stent restenosis (re-narrowing of the blood vessels at the stent site) [2], [3]. Delivering power to the internal transponder IC is a challenging task due to the lossy transmission medium (thick layers of tissue between the smart stent and the external reader) and the limit on maximum power density exposure to the body as governed by the Federal Communications Commission (FCC) regulations. In the case of smart stent, these limitations results in a very limited induced power at the smart-stent site, i.e., on the order of a few tens of µW. Inductive power transfer is a commonly used approach for delivering power to implantable devices. However, as the size
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RF+
VIN M8
M3
M4
M11
M9
Mnt
M13
M7
M6
align
Vref
outDC,i-1
aVIN
mon
Vbias
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Vboostn Vboostp Md
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Mt Vboostn Vboostp
Smon
M1
Vbias
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Mpd Cin
Vbias,p
Cdec Md
(b) outDC,i
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Quasi-Floating Gate structure
Cin
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Rlarge Vbias,n-i Vbias,p-i
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Dynamic Biasing Circuit
Figure 2.
Schematic diagram of the dynamic biasing and decision circuits. VDDalign
Lmain
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CSensor
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Figure 4. Proposed Tunable Differential Converter (a) Schematic diagram, (b) Quasi-Floating Gate Biasing architecture, (c) Bias Generation Network
VDDmon
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Alignment Transmitter
Figure 3. (right).
(a)
Decision Circuit
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Monitoring Transmitter
The schematic of the alignment (left) and monitoring transmitter
of secondary coil is typically small, proper alignment between the primary and secondary is of paramount importance to assure transmission of sufficient power. In the case of smart stent the dimensions of the receive coil, namely, the stent itself, is about 5 mm in diameter and 19 mm in length. Recent studies reveal that there is an optimum frequency for which the highest transmission efficiency can be obtained [2], [4]. Electromagnetic simulations performed on the smart stent shows that the optimum frequency for power transmission is about 2 GHz. The above-mentioned challenges (tight power budget, alignment issue and optimal frequency) calls for a custom integrated transceiver circuitry. Fig. 1 depicts the block diagram of the proposed transceiver unit designed specifically for smart stents. Unique to this design is the alignment unit which provides the possibility of monitoring the received power level by the receiver coil (smart stent, in this case). As shown in Fig. 2, the decision circuit performs power level detection by comparing the generated local reference voltage (Vref ) and a portion of the rectifier output (aVIN ) and enabling/disabling the low-power alignment transmitter. The schematic diagram of the alignment and the monitoring transmitters are presented in Fig. 3. To decrease the power consumption of the alignment unit the value of the capacitance in the LC tank has to be minimized. The LC tank capacitance in the alignment transmitter consists of only parasitic capacitances, denoted by Cpar in Fig. 3. Furthermore, any change of the bias point of the alignment transmitter (as a result of variation of the output voltage of the rectifier) changes Cpar accordingly which in turn varies the alignment transmitter frequency.
At the start-up, if the received power (induced voltage) is insufficient for the proper operation of the system, the decision circuit switches off the main transmitter (monitoring transmitter) and switches on the low-power alignment transmitter which in turns notifies the reader of improper alignment. Note that oscillation frequency (and amplitude level) can be used as a measure of alignment (refer to Fig. 1). Switching off the main transmitter at the start up reduces the current load and facilitates the voltage generation at the output of the rectifier. By further adjusting the relative placement of primary coil (external reader) with respect to the secondary coil (e.g., "smart-stent" in our case), the rectified voltage level starts to build up. After achieving the required power threshold for proper operation of the system, the decision circuit switches off the alignment transmitter and turns on the monitoring transmitter through the switch Smon in Fig. 1. At the start-up, when the rectified voltage is very low, the dynamic biasing circuit (DBC) sets the tail current of the alignment transmitter at the minimum operating level to guarantee that it can operate and send a signal to the reader. III. A N E FFICIENT RF- TO -DC C ONVERTER Power-conversion efficiency (PCE) of a rectifier plays a key role in the operation of the power harvesting block and directly determines the detection range of the whole monitoring system. PCE of rectifiers is generally optimized based on the application and load requirements. In standard CMOS technology, differential drive rectifiers are commonly used in ultra-high-frequency (UHF) applications as they provide a simultaneous reduction in forward voltage drop and reverse leakage current [5]. In a differential rectifier, for a fixed load requirement and frequency of operation, design variables range from transistor sizing, capacitor values, number of stages, and input matching network [6]. Extensive studies on PCE optimization techniques are available in the literature. However, design strategies built upon these techniques mainly target a fixed load condition for which they guarantee an optimum PCE. It should be noted that PCE is a strong function of rectifier input power/voltage and drops rapidly if the input power deviates from the optimal point. Therefore, in an inductively coupled link, if the input power/voltage changes as a result of misalignment of the primary and the secondary coils or increased distance between the coils, the rectifier
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fails to provide sufficient power for proper operation of the succeeding circuitry. As the core of the power harvesting unit in the proposed monitoring system, a three-stage rectifier is designed and optimized to drive the transceiver in monitoring mode, i.e., when sufficient power is available at the rectifier input. However, for a given matching network, if the input power level drops due to misalignment, input voltage level will drop accordingly. For small input voltage levels comparable to the threshold voltage of charge-transfer transistors, PCE drops significantly and the rectifier fails to provide sufficient power to drive alignment circuitry. Therefore, a mechanism is required to maintain a high efficiency when the input power drops due to misalignment. In this section, a gate biasing technique based on quasi floating gate transistors is presented [7]. The proposed biasing scheme improves PCE when the input power/voltage of the rectifier is low due to misalignment, i.e., in alignment mode. As shown in Fig. 4.a, in alignment mode, floating voltage sources VboostP and VboostN provide a gate-drive boost to enhance the forward charge transfer of associated transistors. In other words, the threshold voltage of charge transfer transistors are reduced by Vboost,p,n , i.e., Vboost,p and Vthn,boosted = Vtho Vthp,boosted = Vtho Vboost,n . In normal operation (i.e., monitoring mode), the floating voltage sources are virtually shorted and rectifier keeps operating in an optimized fashion. Quasi floating gate structure is used to implement the floating voltage sources as shown in Fig. 4.(b). The intermediate voltage Md is connected to the gate of the PMOS transistor Mpt through the DC decoupling capacitor Cdec and the appropriate DC voltage, Vbias,p is connected to its gate through a very large resistor Rlarge . Rlarge is implemented by the leakage resistance of the reverse-biased pn junction of a PMOS in cut-off. The large resistor sets the DC voltage level of the gate of Mpt to Vbias,p while high-pass filtering the ac component of Md with a cut-off frequency of 1/(2⇡Rlarge Cdec ) [7]. It therefore, performs as a floating voltage source shifting the DC level of input Md to Vbias,p . It should be noted that with reference to Fig. 4.(a), Vbias,p has to be set equal to the difference of the dc level of intermediate voltage Vmd and the required boosting voltage Vboost,p , i.e., Vbias,p = VM d,dc Vboost,p . The same scenario holds for NMOS transistors. Note that to provide a positive gate-drive boost, Vbias,p < VM,dc and Vbias,n > V M,dc [8]. To set the rectifier back to normal operation in the monitoring mode (virtually shorting the boosting floating voltage source), Salign turns off which leaves the gate of Mpt floating and resets the dc component of Mpt ’s gate voltage equal to the dc value of the intermediate voltage VM through the capacitive divider formed by Cdec and Cg (the gate capacitance of Mpt ). Bias voltages (Vbiasp,n ) for each stage are generated from the intermediate and output voltage of each stage. More specifically, as shown in Fig. 4.(c), to meet the load requirements while in alignment mode (i.e., IL =12 µA at VL =610 mV ) the following bias voltages are applied: Vbias,n1 = Vout1,dc , Vbiasp1 = VM d1,dc /2, Vbias,n2 = Vout2,dc , Vbias,p2 = VM d2,dc /2, Vbias,n3 = Vout,dc and Vbias,p3 = VM d3,dc /2. It should be noted that in order for the bias generation circuitry not to load the rectifier, outputs and
Figure 5. Layout of the proposed tele-monitoring system including: 1. Alignment transmitter, 2. Tunable differential rectifier 3. Decision circuit and dynamic biasing circuit, and 4. Monitoring transmitter.
intermediate voltages are connected to the gate of rectifier’s transistors through large resistors. It is worth mentioning that in order to maintain a high efficiency in both alignment and monitoring modes, the effect of decoupling capacitor Cdec has to be carefully taken into account in the optimization process. Placing Cdec between the intermediate voltage of each branch and the gate terminals of transistors in the other branch (Fig. 4.(b)) slightly attenuates the ac component of the intermediate voltage VM at the gate of the transistors due to the capacitive divider formed between Cdec and Cg , i.e., Vg,ac = VM,ac · (Cdec /(Cdec + Cg )) where Cg is the gate capacitance of the associated transistor. Note that ideally Cdec has to be much larger than Cg . However, this choice of sizing, apart from layout area considerations, directly increases the time constant of the biasing circuit, i.e., time required by the gate of transistors to fully settle to the appropriate dc voltage (Vbias,pi,ni ). Although the transition period does not directly influence the performance of rectifier in terms of efficiency, it has to be kept as short as possible. The time constant of the biasing circuit is defined by T = 2⇡ · Rlarge · Cg,tot where Cg,tot is the total capacitance connected to the gate of charge transfer transistors. The proposed technique provides two optimum PCE points which in turn enables the proper operation of the monitoring system in the monitoring and alignment modes. IV. S IMULATION R ESULTS The proposed architecture is designed and laid out in a 0.13 µm CMOS technology (Fig .5). The overall system occupies an active area of 1100 µm ⇥ 440 µm. According to post-layout simulations results, the alignment transmitter starts to operate with a supply voltage of 610 mV and the tail current of 12 µA. By gradual increase of the rectified supply voltage as a results of improved alignment, the tail current of the alignment transmitter will be increased by the DBC block. When the rectified supply voltage reaches the pre-defined 0.8 V (minimum operation threshold of the main system), the DBC block has already increased the tail current of alignment transmitter to 180 µA which mimics the minimum operating current floor of the monitoring transmitter. Further increase of supply voltage results in the decision circuit to turn off the
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Table I P ERFORMANCE COMPARISON BETWEEN TRANSPONDER IC DESIGNED IN
1.8
THIS WORK AND SIMILAR REPORTED ARCHITECTURES
Aligment Signal
1.6
Monitoring Signal
Power
Output of Rectifier
1.4
Area (mm⇥mm)
Monitoring ON switch Bias from DBC
[1] [9] [10] This work
Voltage (V)
1.2 1
1.78 mW 340 µW 300 µW 176 µW
3⇥6 10 2.2 ⇥ 2.2 1.1⇥0.44
Operating depth (mm) 20-30
