Anomalous Staircase CV Characteristics of InGaSb-on-Insulator FET

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014

Anomalous Staircase CV Characteristics of InGaSb-on-Insulator FET Md. Nur Kutubul Alam, Muhammad Shaffatul Islam, Md. Golam Kibria, and Md. Rafiqul Islam

Abstract— Quasi-static capacitance voltage (CV) characteristics of In1−x Ga x Sb-on-insulator field-effect transistor (FET) are investigated using 1-D coupled Schrödinger–Poisson equations. Here, we report for the first time the staircase trend in the CV characteristics of such ultrathin-body FET. This observation is well correlated with the gate-bias-dependent electron concentration in different subbands. It is revealed that the staircase trend tends to disappear as the channel thickness increases above 15 nm. While the channel thickness and doping concentrationdependent shifts in CV curves are found to be significant, the composition-dependent shift is almost negligible. Index Terms— Capacitance voltage (CV) characteristics, field-effect transistor (FET), InGaSb, self-consistent analysis, staircase, ultrathin body.

I. I NTRODUCTION

O

VER the last four decades, the gate-length of the silicon (Si) MOSFETs has reduced from 10 to 22 nm, and it is now approaching its physical limit [1]. Such miniaturization suffers from various adverse effects including short-channel effects, parasitic capacitance, leakage current, transistor isolation, and so on. However, these effects have been effectively suppressed using silicon-on-insulator (SOI) structure [2]. Additionally, replacement of Si from the channel of SOI with III–V materials would further ameliorate the performance owing to their excellent transport properties [3]. This would allow reduction in operating voltage without compromising the operating speed. The new structure is termed as XOI to represent compound semiconductor-on-insulator, and was first experimentally demonstrated in [4]. Although XOI promises to offer better device performance than SOI, several critical challenges need to be addressed. For better control and high ION /IOFF ratio, the channel thickness needs to be reduced significantly. However, with continuous reduction in channel thickness, the interface charge properties start to dominate the device performance. In fact, interface traps close to or beyond the conduction band edge can alter the carrier density and transport properties. The quality of the interface and therefore Manuscript received May 27, 2014; accepted September 13, 2014. Date of publication September 29, 2014; date of current version October 20, 2014. The review of this brief was arranged by Editor S. Bandyopadhyay. M. N. K. Alam, M. S. Islam, and M. R. Islam are with the Department of Electrical and Electronic Engineering, Khulna University of Engineering and Technology, Khulna 9203, Bangladesh (e-mail: alamjhilam@gmail.com; mashru.islam@yahoo.com; islambit@yahoo.com). M. G. Kibria is with the Department of Electrical and Computer Engineering, McGill University, Montréal, QC H3A OE9, Canada (e-mail: md.kibria@mail.mcgill.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2358650

Fig. 1. Schematic of InGaSb XOI FET under study. All dimensions in the following figures are measured from gate–oxide interface along y direction.

the transport properties of the channel can be well understood from its capacitance voltage (CV) characteristics. Although the CV characteristics of SOI FET have been well understood, it has not been comprehensively studied for XOI FETs. Among III–V compound semiconductors, InGaSb exhibits highest electron and hole mobilities [5]. Therefore, it is expected that InGaSb XOI FETs may outperform other XOI FETs. Some preliminary results of the ideal CV characteristic of InGaSb XOI FETs were reported in our recent studies [6]. In this brief, we have comprehensively studied the CV characteristics of InGaSb XOI FET to demonstrate and optimize the interface properties. II. S IMULATION D ETAIL A. Device Structure The XOI device structure used in our simulation is shown in Fig. 1, where 7 nm In0.3 Ga0.7 Sb channel material is laid over a 50 nm SiO2 insulator layer, called buried oxide, which is grown on Si substrate. To achieve required control over channel, 10-nm-thick hafnium oxide (HfO2 ) is used as gate dielectric. Si substrate is left undoped and channel is doped with n-type impurity. B. Self-Consistent Theory Poisson’s equation for MOS electrostatic potential is [7] ε0 ε

d 2 v(y) = q[ p(y) − n(y) + N D − N A ] d y2

(1)

where n(y) and p(y) are, respectively, the electron and hole concentrations, N D and N A are the ionized donor and acceptor concentrations, respectively, ε is the relative dielectric constant, and ε0 is the free space permittivity. The electron

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ALAM et al.: ANOMALOUS STAIRCASE CV CHARACTERISTICS

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Fig. 2. CV profile of In0.3 Ga0.7 Sb XOI FET as a function of channel thickness. Inset: CCR region for clarity.

concentration n(y) for n-MOS structure can be given by [7]  n(y) = Ni j | ψi j (y) |2 (2) ij    E F − Ei j n vi m di K T (3) Ni j = ln 1 + exp KT π h¯ 2 where Ni j is the carrier concentration in the jth subband of the ith valley, n vi and m di are the ith valley degeneracy and density of states effective mass, respectively, n(y) is the total carrier concentration that can be obtained from the summation of Ni j over all the subbands, K is the Boltzmann constant, T is the temperature, E F is the Fermi energy, and E i j and ψi j are, respectively, the eigenvalue and eigen function of the jth energy level of the ith valley, which are obtained from the 1-D solution of the Schrödinger equation [7]   h¯ 2 d 2 (4) − ∗ 2 + V (y) ψi j (y) = E i j ψi j (y). 2m d y

In the Silvaco’s Atlas simulation package, (1) is solved using the semiclassical approximation assuming zero charge density, with Neuman boundary condition. Then the charge density profile n(y) is determined by combining (2)–(4). In our calculation, the first and second eigen values are considered. The charge density profile n(y) is then used to solve Poisson’s equation again, and the process is repeated until the selfconsistency is achieved. Then, the CV characteristics are determined from the device electrostatics. III. R ESULT AND D ISCUSSION In previous studies [8], the quasi-static CV characteristics of conventional SOI MOSFETs and bulk MOS devices were found almost symmetrical. Unlike them, the CV characteristics obtained for XOI FET with very thin-channel show staircase behavior as shown in Fig. 2. Here note for the 7 nm thickness (or in Fig. 4), the gate capacitance increases from its minimum value for gate bias (VG ) from 0 to 0.7 V and then remains constant up to VG = 2.1 V. This constant capacitance is denoted as the first-step constant capacitance region (CCR). After the first-step CCR, the gate capacitance further increases and then remains constant up to a gate bias of 3 V. This region is defined as the second-step CCR. This staircase behavior in the CV characteristics is unique and has been observed only for the XOI FET. Fig. 2 shows that with increasing channel

Fig. 3. Channel thickness-dependent (a) band diagram along with the first and the second eigen levels and (b) difference between the fist and the second eigen levels of In0.3 Ga0.7 Sb XOI FET.

thickness, the CV curves shift toward left for positive gate bias. Also note for the thicknesses above 15 nm, the CCRs disappear and CV curves show the same trend as SOI and bulk MOSFET [8]. To explain the anomalous nature in CV curves, channel thickness-dependent conduction band profiles as well as the first and second eigen energy levels are shown in Fig. 3(a) for VG = 3 V. Note that the finite quantum well structure of XOI FET causes the energy eigen levels to be discrete and it brings subbands at the channel. Occupation of these subbands depends on the relative position of Fermi level E F and eigen level E i j . With increasing positive VG , the eigen levels move downward (because Fermi level is kept fixed at 0 eV). When an eigen goes below the Fermi level, it gets populated. At a lower channel thickness (less than 10 nm), the difference between eigen states is quite high, which is shown in Fig. 3(b) for different VG . Therefore, when the Fermi level crosses the first eigen state and lie in between the first and the second, only the first eigen level contributes to the total charge in the channel. Owing to low density of states of III–V materials and a single subband contribution, biasdependent charge increment is small enough to make the capacitance constant, leading to the first-step CCR. With further increase in gate bias, the Fermi level goes over the second eigen state, hence both the first and the second subbands contribute and cause a jump in the total charge in the channel. Therefore, the capacitance changes from the first-step to the second-step CCR (Fig. 2). However, if the eigen energy states are close to each other, carriers can move smoothly in subbands. For channel thickness 15 nm or above, the difference between eigen levels gets lower

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014

Fig. 4. Channel composition-dependant CV characteristic of In1−x Gax Sb XOI FET.

Fig. 6.

Effect of doping on CV curves of In0.3 Ga0.7 Sb XOI FET.

thickness and effective mass. Doping concentration does not affect the separation between eigen states, and hence it does not perturb the staircase nature, as shown in Fig. 6. Increasing n-type doping lowers the difference between eigen levels and Fermi level at zero gate bias. Therefore, the CV curves left shifted (Fig. 6). The left shift represents a reduction in threshold voltage. IV. C ONCLUSION

Fig. 5. For different Ga composition, the first and the second eigen energy states as a function of electric field at gate oxide–channel interface.

enough for the smooth intersubband transition of carriers. As a result, no steps or CCRs are observed in the CV characteristics at high channel thickness (Fig. 2). Fig. 3(b) also shows that the difference between eigens is not constant but changes with VG owing to the bending of conduction band with it. Also it gets lower with increasing channel thickness for VG < 2 V. For VG > 2 V, the 15 and 20 nm channels show opposite trend. It is because at high gate bias, more carriers accumulate in the first subband and their electrostatic repulsion pushes the closely located the second eigen a little bit away. Fig. 4 shows the channel composition-dependent CV characteristics as a function of VG . The capacitance increases in each CCR with increasing Ga composition. Note that the CV curves left shifted during the transition from the first to the second step CCR. The increment in capacitance is due to the enhancement in effective mass and therefore the increment in the density of states with increasing Ga composition. The higher effective mass also reduces the separation between successive eigen levels. This is shown in Fig. 5 in which the composition-dependent first and second eigen energies are plotted with respect to electric field that exists at the gate–oxide and channel interface. Because the difference between the first and the second eigen energies for a given surface electric field (or respective gate bias) decreases with increasing Ga composition, the required gate bias for the transition from the first- to the second-step CCR also decreases (Fig. 4). The main reason of obtaining CCRs is the separation between eigen states, which is a function of channel

In this brief, quasi-static CV characteristics of ultrathinbody InGaSb XOI nFET are reported. Influence of different process parameters such as channel thickness, channel composition, and doping concentration on the CV profiles are studied. The CV characteristics obtained for InGaSb XOI nFET show an anomalous staircase nature for channel thickness at and below 15 nm. The gate capacitance in the first-step and the second-step CCRs found to have strong dependence with composition and channel thickness. Doping level does not affect the capacitance at saturation; however, it significantly left shifts the CV curves and thereby changes the threshold voltage. R EFERENCES [1] F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. Lundstrom, “On the performance limits for Si MOSFETs: A theoretical study,” IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 232–240, Jan. 2000. [2] G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys., vol. 93, no. 9, pp. 4955–4978, May 2003. [3] A. Nainani et al., “Inx Ga1−x Sb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design,” J. Appl. Phys., vol. 110, no. 1, p. 014503, 2011. [4] H. Ko et al., “Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors,” Nature, vol. 468, no. 7321, pp. 286–289, 2010. [5] A. Nainani et al., “Development of high-k dielectric for antimonides and a sub 350 °C III–V pMOSFET outperforming germanium,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2010, pp. 6.4.1–6.4.4. [6] M. N. Kutubul Alam, M. S. Islam, and M. R. Islam, “Self-consistent quasi-static C-V characteristics of In1−x Gax Sb XOI FET,” in Proc. IEEE Int. Conf. Electron Devices Solid-State Circuits (EDSSC), Jun. 2013, pp. 1–2. [7] F. Stern and W. E. Howard, “Properties of semiconductor surface inversion layers in the electric quantum limit,” Phys. Rev., vol. 163, no. 3, p. 816, Nov. 1967. [8] F. A. Ikraiam, R. B. Beck, and A. Jakubowski, “Modeling of SOI-MOS capacitors C-V behavior: Partially- and fully-depleted cases,” IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1026–1032, May 1998.

ALAM et al.: ANOMALOUS STAIRCASE CV CHARACTERISTICS

Md. Nur Kutubul Alam received the B.Sc. degree in electrical and electronic engineering from the Khulna University of Engineering and Technology (KUET), Khulna, Bangladesh, in 2012, where he is currently pursuing the M.Sc. degree. He is currently a Lecturer with the Department of Electrical and Electronic Engineering, KUET. His current research interests include device modeling, simulation, and nanotechnology. Mr. Alam received the Academic Gold Medal from KUET.

Muhammad Shaffatul Islam received the B.Sc. degree from American International UniversityBangladesh, Dhaka, Bangladesh, in 2010. He is currently pursuing the Degree in electrical and electronic engineering with the Khulna University of Engineering and Technology, Khulna, Bangladesh. His current research interests include III–V-based single- and double-gate MOSFET and the crystal orientation-dependent characteristics of devices.

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Md. Golam Kibria received the B.Sc. degree in electrical and electronic engineering from the Khulna University of Engineering and Technology, Khulna, Bangladesh, in 2006, and the M.A.Sc. degree in electrical and computer engineering from McMaster University, Hamilton, ON, Canada, in 2010. He is currently pursuing the Ph.D. degree with the Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada.

Md. Rafiqul Islam received B.Sc. (Eng.) degree in electrical and electronic engineering from the Khulna University of Engineering and Technology, Khulna, Bangladesh, in 1991, the M.Sc. (Eng.) degree in electrical and electronic engineering from the Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1998, and the Dr.Ing. degree from the Kyoto Institute of Technology, Kyoto, Japan in 2004.