future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future cha
Alert on LAN** Design Guide Application Note (AP-388) Revision 1.1 July 1998
Document Number: 703222-002
Revision Date
Revision
Feb. 1998
1.0
July 1998
1.1
Description First release •
Replaced Figure 3. "Overview of BIOS Support for Alert on LAN" with an updated version
•
Corrected SMB address to 0101AAA and added paragraph in Section 6.0, "System Management Bus (SMB)"
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Alert on LAN** ASIC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683. Many documents are available for download from Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1997 *Third-party brands and names are the property of their respective owners.
** Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
ii
Application Note (AP-388)
Contents 1.0
INTRODUCTION ......................................................................................................................... 1
2.0
HARDWARE REQUIREMENTS..................................................................................................1 2.1
2.2 2.3 2.4 2.5 3.0
82558 B-step (82558B) Fast Ethernet LAN Controller .................................................... 1 2.1.1 82558 B-step EEPROM ..................................................................................2 2.1.2 82558 B-step Clock Out 25 MHz Output ......................................................... 2 64x16 1 MHz EEPROM...................................................................................................2 Environmental Integrated Circuit ..................................................................................... 3 PIIX4 or Equivalent..........................................................................................................3 Sticky Latch (optional) .....................................................................................................3
BIOS REQUIREMENTS ..............................................................................................................4 3.1 3.2 3.3 3.4
Hardware Preparation for Boot........................................................................................6 System ID Programming ................................................................................................. 6 Watchdog Setup for Hang on Boot Alert .........................................................................6 POST Error Reporting Support .......................................................................................7
4.0
COMPONENT PLACEMENT ...................................................................................................... 7
5.0
ALERT ON LAN ASIC EVENT INTERFACE .............................................................................. 7 5.1 5.2 5.3 5.4 5.5
Cover Tamper .................................................................................................................7 Environmental System Management Interrupt ................................................................ 7 Board Temperature Interrupt ...........................................................................................8 LAN Leash.......................................................................................................................8 Processor Missing ...........................................................................................................8
6.0
SYSTEM MANAGEMENT BUS (SMB) .......................................................................................8
7.0
SMOOTH CLOCK SWITCHING LOGIC ..................................................................................... 9
8.0
ALERT ON LAN ASIC SIGNALS................................................................................................9 8.1 8.2 8.3
PCI Reset and Main Power Good ................................................................................... 9 System Management Interrupt (SMI) .............................................................................. 9 Auxiliary Power Good and Main Power Good ...............................................................10
9.0
PCI COMPLIANCE....................................................................................................................10
10.0
ACPI B2 AND D2 POWER STATES.........................................................................................11
11.0
APPENDIX A: REFERENCE SCHEMATICS ............................................................................ 11
Application Note (AP-388)
iii
iv
Application Note (AP-388)
1.0
Introduction This application note provides information and design specific considerations relevant to system designers interested in implementing a design using the Alert on LAN** ASIC. The Alert on LAN ASIC was specially designed to operate through Intel’s 82558’s Total Cost of Ownership (TCO) Interface. It is not a stand alone device and requires additional components to create a functional management solution. The following is a list of documents related to the Alert on LAN ASIC and can be obtained through your local Intel sales representative:
• • • • •
Alert on LAN ASIC Datasheet Alert on LAN ASIC Software Developer’s Manual 82558 Total Cost of Ownership (TCO) Management Interface Application Note (AP-385) 82558 Fast Ethernet PCI Bus Controller with Integrated PHY Datasheet 82557 C-step and 82558 Based Products EEPROM Address Map and Programming Information Application Note (AP-382)
• Alert on LAN Stepping Information
2.0
Hardware Requirements The Alert on LAN ASIC is not a stand alone device. It requires additional components to create a functional management solution. One possible set of supporting hardware is identified in this section.
• • • • • Note:
2.1
82558 B-step Fast Ethernet LAN Controller 64x16 1 MHz EEPROM Environmental Integrated Circuit (IC) PCI-to-ISA/IDE Xcelerator (PIIX4) Sticky Latch (optional)
Supporting hardware sets will differ from implementation to implementation.
82558 B-step (82558B) Fast Ethernet LAN Controller The 82558 Fast Ethernet LAN Controller is required for a complete solution. The Alert on LAN ASIC is designed to communicate with the proprietary TCO interface of the 82558B. The 82558B provides the functionality to transmit data on the network and calculates and adds a checksum to the data from the Alert on LAN ASIC.
Application Note (AP-388)
1
Alert on LAN** ASIC Design Guide
2.1.1
82558 B-step EEPROM The 82558’s EEPROM map for word Ah is illustrated in Figure 1. Word Ah
15
14 SIG
13
12
11
ID
CLK ISOL DIS
BD
10
9
8
REV ID
7
6
5
PWR MGT
TCO EN
WOL
4
3 00b
2 EXT CLK EN
1
0
PHY ADDR
Figure 1. 82558 B-step EEPROM Word Ah The following fields of the 82558’s EEPROM word Ah should be set to 1b to enable the TCO interface when an Alert on LAN ASIC is present. (Details can be found in the 82557C and 82558 EEPROM Map and Programming Information Application Note, AP-382.)
• • • • 2.1.2
Bit 12: Clock Isolation Disable Bit 6: TCO Enable Bit 5: Wake on LAN* (WOL) Bit 2: External Clock Enable
82558 B-step Clock Out 25 MHz Output 2.1.2.1
82558 Clock Out Signal Quality
The 25 MHz output clock is a full 5 V swing with a strong driver behind it. To reduce ringing and emissions, a series resistor should be used on this line. The resistor value should effectively match the trace impedance less the driver impedance. Another reason for the series resistor is to eliminate large undershoots. Large undershoots can cause the 3126 gate to turn on momentarily if the difference between ground and the voltage of the undershoot is greater than the VGS (gate-to-source) threshold voltage of the FET in the 3126.
2.1.2.2
82558 Clock Out Errata
The 82558B Clock Out output signal (CLKOUT) can be configured to output a 25 MHz clock signal. This helps reduce design cost when it is used as a 25 MHz clock to the Alert on LAN ASIC instead of using an oscillator. However, there is an erratum in the 82558B. The CLKOUT clock may not start from applied power (cold boot) if there are no clocks on its PCI_CLK input. The Alert on LAN ASIC works around this by relying on the PIIX4’s “power-up on cold boot” feature. This ensures that the PCI_CLK will be enabled. Therefore, the ASIC defaults to the PCI_CLK (expecting it on power-up) and therefore provides the 82558B with the necessary clocks to prevent the no start CLKOUT condition.
2.2
64x16 1 MHz EEPROM The Alert on LAN ASIC is designed to use a 64x16 1 MHz EEPROM to configure the default settings upon reset and hard G2 transitions. If an EEPROM is not present or contains an invalid checksum, the Alert on LAN ASIC will default to its component default settings as defined in the Alert on LAN ASIC Datasheet. Note:
2
The 82558 requires the use of an EEPROM for its configuration settings; this is a separate EEPROM from the 82558B’s EEPROM.
Application Note (AP-388)
Alert on LAN** ASIC Design Guide
2.3
Environmental Integrated Circuit An environmental IC that is capable of monitoring voltage, temperature, and cover tamper can be used as part of the system management solution. However, only one input exists on the Alert on LAN ASIC.
2.4
PIIX4 or Equivalent The PIIX4 device provides the SMB master interface that enables the system BIOS and OS to communicate with the Alert on LAN ASIC. PIIX4 also provides the PWR_GOOD and PCI_RST# signals that propagate to the Alert on LAN ASIC. Note:
The PIIX4 has the ability to force the system into a low power state without prior indication to software. Thus, the Alert on LAN ASIC monitors PWR_GOOD for a hard G2 transition. If the PIIX4 power-up feature is disabled by external hardware, it may cause an initialization problem with the Alert on LAN ASIC since it expects a PCI_CLK on power-up. It is the responsibility of the designer to ensure that the Alert on LAN ASIC and the 82558B get at least four clocks during hardware reset and at least four clocks after hardware reset to overcome this problem. Contact your local Intel representative for more suggestions on how to work around this problem.
2.5
Sticky Latch (optional) Sticky latches can are useful for detecting events that occur when the system is in a G3 state (completely off), such as Cover Tamper input. The latch can be battery-backed so that the Alert on LAN ASIC will become aware that an event occurred when it is powered-up. A sticky latch also provides the ability to be reset by driving the opposite polarity to the latch on the bidirectional pin, EVENT_1, of the Alert on LAN ASIC. The EVENT_1 pin of the Alert on LAN ASIC has the ability to clear a sticky latch. If this feature is enabled, it is executed by clearing the STA_EV1 bit in the Event Status register. The result is at least a 20 ms output pulse of opposite polarity on the EVENT_1 pin. An example sticky latch circuit is illustrated in Figure 2.
2M
2M
SAMPLE/CLEAR 5VSB 10K
SET
Figure 2. Sticky Latch Example Note:
This solution also prohibits the use of the ASIC cover tamper clear mechanism (the ASIC can be configured to output a 20 ms clear pulse). The environmental IC should clear the sticky latch.
Application Note (AP-388)
3
Alert on LAN** ASIC Design Guide
3.0
BIOS Requirements The Alert on LAN ASIC support for POST failure reporting requires changes to the client system’s BIOS. The BIOS software performs four important tasks within the Alert on LAN Client while the client is in the preboot state. 1. The BIOS software disables (masks) the generation of hardware alert messages and heartbeat messages at the Alert on LAN ASIC. This task is important because it ensures that Alert on LAN ASIC’s transmission activity will not interfere with later BIOS and OS initialization activities. 2. The BIOS software programs and guards against corruption of the System ID field in the Alert on LAN ASIC’s EEPROM. 3. The BIOS software configures the Alert on LAN ASIC to generate a watchdog alert message if the client system hangs during POST or OS boot. 4. The client BIOS software provides the Alert on LAN ASIC POST error capability. When the BIOS discovers a fatal error during POST, the BIOS generates a software event message to the Alert on LAN Proxy Service (APS).
4
Application Note (AP-388)
Alert on LAN** ASIC Design Guide
The figure below shows the high level flow of the steps an Alert on LAN enabled BIOS follows during the preboot state. 1
Start Pre-POST No
System ID Valid
Yes No
LAN exists
Update System ID and Set Global Disable
Init AP registers
Yes
No
Disable Watchdog
AP exists
No
Disable AP transmits
No
AP Enabled
Yes
Yes
EEPROM read after reset
Enable AP Transmit
Yes
EEPROM Checksum OK
No
Send System Awake
No
Send Heartbeat Start
Yes
User Setup Enables AP Yes
1
Exit Pre-POST
Figure 3. Overview of BIOS Support for Alert on LAN More detailed information regarding BIOS requirements is described in the Alert on LAN ASIC Software Developer’s Manual.
Application Note (AP-388)
5
Alert on LAN** ASIC Design Guide
3.1
Hardware Preparation for Boot Prior to OS Boot, the Alert on LAN enabled BIOS must disable the generation of heartbeat messages and hardware alert messages. The BIOS should disable heartbeat message generation by disabling the Alert on LAN ASIC Heartbeat Timer. The BIOS should disable generation of hardware alert messages as well by masking all hardware events.
3.2
System ID Programming The Alert on LAN enabled BIOS is responsible for programming and maintaining the System ID in the Alert on LAN EEPROM. The Alert on LAN EEPROM is described in detail in the Alert on LAN ASIC EEPROM Application Note, AP-387. The System ID for the given system is a constant value programmed into the BIOS code. At powerup, the BIOS should compare the current System ID value contained at offset 3Eh in the Alert on LAN EEPROM against the expected value in the BIOS code. If the System ID value in the EEPROM differs from the expected value, the BIOS should write the expected System ID value into the Alert on LAN EEPROM and set the Global Disable Bit.
3.3
Watchdog Setup for Hang on Boot Alert The Alert on LAN enabled BIOS should configure the Alert on LAN ASIC to generate a watchdog event if the BIOS hangs during POST or the OS hangs during boot. To accomplish this, the BIOS must perform two tasks. 1. The BIOS must unmask generation of watchdog events by writing a value of 40h into the Alert on LAN Event Mask register. 2. The BIOS must program the Alert on LAN Watchdog Status Byte register to FFh and set the Alert on LAN Watchdog Timer. The value programmed into the Watchdog Timer should allow enough time for BIOS POST to complete and for the OS to boot. The BIOS may optionally support the POST check-pointing feature. This feature enables the APS to identify where in the system boot sequence the hang occurred. The BIOS enables this feature by updating the Alert on LAN Watchdog Status Byte at the beginning of individual POST test and again just prior to OS boot. The following table describes the defined Watchdog Status Byte register values. Table 1. Defined Watchdog Status Values Value 00h 01h - FEh FFh
6
Watchdog Message Power On HANG POST Checkpoints OS Boot
Application Note (AP-388)
Alert on LAN** ASIC Design Guide
3.4
POST Error Reporting Support The Alert on LAN enabled BIOS should generate an Alert on LAN software event message on a fatal POST Error. First, the BIOS should write the POST failure code into the Alert on LAN Software Status Byte registers in big-endian byte ordering with low byte in Software Status Byte 1 and the high byte in Software Status Byte 2. Next, the BIOS should set the software event bit in the Alert on LAN Event Status register. The software event message will inform the APS of the POST failure and provide the POST Error Code to the system administrator.
4.0
Component Placement The Alert on LAN ASIC should be placed as close as possible to 82558B, clock switching logic, and EEPROM. The recommended distance between each of these components is less than one inch.
5.0
Alert on LAN ASIC Event Interface The Alert on LAN ASIC is designed to provide the capability of generating alerts in fully operational and low power states if any of the five hardware events occur. The Alert on LAN ASIC implements the following alerts:
• • • • •
5.1
Cover Tamper Environmental System Management Interrupt (SMI) Board Temperature Interrupt (BTI) Thermal LAN Leash Processor Missing
Cover Tamper Cover Tamper is used to indicate that the cover has been opened and is typically wired to a batterybacked sticky latch. Due to process limitations of the Alert on LAN ASIC, a low impedance path exists between all inputs and VDD when the ASIC is not powered. Since the sticky latch is battery-backed, this may result in battery drainage when the system is unplugged (no AC power). Details are described in the Alert on LAN Stepping Information document. This is normally an active high input signal to the Alert on LAN ASIC.
5.2
Environmental System Management Interrupt The SMI line of the environmental integrated circuit (IC) should be connected to the ASIC. The environmental IC is typically used to monitor motherboard voltages or fans. The current implementation of the Alert on LAN ASIC does not have the capability to integrate the
Application Note (AP-388)
7
Alert on LAN** ASIC Design Guide
environmental IC. Therefore, designs are based on only one event of interest (such as fan or voltage sense) to determine the cause of an Environmental SMI. This is normally a level active input signal to the Alert on LAN ASIC.
5.3
Board Temperature Interrupt The BTI input to the ASIC is delivered from a thermal sensor close to the system’s microprocessor(s). This is normally an active high input signal to the Alert on LAN ASIC.
5.4
LAN Leash The LAN Leash input to the ASIC is simply a link indication. It should be connected to the 82558 via pin number 162, LILED#. This is normally an active high input signal to the Alert on LAN ASIC.
5.5
Processor Missing This input to the ASIC is intended to indicate when one or more of the system processors is missing and depends on the processor used. One example is to use the Slot Occupied (SLOTOCC#) signal on the Pentium ® II processor. This is normally an active high input signal to the Alert on LAN ASIC.
6.0
System Management Bus (SMB) The Alert on LAN ASIC provides a slave SMB interface used for configuring the ASIC. Pull-up resistors are required on both of the signals. The resistor values are dictated and described in the System Management Bus (SMB) Specification. The ASIC SMB address is 0101XXXb, where XXX is defined by pull-up and pull-down resistors on SMB_A[2:0] (also used as TCO Data Bus[2:0] signals) pins. A minimum value of 2 KΩ pull-up resistor is required to overcome the internal pull-down resistance of the 82558 B-step device. Pulldown resistor values may be larger (for example, 10 KΩ). The SMB address lines that are required to be read as 1b should be pulled-up externally with relatively strong pull-up resistors (for example, 1 KΩ or 2.2 KΩ). This is necessary because the pull-down resistors on the same lines in the 82558 B-step may be active, depending on the reset sequence between PCI_RST# and AUX_GOOD, and cancel out the effect of the internal Alert on LAN pull-up resistors. Note:
8
The SMB interface of the ASIC supports Transistor-to-Transistor Logic (TTL) level inputs. Thus, if the SMB is a 3.3 V bus, a 3 V to 5 V conversion is not required. Since the bus is open drain (the pull-up resistors provide the logic high level), the ASIC can drive the SMB to 5 V.
Application Note (AP-388)
Alert on LAN** ASIC Design Guide
7.0
Smooth Clock Switching Logic The 82558B requires smooth clock switching logic to operate with flexible filters and TCO mode. This logic is required to avoid glitches that may potentially alter the operational sequence of the micromachine such that it will execute operations destructive to flexible filter when switching between the 33 MHz PCI clock and the 82558 external clock output. The smooth clock switching logic for the ASIC operates with 2 clock domains, the PCI Clock signal (PCI_CLK) and the 82558 external clock output signal (CLKOUT). Each domain has several memory cells. To switch from one domain to the other, clocks from both domains are required. Attention should be given to any signals from PIIX4 to the clock generation IC which might stop the PCI_CLK before the power transition (for example, PCI_STOP#). Note:
The Alert on LAN ASIC defaults to the PCI_CLK and assumes that the PIIX4 will force an AC power-up of the main supply, thus supplying a PCI_CLK. This was implemented to overcome the CLKOUT start-up anomaly in the 82558B. More information on the CLKOUT anomaly can be found in the 82558 Stepping Information document. The routing of this logic should receive high priority since it is very time sensitive. Traces should be kept to a minimum length. A 3126 part should be used since the circuit was modeled on the QSI 3126. Additionally, it will also work with TI 3126.
8.0
Alert on LAN ASIC Signals
8.1
PCI Reset and Main Power Good The Alert on LAN ASIC blocks the PCI Reset (PCI_RST#) signal from the 82558B when the Main Power Good (PWR_GOOD) signal is low. This is required to prevent the 82558B from resetting during normal power-down situations. Otherwise, the 82558B will lose its PCI device state (return to D0) and lose any programmed flexible filters. PCI_RST# is typically asserted by the PIIX4 during power-down. PIIX4 looks at a Power OK (PWROK) signal that is transitioning low and then asserts PCI_RST#. PWOK and PWR_GOOD should be the same signal (or derived from the same source with identical timing). This allows the ASIC to see PWR_GOOD at the same time PIIX4 does and block the PCI_RST# that the PIIX4 is about to drive low.
8.2
System Management Interrupt (SMI) The ASIC provides an SMI# signal for indication of events to the local CPU. Since these interrupts can happen during low power states, this interrupt should be connected (if used) to an input on the PIIX4 (or PIIX6) which provides SMI, SCI, and Resume capabilities. However, the current software stack does not use interrupts.
Application Note (AP-388)
9
Alert on LAN** ASIC Design Guide
8.3
Auxiliary Power Good and Main Power Good Typically, the Auxiliary Power Good (AUX_GOOD) signal is expected to transition from low to high before the Main Power Good (PWR_GOOD) signal transitions from low to high. However, this is not a restriction on the Alert on LAN ASIC. Note:
The AUX_GOOD signal works as a hardware reset signal (active low) to the ASIC. This signal must be a quick transition signal and driven by sound logic. The PWR_GOOD signal has a Schmitt-triggered input in the ASIC. It does not require a quick transition signal; however, it is recommended since low rise and fall time signals are susceptible to DC offsets from crosstalk of other signals.
9.0
PCI Compliance Due to the nature of the Alert on LAN solution with the 82558B, special clocking is required on the PCI_CLK signal. The loading characteristics of the PCI_CLK are as follows: PCI_CLK Net Connection
Min
Alert on LAN ASIC 82558 B-step
Typ
Max
2.5
Units pF
5.0
12.0
pF
3126 Analog Switch
8.0
pF
Stray 3126/82558B Traces
4.0
pF
The maximum and minimum calculation exceeds the maximum allowed by the PCI specification (12 pF). Several methods can be implemented to compensate this:
• Reduce the overall capacitance by reducing the trace length of the PCI_CLK signal to the 3126/82558B, which reduces trace capacitance
• Run a separate PCI_CLK trace to the Alert on LAN ASIC to reduce the total capacitance to the 3126/82558B trace Note: The 2.5 pF loading on the Alert on LAN ASIC does not meet the minimum capacitance of 5 pF. However, the Alert on LAN ASIC does not have access to the PCI bus and does not require a close timing reference to PCI_CLK. At minimum, the following PCI_CLK characteristics should be met:
• Verify that the clock skew between all PCI_CLK traces is at maximum 2 nanoseconds. • If worst case PCI timing (11ns) is to be met, the Alert on LAN ASIC must have zero or negative skew on the PCI_CLK in relation to the PCI_CLK seen by the 82558B. In other words, the PCI_CLK should arrive at the Alert on LAN ASIC and 82558B at the same time or slightly faster to the Alert on LAN ASIC (but not slower). This is unlikely to be a concern since this is only necessary if worst case PCI timing is required, and the Alert on LAN ASIC is worst case process, temperature, and voltage. However, it is mentioned in this document for completeness.
10
Application Note (AP-388)
Alert on LAN** ASIC Design Guide
10.0
ACPI B2 and D2 Power States The Alert on LAN ASIC uses the PWR_GOOD signal as an indication of whether to switch between the PCI_CLK or the CLKOUT of the 82558B clock source. The 82558B requires a clock source to function in TCO mode that the ASIC uses. It also requires the clock to support flexible filtering. However, the B2 PCI bus state (which implies the D2 device state) implements a stopped PCI clock with power still applied to the PCI bus. This indicates that the 82558B would not have a clock to perform TCO or flexible filtering since the ASIC will still select the PCI_CLK (PWR_GOOD is still valid). This is a scenario that is not covered in the implementation since the Alert on LAN solution is targeted for managed desktops. The B2 bus state has little use in a desktop model and is unlikely to be implemented.
11.0
Appendix A: Reference Schematics The following pages contain reference schematics for an 82558B/Alert on LAN ASIC design.
Application Note (AP-388)
11
1
2
3
4
6
5
D
D
Alert on LAN* Reference Schematics C
C
SHEET 2: 82558 82555.SCH
B
SHEET 3: LM79 & Interface LM79.SCH
SHEET 4: AP Asic & related logic AP_LOGIC.SCH
NOTES: 1. These are generic schematics intended to be used as reference only. 2. All references to VCC should be interpreted as +5V standby supply unless otherwise noted. 3. All GND references should be interpreted as digital ground. 4. This design assumes a PIIX4 is used as the SMB Master. 5. This design assumes that PIIX4 forces full power-on at AC power-on. 6. This design assumes that the Cover Tamper sticky latch is cleared by the LMxx. 7. Use these reference schematics along with an Alert on LAN* datasheet.
B
SHEET 5: Power Detect & Reset PHY_WOL.SCH
SHEET 6: Bypass Caps & Testpoints CAP.SCH A
A Title Size B Date: File: 1
2
3
4
5
Alert on LAN* Reference Schematics Number
Revision
Alert on LAN*
23-Jan-1998 A:\AP_EVAL.PRJ
Sheet 1of 6 Drawn By: 6
03
2
3
4
5
6
98 60 200 199 196 190 191 121
1
C/BE#[3:0]
From ASIC, Page 4
C/BE0# 106 C/BE1# 92 C/BE2# 76 C/BE3# 62
82558RST#
82558RST#
PCI_CTRL
41 REQ# 38 GNT# CLK 35 INTA# 42 82558RST# 37 FRAME# 78 TRDY# 83 IRDY# 79 STOP# 86 IDSEL 59 DEVSEL# 84 PERR# 87 SERR# 89 PAR 90
From PCI Interface
From Page 5
AUX_GOOD
VCC R26 or equivalent may already exist on Mother board.
R26 10K 201645-073
B To Page 4
AUX_GOOD 36 39 PME# TEST 30
PME#
C52 X1
1
C53
197 198
4
Y1 CRYSTAL_25MHZ 201760-011
nc
27pF 108425-006
X2
25M_CLK
27
RDP RDN
TDP TDN
171 172
RDP RDN
TPE_DATA D VCC
82558B
LILED ACTLED SPEEDLED
C/BE0# C/BE1# C/BE2# C/BE3#
FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
REQ# GNT# PCLK INTA# RST# FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# PERR# SERR# PAR
FD7 FD6 FD5 FD4 FD3/PHY_SA FD2/EEDI FD1/EEDO FD0/EESK FCS# FOE# FWE# EECS
ALTRST# PME# TEST X1 X2
VREF RBIAS10 RBIAS100
EXT_CLK
162 163 164
LILED ACTLED SPEEDLED
128 132 135 136 139 140 142 143
FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
LED DS1 641184-001
2 LED DS2 641184-001
ISOLATE#
FA[7..0]
144 146 151 153 154 155 156 159
FD7 FD6 FD5 FD4 FD3 FD2/EEDI FD1/EEDO FD0/EESK
127 122 123 160
FCS# FOE# FWE# EECS
180 181 182
U2VREF BIAS10
R35 220 202285-033
FA[7:0]
This pull-down on LISTAT indicates that the 82558 is powered by an auxiliary power source. To ASIC on Page 4 FD[7:0]
FL_CTRL B
The values of the RBIAS resistors may require tuning for your board implementation. Use these values as a starting point.
BIAS100 R6 634 202286-174 1%
VCC
R7 768 202286-182 1%
R1 220 202285-033 5%
93C46
R101 10K 201645-073
U5
16
R25 39 A_CLK
PCLK A B25_SEL PCI_SEL
B25_SEL PCI_SEL
3 6 11 14 2 5 12 15
1A 2A 3A 4A 1OE 2OE 3OE 4OE
1Y 2Y 3Y 4Y
U15 4 7 10 13
A Title
8
Clk Select lines from ASIC
109862-201
202285-015 VCC
A_CLK
Size QS3126 100625-184
B Date: File:
Tex
1
2
C
LILED
GND
Main clock source for ASIC
LED DS3 641184-001 1
ZREF LISTAT ISOLATE#
R14 510 202285-042
1
SLVTRI MDC RSTOUT ZREF LISTAT ISOLATE#
R10 10K 201645-073
203 17 3 15 204 31
R13 510 202285-042 2
R12 510 202285-042
R27 1K 201645-049
27pF 108425-006
186 187
1 2 3 4
From PCI Interface
TDP TDN
EECS EESK EEDI EEDO
C
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
2
D
119 118 116 115 113 112 110 107 105 102 101 99 97 95 94 93 75 73 72 70 69 66 65 63 58 57 55 54 52 51 47 46
1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
NCH NCG NCF NCE NCD NCC NCB NCA
U2 AD[31:0]
3
4
5
82558B.SCH Number
Revision
Alert on LAN*
23-Jan-1998 A:\82555.SCH
Sheet 2 of 6 Drawn By: 6
03
2
D
3
4
+3.3V 3.3V
VCC
R41
-12V 27.4K 1%
+12V 4.75K 1%
+1.5V +2.5V +3.3V VCC
R40
+3.3V
C
U7 HEC-12V +12V VCC +3.3V +2.5V +1.5V
FAN1_TACHOMETER FAN2_TACHOMETER COVER
14 15 16 17 18 19
FAN1 FAN2
5 6
COVER
7
SDA SCL
3 4
AUX_GOOD
AUX_GOOD
+3.3V
R49 10K 201645-073
HH2
C
+2.5V_Sense/+Vccp2 +12VIN +5VIN +3.3VIN +2.5VIN +Vccp1
V+ INT# VID4 VID3 VID2 VID1 VID0
FAN1 FAN2
12
9 10
LM_SMIA
20 21 22 23 24
VID4 VID3 VID2 VID1 VID0
11
FAN_CTRL
LM_SMIA
VID[4:0] CHS_SEC NTEST_IN/AOUT
SDA SCL
D
The HH2 or equivalent Environmental IC is shown below as an example only. Actual connections for voltage/temperature/fan monitoring is specific to each board implementation.
202286-258
+3.3V
6
5
202286-331
1
SDA SCL
NTEST_OUT/A0 A1
RESET# GNDD GND
B SMB_ADR=58 (HEX) 680050-101
FAN_CTRL
To ASIC, Page 4
VID voltage lines to CPU Analog output to control fan speed
1 2 8 13
R28 10K 201645-073
R37 10K 201645-073
B
U8 LM75 Temperture Sensor
BTI
LM75
A
A Title Size
HH2.SCH Number
B Date: File: 1
2
3
4
5
23-Jan-1998 A:\HH2.SCH
Revision
Alert on LAN* Sheet 3 of 6 Drawn By: 6
03
A
B
C
D
5
8
U9
93C46
1 2 3 4
1
1
3
U3B 4
22 23 24 25 26 29
ASIC_COVER
1 2 SW_NO
N.O.
SW1
2
3
4 3
2
2N7002 603400-001
G D S
Q1
The reason for the sticky latch being powered by battery is to store the fact the cover was tampered even with the power plug removed from the PC.
Switch Closes when PC cover is removed. A photo detector with an active low output can be used in place of mechanical switch.
3
2M 202285-128
R17
74LV14 676292-101
36 37
SCL SDA
687974-002
SMB_ADR=5C
SMB_SCL SMB_SDA
EE_CS EE_SK EE_DI EE_DO
Cover LM_SMI BTI LANLEASH PROC_MISS EVENT 6
AUX_GOOD
PWR_GOOD
PCI_CLK
SMI_OUT#
PCI_RST# 82558_RST# ISOLATE#
TSTATUS# TREADY#
TRDREQ TMARKER TACTIVE
TFORCE
TDATA0 TDATA1 TDATA2 TDATA3 TDATA4 TDATA5 TDATA6 TDATA7
B25_SEL PCI_SEL
AP_ASIC B25_CK
U12
FD5 FD6 FD7 FWE# FOE# RST# 82558RST# ISOLATE#
14 11 1 10 35 32 15 33
C4 .1uF 108427-050
2M 202285-128
R16
2
COVER
U3A
676292-101 74LV14
10K 201645-073
R15
PME#
3.3 volts
B1 BATTERY
1
4
PME# 5
To Page 3
COVER
6
VCC
WAKE_UP
FAN
VCC
R36 1K 201645-049
R102 1K 201645-049
VCC
74HCT14 108251-181
U4C
FAN
BTI PROC_M
SMI_OUT#
SCL SDA
FD3
44
34
FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7
2 3 4 7 8 9 12 13
R46 1K 201645-049
B25_SEL PCI_SEL
4
43 41
This Resistor is required but not duplicated on the Mother Board.
The default address is 5C (HEX). Use 2K resistors on TDATA2, TDATA1, and TDATA0 to set bits [3:1] of this address.
18 19 20 21
LIDED
LM_SMIA
30
AUX_GOOD
31
40
PCI_CLK PCI_GOOD
42
EE_CS EE_SK EE_DI EE_DO
VCC
R106 1K 201645-049
LIDED
LM_SMIA
ASIC_COVER
AUX_GOOD
PCI_GOOD
PCI_CTRL
A_CLK
3
A_CLK
ASIC_COVER R23 The Cover Tamper Input to the ASIC is isolated 1K an N-channel FET because the ASIC can 201645-049 with sink current through the Vcc rails when power is completely off and the battery backed-up sticky latch is driving a positive potential.
VCC VCC
R20 1K 201645-049
R20 and R23 should not be stuffed if they are some where else on the Mother Board.
SDA SCL
109862-201
VCC EECS EESK EEDI GND EEDO
Signals to LM79, Page 3
VCC
Pin 162 of 82558
Pin 40 of LM79 or equivalent.
Example AUX_GOOD signal from Page 5
Example PWR_GOOD signal from Page 5
PCI_CLK from PCI bus
A_CLK source from Y2 on Page 2
2
14
1
1 2
WAKE_UP
FAN
VCC
BTI PROC_M
SIM_OUT#
SCL SDA
R27 1K 201645-049
R103 1K 201645-049
FA[7..0]
PCI_CTRL 82558RST# ISOLATE#
FL_CRTL
FD[7..0]
FA[7..0]
B25_SEL PCI_SEL
5
Date: File:
B
Size
Title
Alert on LAN* 26-Jan-1998 A:\AP_LOGIC.SCH
Number
AP_LOGIC.SCH
Wake Up Signal If this siganl is required, do not connect the PME# signal out of the 82558B to the PCI interface.
Connected to the TACK output of the CPU FAN. See LM79 or equivalent device specification.
Every part that requires VCC on these schematics should be not be connected the VCC Power Plane, but to AUX 5 volt Plane, unless otherwise noted.
BTI = Thermal sensor near CPU Processor Missing
6
6
Sheet 4 of 6 Drawn By:
To 82558 interface on page 2.
To Clock stearing logic on Page 2
Interupt Line out of ASIC (active low) This open drain interrupt can be shared with other interrupts i
SDA and SCL signals will come from PIX4 or equavailent.
5
Revision 03
A
B
C
D
A
B
C
1
PCI_PWR
PCI_PWR
1 D1
BAV99LT1 305901-001
This is an example circuit to generate a PWR_GOOD signal. NOTE that the output edges are driven by real digital logic ensuring quick transitions. BAV99LT1 305901-001 D2
2
2
Four Diode drops are used here to ensure that PWR_GOOD goes low as soon as power is falling. This is necessary b/c of the low Vil of the 74HCT14 part.
1
RDP RDN
TDN
TDP
2
C12 12pF 108425-002
U4A
74HCT14 2.7K 108251-181 R39 201645-059
1
C14 .1uF 108427-050
2
3 74HCT14 108251-181
U4B 4
3
C8 .1uF 108427-050
PCI_GOODX
1000pF 108425-063
C13
R4 49.9 202286-068 1%
R2 49.9 202286-068
MAGTERM
R5 49.9 202286-068 1%
R3 49.9 202286-068
3
PCI_GOOD
C7 .1uF 108427-050
0 ohm 108506-002
R34
VCC
RX+ RXRXC
TX+ CMT TX-
4
10/100 MAGNETICS 677262-001
RD+ RDRDC
TD+ TDC TD-
U1
PCI_GOOD
1 2 3
16 14 15
4
7 6 5
10 12 11 RX+ RXMAGRXC
RP2A 75 202474-022
TX+ MAGCMT TX-
8 1
D
TPE_DATA
2
RST
VCC
3
5
SPRVSR 658184-001
U6
RP2B 75 202474-022
5
6 TERMPLANE
RP2C 75 202474-022
C29 1500pF 108425-027
RP2D 75 202474-022
Date: File:
B
Size
Title
9
8
AUX_GOOD
Alert on LAN* 23-Jan-1998 A:\PHY_WOL.SCH
Number
PHY_WOL.SCH
74LS14
U4D
This is an example circuit for the generation of AUX_GOOD. A supervisor IC is used to generate a clean transition and also monitor the voltage.
3
1
3
5 4
Analog Differential Signals from 82558B
3
7 2 2 VCC GND 3
6
6
Sheet 5 of 6 Drawn By:
Revision
C1 .1uF 108427-050
CGND
SMT RJ45 623377-001
AUX_GOOD
1 2 3 4 5 6 7 8
J1
11 12
03
C30 .1uF 108427-050
A
B
C
D
A
B
C
D
1
1
C58 .1uF 108427-050
C59 .1uF 108427-050
AP_ASIC Bypass
C60 .1uF 108427-050
C61 .1uF 108427-050
C66 .1uF 108427-050
C62 .1uF 108427-050
2
PCI_PWR
C63 .1uF 108427-050
C68 .1uF 108427-050
C43 .1uF 108427-050
C67 .1uF 108427-050
LM79 bypass Caps
C44 .1uF 108427-050
PCI_PWR
2
C64 .1uF 108427-050
C69 .1uF 108427-050
C45 .1uF 108427-050
C65 .1uF 108427-050
VCC
3
VCC
C57 4.7uF 202170-004
C22 .1uF 108427-050
C40 .1uF 108427-050
C28 .1uF 108427-050
C36 .1uF 108427-050
C31 .1uF 108427-050
C34 .1uF 108427-050
C33 .1uF 108427-050
C24 .1uF 108427-050
AUX_PWR
VCC DECOUPLING
C56 4.7uF 202170-004
AUX_PWR DECOUPLING
C47 .1uF 108427-050
+3.3V
C42 .1uF 108427-050
+3.3V DECOUPLING
3
4
C3 4.7uF 202170-004
C25 .1uF 108427-050
C6 .1uF 108427-050
C23 .1uF 108427-050
4
C48 4.7uF 202170-004
C16 .1uF 108427-050
C19 .1uF 108427-050
C39 .1uF 108427-050
C5 .1uF 108427-050
C26 4.7uF 202170-004
C35 .1uF 108427-050
C9 .1uF 108427-050
C38 .1uF 108427-050
C11 4.7uF 202170-004
C10 .1uF 108427-050
C46 .1uF 108427-050
C18 4.7uF 202170-004
C15 .1uF 108427-050
C27 .1uF 108427-050
C37 .1uF 108427-050
5
5
Date: File:
B
Size
Title
23-Jan-1998 A:\CAP.SCH
Number
CAP.SCH
C41 4.7uF 202170-004
C32 .1uF 108427-050
C21 .1uF 108427-050
C20 .1uF 108427-050
Alert on LAN*
6
Sheet 6 of 6 Drawn By:
6
Revision
03
A
B
C
D
