Power management IC and bypass capacitor placement area are restricted ...
This application note provides the basic notice of power supply design of.
Application note Power Supply Design of High Speed memory May 2011 Fujitsu Semiconductor Limited
Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Contents Introduction Background Purpose
Notice Recommended operating condition Average current ant Peak current Voltage drop Bypass capacitor placement
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Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Introduction Background More difficult power supply design • Peak current increasing with increasing memory data bandwidth • Voltage margin decreasing with lowering operation voltage • Timing margin decreasing with higher clock speed
Less PCB space with high density mounting • Power management IC and bypass capacitor placement area are restricted
Purpose This application note provides the basic notice of power supply design of high speed memory.
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Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Recommended operating condition (1) Supply voltage level must be designed within recommended operating condition VDD and VDDQ are referenced to VSS and VSSQ Variation of VSS and VSSQ must be considered
Example Supply voltage spec: VDD = VDDQ = min 1.7 to max 1.9V
1.9V
1.9V
1.8V
1.8V
1.7V
1.7V Time
Note VDD: VSS:
Core power supply, Core ground,
NG
NG Time
VDDQ: VSSQ:
DQ power supply, DQ ground 3
Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Recommended operating condition (2) Dynamic and Static voltage drop must be considered. Recommended operating condition is specified at supply voltage pad of memory chip. Voltage drop occurs on power distribution network between power supply source of power management IC (PMIC) and memory chip.
Example: Power distribution network Power supply source
Package
PCB
Chip (memory) VDD/VDDQ VSS/VSSQ
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Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Average current and Peak current Peak current must be considered as well as average current. Peak current is bigger than average current as shown below • Peak current may cause dynamic voltage drop • Generally only average current is shown in datasheet
Example: Current profile of 1 bank operation CK Command
ACT
RD D0 D1 D2 D3
DQ
Peak current
Current profile
Average current
0 Time 5
Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Dynamic voltage drop Dynamic voltage drop at load-transient must be considered. Current rapidly pump when system status move from STANDBY to ACTIVE which may cause significant dynamic voltage drop
Example: 1.8V voltage profile of load-transient System status
STANDBY
ACTIVE
STANDBY
Current profile
1mA
500mA
1mA
Voltage profile 1.9V 1.8V 1.7V Voltage drop 6
Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Bypass capacitor placement (1) Separate VDD from VDDQ If VDD and VDDQ are connected to same power supply source the bypass capacitor for VDD should be placed to avoid noise affect from VDDQ as shown in the following Good example
Example: bypass capacitor placement Good example
Bad example
VDD
VDD
Power supply
Power supply VDDQ
noise
VDDQ
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Copyright 2011 FUJITSU SEMICONDUCTOR LIMITED.
Bypass capacitor placement (2) Bypass capacitor value VDD-VSS：
0.1uF
• Recommend to place bypass capacitors to all VDD terminals
VDDQ-VSS： 0.1uF
Bypass capacitor location Bypass capacitor should be placed as close as possible to VDD and VDDQ terminals to minimize inductance
