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Application of Discontinuous PWM Modulation in Active Power Filters Lucian Asiminoaei, Member, IEEE, Pedro Rodríguez, Member, IEEE, and Frede Blaabjerg, Fellow, IEEE
Abstract—Classical discontinuous pulsewidth modulations (DPWMs) may not be efficiently applied in active power filters (APFs), because it is hard to predict the peak values of the inverter current, and consequently it is difficult to calculate the position of the clamped interval, that minimizes the switching losses in any operating point. This paper proposes a new DPWM strategy applied to shunt APFs. The proposed modulation strategy detects the current vector position relative to the inverter voltage reference and determines instantaneously the optimum clamped duration on each phase. It achieves a clamped voltage pattern, with variable lengths depending on the magnitude of the inverter current. This property adaptively reduces the current stress and minimizes the inverter switching losses, regardless of its application. The proposed modulation strategy is described, analyzed and validated on a three-phase voltage source inverter, rated at 7 kVA 400 V, controlled as an APF. Index Terms—Active filters, losses, power system harmonic, pulsewidth modulated (PWM) inverters, reactive power, switches.
Fig. 1. Principle diagram of a shunt APF for mitigation of harmonic currents from an adjustable speed drive. The power inverter receives the gating signals from the pulsewidth modulator.
I. INTRODUCTION
A
shunt active power filter (APF) is a power electronic device used for mitigation of the harmonic currents from non-linear loads. It is connected either near to the non-linear load or at the point of common coupling (PCC) and it has the task to detect and cancel out the harmonic content of the load current [1] (see Fig. 1). As the cost of the APF is still relatively high, its utilization is more efficient for medium- or high-power applications. However, for high-power, the inverter cannot operate at very high switching frequency because of the considerable increase of the switching losses. On the other hand, a lower switching frequency is not desirable because the reduced controller bandwidth determines improper harmonic compensation and unstable operation [2]. To meet the constraints of high-power, several solutions may be found for active filtering. One solution is to use hybrid power filters (HPFs), which requires a smaller rated inverter [3], but the HPF is not suitable in any case, for example when the reactive power needs also to be compensated. Another solution that copes with high power is to connect smaller power inverters in
Manuscript received August 30, 2006; revised February 8, 2007. Published June 13, 2008. Recommended for publication by Associate Editor F. Z. Peng. L. Asiminoaei is with Danfoss Drives A/S, Graasten DK-6300, Denmark (e-mail:
[email protected]). P. Rodriguez is with the Department of Electrical Engineering, Universitat Politecnica de Catalunya, Terrassa-Barcelona 08222, Spain (e-mail:
[email protected]). F. Blaabjerg is the Dean of the Faculty of Engineering, Science and Medicine, Aalborg University, Aalborg 9220, Denmark (e-mail:
[email protected]). Digital Object Identifier 10.1109/TPEL.2008.924599
parallel, but the overall control and parallel operation are more complex [4], [5]. Soft switching techniques may also be used to reduce the power losses, although it requires faster routines and hardware for the detection of the current/voltage zero-crossing [6]. One potential solution that allows an increased switching frequency for high-power inverters is the use of discontinuous pulse width modulation (DPWM) [7]. Theoretically, DPWMs give an average of 33% reduction in switching losses compared to continuous PWMs (CPWM), or alternatively allows an increase of the switching frequency by 33%. Furthermore, DPWMs may be easily implemented on regular voltage source inverters, opposite to soft switching converters, which require custom built hardware. DPWMs have successfully been used in applications where the behavior of the plant is well known, such as unity power factor utility interface applications and induction motor drives with known power factor [8], [9]. For plants where the phase of the load current changes within limited values, the clamped region may be placed such that there is no switching in the vicinity of the current peaks [10]. For applications where the behavior of the plant is not exactly known or the current displacement has a large variation, it is required to measure the current, which allows placing the clamped region for the switch conducting at the largest current. This principle is used in [11], where the phase angle of the inverter current is calculated and the clamping is automatically shifted within an interval of 60 , to obtain minimum switching losses. In [12] the peak inverter current position is measured, which determines the
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Fig. 2. Discontinuous modulation waveforms for modulation index of 0.73 and sinusoidal reference voltage at fundamental frequency. The output voltage (V ) of the discontinuous modulation is obtained by modifying the initial reference voltage (V ) according to the imposed zero-sequence signal (V ). (a) DPWM0. (b) DPWM1. (c) DPWM2. (d) DPWM3.
power factor and decides the optimal placement of the clamped voltages. A similar algorithm based on instantaneous current values is proposed in [13] for four-leg inverter, and applied for fundamental current. However, these applications are given for motor drives, where the output current is sinusoidal, with fundamental frequency. In APFs the inverter current mainly consists of harmonics, which makes the calculation of the phase angle or peak current difficult. Furthermore, the use of a fixed clamped region of 60 , may not be very efficient for APFs, because of the complex shape of the inverter current, which has various peaks, depending on the existing harmonics. This paper describes a new DPWM strategy that detects the current vector position relative to the inverter voltage reference and instantaneously determines the optimum clamped duration on each phase. It achieves a clamped voltage pattern, with different durations depending on the inverter peak current at each instant. This adaptively clamps the switch that conducts the largest current at any instant, reducing the current stress and switching losses.
The proposed DPWM (hereafter referred to as generalized DPWM or GD-PWM) is applied in this paper in active harmonic filtering, but it is proven that this modulator is suitable for any type of applications. The paper analyzes the proposed GD-PWM strategy, and describes its implementation on a threephase voltage source inverter rated at 7 kVA, 400 V. II. DESCRIPTION OF THE PROPOSED MODULATION PWM has been a subject of intense research, different types of modulations being proposed for various applications. Selection of a proper modulator depends on the desired linearity, modulation range, waveform quality, switching losses, and easy of numerical implementation in digital signal processors (DSPs) [7], [8], [11]. Two types of carrier-based modulators are largely used: CPWMs (e.g., sinusoidal, space vector modulation, etc.) and discontinuous modulators (DPWM0-4) [9]. A. Discontinuous Pulsewidth Modulations In discontinuous modulation only two phases are modulated, while the third phase is clamped to one of the positive
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Fig. 3. Simulated plots of the inverter reference voltage (dashed line) and current (solid line, scale 10:1). (a) and (c) Sinusoidal current reference of 1.6 A , cos(') 0.95, displayed in time domain, respective coordinates. (b) and (d) Harmonic current reference, displayed in time domain, respective coordinates. The plots show only the span of the voltage and current vectors within first two sectors, i.e., 120 compared to plots in time-domain that show a complete period, i.e., 360 .
0
0
or negative 2 rails. Since the phase that is clamped has no switching losses it is desirable to have the largest current passing through it. However, in classical discontinuous modulator the current is not considered and therefore, the modulation has a fixed pattern, selected depending on its application. The pattern is created by changing the distribution of the zero-vectors, which is the same as introducing a zero-sequence signal with defined shape [7] in each pole voltage. Several common used discontinuous modulators are presented in Fig. 2. DPWM1 has the center of each clamped region aligned to the reference voltage peak, which makes it suitable for unity power factor applications. DPWM0 and DPWM2 are efficient for 30 leading respective lagging power factors, and DPWM3 is a distortion-optimized modulation [14], which may be used in reactive power compensation. Other discontinuous modulations are also disclosed in literature [11] but their utilization is limited, as they give unequal stress in the semiconductors. B. Generalized Discontinuous Pulse Width Modulations The proposed GD-PWM is based on the inverter reference as like in the existing DPWMs, but also on the voltages inverter reference currents . The principle is similar as in
0
[12] where the measured current is used for calculation of the inverter power factor, which decides the placement of the clamped region. Fig. 3(a), shows a simulated case when the inverter has a sinusoidal current reference with a lagging power factor of 0.95. It is easy to determine the power factor and the peak value from the measured inverter current. The clamped region for phase-A reference voltage can naturally be placed around the peak current. It is acknowledged that the algorithm presented in [12] relies on the position of the space vector; therefore, it is possible that similar results may be obtained as it is presented in the proposed manuscript if the algorithm described in [12] would be applied for APFs. However, its application in APFs is not stated explicitly. For APF application, the measurement of the inverter power factor is difficult, because the output current mainly contains harmonic frequencies. A small fundamental current still exists, imposed by the voltage controller mainly to cover the losses and keep the dc-voltage at the imposed reference; but it cannot be used for an accurate calculation of the inverter displacement power factor. Fig. 3(b) shows a simulated case when the inverter current reference is a complex harmonic current that compensates the load current from an adjustable speed drive (ASD). In this case there are three instants when the inverter current on phase-A,
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Fig. 4. Simplified illustration of the proposed generalized discontinuous pulse width modulation (GD-PWM) for phase A. Both reference voltage and inverter current are required for the calculation of the clamped durations.
is larger compared to the other phase-currents (see the circled zones in Fig. 4). The fundamental current is much smaller than its harmonics. Fig. 3(c) and (d) show the plots of the inverter current and coordinates system, in correvoltages on the stationary lation to Fig. 3(c) respective Fig. 3(d). For a constant sinusoidal current reference the inverter current phasor describes a circle with fixed diameter, the same way as the reference voltage. Both rotate in the same direction, with the same span [e.g., of about two sectors in Fig. 3(c)]. For a harmonic current reference the inverter current phasor has variable amplitude and rotates faster compared to the reference voltage, depending on the existing harmonic currents. This indicates that not only the reference voltage is important but also the inverter current in determination of the optimum clamped intervals (see Fig. 4). If only the voltage references are used to do the clamping, without the knowledge of the position of inverter current vector, the obtained discontinuous modulation is not optimum in respect to the minimization of the switching losses, i.e. the switches conduct not always the maximum inverter current. The use of only the inverter currents is also not sufficient because the current vector may overpass sectors where it is not possible to clamp the associated phase voltage. The grey shaded areas in Fig. 4 indicate the sectors where the phase-A voltage cannot be clamped. Clamping is similar as adding an offset to all phase voltages. Inside the grey shaded areas, voltage if the phase-A voltage is clamped it determines over-modulation of at least another phase, with the consequence of loosing the controllability of the inverter current. The algorithm of the proposed discontinuous modulation, is presented in Fig. 5. It is performed each switching period, by using the reference voltages obtained from the inner current controller. Primarily, based on the calculated reference voltages the algorithm determines if the phase carrying the highest current is allowed to be clamped.
Fig. 5. Description of the logical algorithm of the proposed GD-PWM. The common mode voltages are calculated based on the allowed clamped interval and maximum current peak for each phase.
The algorithm establishes first what pole voltage is not allowed to be clamped. The other two pole voltages are associated to their reference phase currents. Based on a comparison of which phase current is higher in absolute value, the pole voltage is selected for clamping. The clamping is done to the positive or negative rails, in accordance with the sign of the respective phase voltage. If the highest current corresponds to the pole voltage not allowed for clamping, it will not be considered in the calculation of the common mode voltage. Thus, the second highest current is the one that establishes the associated pole voltage that is clamped. The output current may also be used instead of the reference current, but it will give a poorer performance because of its delay of one switching period. As the clamping depends on the amplitude of the output current, the clamp intervals are spliced in non-constant periods along the positive/negative periods, in APF applications compensating a wide bandwidth of harmonics. The sums of positive or negative clamped intervals are equal, only if the reference current system is balanced. Thus, the algorithm creates symmetrical switching patterns of positive and negative periods in a fundamental cycle. In this condition the equal distribution between positive and negative periods gives also equal switching losses among the power switches (i.e., upper respective lower power switches). In the case of non-balanced currents, it is true that the algorithm creates non-symmetrical switching pattern, which means
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0
Fig. 6. Simulation of the proposed GD-PWM. The output current I has fundamental frequency and a variable phase (') within the interval ( 90 ; 90 ). changes according to the phase change of the output current. (b) The shape of the common mode voltage V (a) The region of the clamped voltage V
.
that some power switches have wider clamped periods, and consequently lower switching losses. This subject is discussed in Section V. III. PERFORMANCE CRITERIA A modulator is characterized by different performance parameters [7], i.e., generated current harmonics, harmonic spectrum, maximum modulation index, switching frequency, switching losses and dynamic response. An analytical determination of these performances for the proposed GD-PWM is difficult in active filter applications, because the inverter current vector is not constant as in motor drives. As the output current of an APF depends on the compensated harmonic current spectrum, the result is not practically meaningful for all active filtering applications. However, the proposed GD-PWM may be evaluated based on sinusoidal output currents with fundamental frequency. It allows assessing its performance compared to the existing discontinuous modulations presented in Fig. 2. GD-PWM is first tested at different phase angles of inverter current. The current is set as in (1), where the phase linearly varies within 90 90
(1) is the magnitude of the output current, is the funwhere damental frequency here 50 Hz, and is the slope of the phase. The simulation results are shown in Fig. 6, for a single phase only. As the phase angle of the output current changes, the shape of the modulation changes also (i.e., the location of the clamped
Fig. 7. Comparison of switching loss factor SLF of the existing DPWMs and GD-PWM calculated for fundamental output current with a phase shift '(t) within ( 180 ; +180 ). The switching frequency is the same for all modulators.
0
region relative to the reference voltage ). It indicates that the proposed modulation follows the peak of the current such that it achieves minimum switching losses. During the span of the phase angle, depending on its current value, the shape of the resembles the following modulacommon mode voltage 90 , b) DPWM2 for 45 , tions: a) DPWM3 for 0 , d) DPWM0 for 45 , and e) c) DPWM1 for DPWM3 again for 90 . This is an indication that the
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Fig. 8. Simulation of the proposed GD-PWM. The frequency of the output current I is 250 Hz (i.e., fifth harmonic) and has variable phase (') within the interval changes according to the output current. (b) The shape of the common mode voltage V . ( 90 ; 90 ). (a) The region of the clamped voltage V
0
proposed GD-PWM unifies the existing discontinuous modulations presented in Fig. 2, depending on the actual output current vector. A. Switching Losses Evaluation of the switching losses is done in the same way as in [11], assuming that the inverter has a linear switching loss dependency with the amplitude of the current. The average value of the switching power losses over the fundamental period is evaluated in (2), (3) based on the turn-on and turn-off energy losses given by the commutation (2)
(3) is the dc-voltage, and are the turn-on rewhere spective turn-off intervals, is the switching frequency, is ”is the absolute value funcoutput inverter current, and “ tion. A coefficient named switching loss factor SLF is defined, by normalizing to the switching power losses of CPWM. SLF . is calculated as a function of the current phase angle SLF
(4)
Fig. 7 shows the SLF for an output current of fundamental frequency, at different phase angles . For CPWMs the factor SLF is 100%. For the existing DPWMs the SLF depends on the selected modulator, and varies according to the current phase angle. Regarding the proposed GD-PWM, because its clamped interval adapts with the current peak, the switching losses swing between the existing DPWMs, as it is shown in Fig. 6. Its adaptive tracking keeps the losses at the minimum, as confirmed in Fig. 7. The shaded area indicates that the GD-PWM acts in the same way as a discontinuous modulation that starts from the shape of DPWM0 and shifts the clamped interval towards DPWM2 and DPWM3, as illustrated in Fig. 6. Approaching the case of an active filter, Fig. 8 shows the simulation of the proposed GD-PWM for 250 Hz output current frequency, i.e., fifth harmonic current. The phase of the output current is again variable within 90 , during the selected time. Two phenomena are noticed: one is the shift of clamped interval for tracking the peak of the current, in the same way as presented for the fundamental frequency. The second phenomenon is the split of the clamped interval in smaller multiple clamped intervals, according to the frequency of the output current. Consequently, the shape and the frequency of common mode voltage also changes [see Fig. (8b)]. The calculation of switching losses factor SLF given by the harmonic current can be done in the same way as in (4). Fig. 9 shows the evolution of the SLF as a function of the phase angle, for fifth respective seventh harmonic currents. It is noticed that the amplitude of the SLF becomes lower with
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Fig. 9. Comparison of switching loss factor of the existing DPWMs and GD-PWM calculated for an output current with a phase shift within output current is: (a) fifth harmonic and (b) seventh harmonic. The switching frequency is the same for all modulators.
the increase of the harmonic order, and less sensitive to the current phase angle. As the harmonics go higher, the integral of the output current over a harmonic period becomes smaller and therefore, the variation of the phase angle is less significant. It is proven in Appendix A that the DPWM methods converge to an average switching losses of 66%, while the proposed GD-PWM converges to 54%, which means a further 12% reduction of the switching losses. On the other hand for higher frequencies the number of switching increase due to the multiple split of the clamped intervals, therefore, the power losses are also increased compared to what is given in Fig. 9. However, for the most dominant harmonics fifth and seventh it allows an increase of the switching frequency by a factor of 1.5–2 times the switching frequency of CPWMs, if the associated increase of the switching losses is allowed.
0180 +180 ;
. The
mental frequency, even though it is slightly changed by the control to produce the imposed output harmonic current (6) (7) (8)
(9) (10)
B. Current Distortion The copper losses are determined by the output current harmonics. The ratio between the RMS output current determined by the selected modulator, and the RMS current of an equivalent six-pulse converter, gives an indication about copper losses [15]
(5) The analytical calculation of -factor for fundamental current is given in [16]. The current distortion of various modulations can be estimated as in (6)–(11). The calculations are given for a three-phase system with sinusoidal duty-cycles, which is the case of motor-applications. However, these also apply for APF applications, because the inverter has to work against the line-voltage, assumed to be most of the time sinusoidal. The reference voltage resembles sinusoidal waveform with the funda-
(11) where is the modulation index, is the RMS value of the phase voltage, is the dc-voltage, is the frequency factor used for DPWMs to compare the switching losses at different switching frequencies. Fig. 10 shows the harmonic distortion factor, i.e. -term, as a function of the modulation index . As the APF is a gridconnected application, the modulation index is relatively high in steady-state. Typical values of the modulation index are placed between 0.75 to 0.95 (see the shaded area in Fig. 10), depending , and the on the maximum current gradient, the dc-voltage boost inductance . In the condition that the same switching frequency is used for all modulations, i.e. 1, the distortion factor of DPWMs is
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Fig. 11. Electrical diagram of the experimental setup for testing the performance of the GD-PWM in harmonic filtering applications.
Fig. 10. Harmonic distortion factor d , for different modulators. The DPWM plots are given in two cases, for a switching frequency factor k of 1 and 3/2 to be compared to the distortion created by CPWM strategies.
=
almost three times higher than of CPWMs. However, DPWMs allow operation of the inverter at an increased switching frequency, due to the reduction of the switching losses (see Section II-A). If the switching frequency factor is increased, e.g., 1.5, the distortion factor becomes comparable to CPWM. Regarding the proposed GD-PWM it is expected that the distortion factor stay within the limits set by DPWM1 and DPWM3, as illustrated by the shaded intervals. By considering the outcome of the GD-PWM in respect to the switching losses and the distortion factor, it is therefore proven that its performance is similar to CPWMs. However, its switching frequency is 1.5 times higher, providing an increased bandwidth and reduced delays, which allow a better harmonic compensation. As Fig. 10 shows, one concern is at the APF start-up, when the low modulation index determines higher harmonic distortion compared to its steady-state operation. One solution is to overrate the inverter and the passive elements (boost inductor, switching ripple filter, dc-capacitor) to cope with the generated harmonics. Another alternative is implementing a combined modulation strategy, e.g., SVM used at start-up followed by GD-PWM for normal operations, which gives an optimum overall performance [17]. C. Overmodulation, Voltage Linearity and Voltage Gain As the proposed modulation falls under the category of discontinuous modulations, the conclusions presented in [11] regarding the overmodulation, voltage linearity and voltage gain, apply also for GD-PWM. For instance, because the voltage linearity depends on the blanking time and minimum allowed pulse width (consequently on the duration of the zero vectors), DPWMs (including GD-PWM) have increased voltage linearity. The overmodulation is however, not desirable in APFs, because the inverter may loose the current tracking capability.
Regarding the dynamic performance in the linear region of the inverter, it mainly depends on the switching frequency [7]. Therefore, by increasing the switching frequency factor towards 1.5 helps for a faster dynamic response. However, the dynamic performance of the DPWMs during overmodulation is inferior to CPWMs because of the increased phase error, which may create unwanted dynamics [18]. IV. EXPERIMENTAL RESULTS The proposed GD-PWM and the other discussed DPWM strategies are implemented and tested on an APF laboratory setup. A. Laboratory Setup The general diagram of the experimental setup is shown in Fig. 11. The setup is realized with a 7-kVA 400-V VLT5006 Danfoss inverter. The inverter has a boost inductor of 5.82 mH and a dc-link capacitor of 2.2 mF. The switching frequency can be changed from 4 to 13 kHz. The control algorithm is implemented in Matlab Simulink, and executed on a dSpace DS1103 platform. A 5.5-kVA three-phase dc-smoothed diode rectifier that replicates the behavior of a typical adjustable speed drive produces the harmonic currents. The rectifier may be set as capacitive or ” and “ ” such that difinductive load by switching “ ferent cases may be created. The load is a variable resistor with values between 50–200 . This way one may create different levels of harmonic currents. The control algorithm and the harmonic detection method are developed in the synchronous -reference frame, although other harmonic detection methods may also be used [24]. The input signals , which are initially achieved in the stationary system, are transformed into the dq-rotating reference frame by means of the Park transformation. The frame rotates at fundamental angular frequency that makes the fundamental current as dc-component and the harmonics as ac-signals. The characteristic harmonics fifth and seventh harmonics become sixth harmonic in dq-frame, 11th, 13th become 12th, etc. Thus, the harmonic detection becomes a matter of removing the dc-signal by means of a high pass filter [19].
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Fig. 12. Diagram of the APF control, where the proposed GD-PWM and the other discussed DPWMs and CPWMs are implemented.
Fig. 13. Distribution of the power losses in a shunt APF. The losses in each element consists of both switching and conduction losses. The power difference P is an estimate of the total power losses in the inverter.
1
The block diagram of the proposed control (Fig. 12) is a typical implementation of an APF having current controllers in the inner loop and the voltage controller in the outer loop [20]. The current control is realized in a combined structure with a classical proportional-integral (PI) controller for fundamental current and resonant controllers, one for each harmonic pair 6 1 [21]. A detailed description of the inner current controller is given in [22]. The dc-voltage control loop is a classical PI controller. Its output is the current reference in -axis, which determines a real power to be drawn by the APF for keeping the dc-voltage at the imposed value. The compensation of the reactive power is only activated for some experiments, by providing the current reference to the -axis current controller. The proposed GD-PWM is implemented by software (see Fig. 12). The algorithm needs the reference voltages from the current controller, and the reference harmonic currents, as described in Section II. B. Measuring Power Losses The existing power inverter consists of a six-pack insulated gate bipolar transistor (IGBT) module, which did not allowed measuring the power losses across individual IGBTs. Estimation of the switching and conduction losses based on the
Fig. 14. Measured waveforms of the harmonic compensation using the proposed GD-PWM, for inductive load of ASD.
measured time-domain currents and voltages is also not very straightforward because of the complex shape of the output current. Furthermore, several other characteristics of the existing setup are not precisely known, such as the magnetic character, inverter snubbers, equivalent istics of the boost inductor series resistance of the dc-capacitor . Thus, existing estimation approaches [14] are difficult to apply. Therefore, the evaluation is done based on the overall power balance in an APF, as illustrated in Fig. 13. Due to the outer loop PI controller (see Fig. 11), the APF drowns a small amount of real power from the utility to charge the dc-capacitor at the imposed voltage, for future needs of energy. The process reaches zero error in steady-states conditions. Therefore, the power losses associated with the power inflow are automatically compensated to be a stationary increase of the voltage reference. As the APF starts the compensation of harmonic currents the energy is taken from dc-capacitor and supplied back to the grid as output harmonic current. The inner harmonic current controller controls this process, which has the task to assure zero stationary-error.
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Fig. 15. Measured waveforms showing the behavior of the GD-PWM for: (a) step of reactive power and (b) ASD startup while the APF initially provides 2.5 A reactive current to the grid. The ASD load is inductive.
TABLE I MEASURED POWER LOSSES AT 13 kHz SWITCHING FREQUENCY, BEFORE AND AFTER THE TRANSIENTS ILLUSTRATED IN FIG. 15
The associated power losses are seen as disturbances and therefore, automatically compensated, by drowning more energy from the dc-capacitor, which in turns is regulated by the outer dc-regulator and more real power is taken from the grid. Thus, represents an estimate of the total losses (switching and conduction) of the APF, which can be measured by a precision power meter connected at the point of common coupling. Fig. 14 shows the harmonic mitigation steady-state perforhas a THD of 23%, mance of the APF. The load current while the source current reaches a THD of 2.3%. The switching frequency was deliberately selected of a higher value, of 13 kHz, to increase power losses that can be easily measured. is clamped The shape of the reference voltage along several intervals with different lengths. Tests of the APF performed with other types of modulations gave the same performance at high switching frequency. However, it was noticed that at lower switching frequency (e.g. 5–7 kHz) the continuous modulations gave a better quality of the output current, due to the reduced phase errors, compared to the discontinuous modulations. Two dynamic tests of the proposed GD-PWM are performed in Fig. 15. In Fig. 15(a) the APF compensates at the beginning the harmonic current of the ASD. A step of 2.5 A current
1P
Fig. 16. Measured power losses using the presented modulations at different switching frequencies. The APF compensates only the harmonic currents produced by the ASD as it is shown in Fig. 14.
is imposed to the current reference, for reaching unity power factor, as it can be seen in the source current . The inverter changes such that clamped intervals are voltage placed over the peak values of the inverter output current . In Fig. 15(b) the APF is set at the beginning to provide only a reactive output current of 2.5 A , then the ASD is powered on. For the imposed reactive output current, the shape of the inverter voltage given by the proposed GD-PWM resemble DPWM3. Once the ASD is started, the APF output current changes and the load harmonic currents are compensated. The modulation shape changes according to the new output current. The power losses are measured for both cases, before and after the moment of the transient, in steady-states conditions. The measured valued for different modulations are given in Table I, indicating that the reduced losses of the GD-PWM.
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Fig. 17. (a) Measured current distortion of the APF due to the switching frequency for sinusoidal output reactive current of 2.5 A compensation of an inductive ASD as in Fig. 14. The APF uses the discussed modulations at different switching frequencies.
. (b) Harmonic current for
Fig. 18. Measured waveforms (source voltage V , load current I , source current I , filter current I , and duty cycle) of the APF using the proposed GD-PWM. The APF compensates the harmonic currents from an: (a) inductive ASD and (b) capacitive ASD.
The power losses of APF compensating the given load current are measured for different switching frequencies (see Fig. 16). As expected, continuous modulations give higher losses, while the losses of the discontinuous modulation, including the proposed GD-PWM, depend on the position of the clamped interval. For this case, DPWM3 and GD-PWM are almost the same regarding the power losses. Measurement of the harmonic current distortion produced by the switching frequency is shown in Fig. 17. Fig. 17(a) shows the harmonic distortion under reactive current, where mainly high order harmonics due to switching frequency are present, and ideally no low order harmonics. Fig. 17(b) shows the harmonic distortion under harmonic current (i.e. compensation of inductive ASD as in Fig. 14). Both figures confirm the conclusion reached in Section III-B that the distortion produced by the proposed GD-PWM is comparable to the distortion of other discontinuous modulations.
Fig. 18 shows the harmonic current compensation of the APF for two types of rectifier based ASDs having inductive, respective capacitive load current. The shapes of the duty cycles, which identify the output look different in both cases. As it can be voltage seen the duty-cycles are clamped along several intervals with different lengths, each time around the peak output current as illustrated by the circled zones of the inverter current . For the inductive ASD type, the shape of the duty cycle resemble the discontinuous modulation DPWM3 that has the split clamped intervals in the middle, while for the capacitive ASD type, the duty cycle is more close to DPWM1 that has the clamped interval centered at the voltage peaks [11]. Table II shows the power losses in both cases of inductive and capacitive ASDs, which confirms the adaptive character of the propose modulation depending on the position of the output current peaks.
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TABLE II MEASURED POWER LOSSES AT 13-kHz SWITCHING FREQUENCY, FOR DIFFERENT TYPES OF ASDS AS IN FIG. 18
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power losses, because of the implied symmetry of the voltages and currents. However, in real-life the grid has always a certain amount of unbalance and harmonic voltage predistortion. The current unbalance was simulated by changing phase-A current magnitude from 50% to 150% of nominal current. The effect is evaluated by calculating the SLF for each phase. Fig. 19(a) shows the switching losses for fundamental frequency current in phase with the inverter voltage (i.e., zero current displacement angle in Fig. 7). As it can be seen, the switching losses of SVM proportionally increases with the amplitude of the unbalance for phase-A; the other phases keep the same losses as in normal operation. The same happens for the DPWMs strategies, even though the rate of increase is smaller. Surprisingly, the distribution of the switching losses is different for the proposed GD-PWM. The SLF decreases for the unbalanced phase-A, while a slight increase is noticed for the other two phases. This is the direct consequence of how the GD-PWM works, the clamped interval is calculated for each phase based on the largest magnitude. Therefore, for an amplitude unbalance greater than 100%, phase-A is clamped over a longer interval compared to the other two phases, which determines a decrease of SLF for the unbalanced phase-A. This dynamic adjustment (i.e. shrinking for smaller current amplitudes, and vice-versa stretching for larger current amplitudes) of the clamped interval is beneficial for keeping the stress between switches at a minimum level. Fig. 19(b) presents the effect of the amplitude unbalance for fifth harmonic output current. Existing modulations, i.e. SVM and DPWMs perform the same as before for the fundamental frequency current. For GD-PWM, the switching losses increase also. The harmonic current splits the total effective clamped interval in multiple sections, which are spread along the allowed clamping interval of 240 . Therefore, the clamped intervals cannot be freely stretched according to the amplitude of the current, which explains why the losses also increase in GD-PWM for a harmonic current. It is estimated that a small phase unbalance does not create significant differences between the switching losses in each legs. Regarding the unbalance of the grid voltages it is also expected not to significantly change the switching losses. Higher level of voltage unbalances, as voltage sags and swells, are not evaluated here, mainly because it may not be required for an APF to operate under severe line fault conditions. B. Practical Reference Current for GD-PWM Applied in APFs
Fig. 19. Comparison of simulated switching loss factor SLF of the existing DPWMs and the proposed GD-PWM calculated for: (a) fundamental and (b) fifth harmonic output current in phase with the inverter voltage. Each subplot shows the SLF factor for: (a) phase-A, (b) phase-B, and (c) phase-C.
V. DISCUSSION A. Switching Losses in Non-Ideal Grid Conditions For ideal conditions of the power inverter and the grid voltages the proposed GD-PWM gives equal stress on the power switching devices, and assures a symmetrical distribution of the
The shape of the current reference supplied to the GD-PWM algorithm influences the effective power losses in APFs. For an APFs designed for typical six-pulse ASDs the current spectrum is dominated by the fifth and seventh harmonics, which are accountable for setting the clamped intervals. As noticed from the experimental results, even though the higher harmonics have smaller amplitudes they casually contribute to the split of the clamped interval, but mainly alter the duration of the clamped intervals. The outcome in respect to the reduction in the switching losses is insignificant, which explains the slight bigger losses of the GD-PWM in some experiments, compared to the DPWMs.
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Fig. 20. Illustration of the clamped voltage applied in APFs when the output inverter current is 13th harmonic. The modulation is: (a) DPWM0 and (b) the proposed GD-PWM.
One solution is to use in the calculation of GD-PWM, mainly the lower order harmonics. Therefore, the existing current reference can be pre-processed such that the higher harmonics are filtered out. A selective filter may also be used. The filtering must be carefully done to not introduce phase errors or to slower the inverter dynamic response. C. Application of GD-PWM in HPFs An HPF is a combination of a passive tuned filter and a power inverter, where the inverter is mainly used to improve the harmonic mitigation of the passive filter. Implementation of the GD-PWM is much easier for HPF because the inverter has to compensate mainly low order harmonic currents. Therefore, the current reference is already filtered and as the clamped intervals are determined by lower harmonics, their length is larger compared to APFs. Furthermore, the harmonic distortion generated by the use of GD-PWM is negligible in HPF due to the filtering effect of the passive components [23]. Thus, the issue of the increased distortion is eliminated. The reduction of the switching losses remains still around 54% compared to CPWM as demonstrated in Section II. It is documented in [23] that hybrid power filters are also more robust to the effect of overmodulation, because the associated tuned passive filter assures ride-through during the overmodulation periods. VI. CONCLUSION This paper describes a new DPWM strategy referred to as GD-PWM for APFs. The proposed GD-PWM is based on the detection of the current vector position relative to the inverter voltage reference, which enables to calculate the optimum clamped duration. It achieves spliced clamped voltage patterns, with different durations depending on the inverter peak current. This adaptively clamps the switch that conducts the largest current at any instant, theoretically reducing the switching losses from the average value of 66% in DPWMs to 54% in GD-PWM.
The paper analyzes the switching losses and the distortion factor of the proposed GD-PWM strategy, and describes its implementation on a three-phase voltage source inverter rated at 7 kVA 400 V. The experiments confirmed the theoretical analysis, proving that the presented GD-PWM is a discontinuous modulation that adapts according to the output current. Discussions are also given for its application in regular inverters operating at fundamental frequency. APPENDIX A Switching power losses associated with an output harmonic current of order converge towards a constant value if the harmonic is much higher than the fundamental period. Its calculation assumes that the switching frequency is high enough to approximate the switching losses with the integral of the output current. The switching loss factor is defined as switching losses generated by the considered DPWM normalized to the losses generated by the CPWM, which resumes to the ratio of integrals of absolute values the respective output currents. A. Switching Losses for Discontinuous PWM Fig. 20(a) illustrates the clamped voltage in the case of DPWM0 and 13th harmonic output current. It shows the associated notations used for the calculation of the SLF for half of fundamental period SLF
(12) (13)
The switching losses over the fundamental period are divided in two parts, one part during the clamped interval (where the
ASIMINOAEI et al.: APPLICATION OF DISCONTINUOUS PWM MODULATION
losses are zero as no switching occurs) and the other for the rest of the period, i.e., not-clamped interval
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The voltage is clamped such that the highest magnitude of the output current is not switched, which determines the switching and losses only during intervals of
(14)
During the non-clamped interval the losses are equally distributed in each period of the output harmonic current, therefore, ” the multiplication constant of “
(21) (22)
(23)
(15)
(16)
For the interval not allowed for clamping, the losses are equally distributed among the periods of the harmonic frequency
Finally the switching loss factor for DPWM gives a value of 66%, which agrees with the average value obtained in Figs. 7 and 9 SLF
(24)
(17)
(25)
B. Switching Losses for Generalized Discontinuous PWM Fig. 20(b) illustrates the clamped voltage in the case of GD-PWM and 13th harmonic output current. The figure shows the associated notations used for the calculation of the SLF for half of fundamental period
The switching loss factor for GD-PWM is 54% (see Figs. 7 and 9) (26)
SLF
SLF REFERENCES (18) (19)
The switching losses over the fundamental period are divided here in a different way, one part is the interval allowed for clamping (i.e., 240 ) and the other for the rest of ) the period (i.e., 120
(20)
[1] W. M. Grady, M. J. Samotyj, and A. H. Noyola, “Survey of active power line conditioning methodologies,” IEEE Trans. Power Del., vol. 5, no. 3, pp. 1536–1542, Aug. 1990. [2] H. Akagi, “Control strategy and site selection of a shunt active filter for damping of harmonic propagation in power distribution systems,” IEEE Trans. Power Del., vol. 12, no. 1, pp. 354–362, Feb. 1997. [3] S. Park, J.-H. Sung, and K. Nam, “A new parallel hybrid filter configuration minimizing active filter size,” in Proc. PESC’99, 1999, vol. 1, pp. 400–405. [4] L. Asiminoaei, C. Lascu, F. Blaabjerg, and I. Boldea, “Harmonic mitigation improvement with a new parallel topology for shunt active power filters,” in Proc. PESC’06, 2006, pp. 776–782. [5] L. Asiminoaei, E. Aeloiza, J. H. Kim, P. Enjeti, F. Blaabjerg, L. T. Moran, and S. K. Sul, “An interleaved active power filter with reduced size of passive components,” in Proc. APEC’06, 2006, vol. 1, pp. 969–976. [6] D. M. Divan, G. Venkataramanan, and R. W. A. A. DeDoncker, “Design methodologies for soft switched inverters,” IEEE Trans. Ind. Appl., vol. 29, no. 1, pp. 126–135, Jan./Feb. 1993. [7] J. Holtz, “Pulse width modulation for power electronic conversion,” Proc. IEEE, vol. 82, no. 8, pp. 1194–1214, Aug. 1994. [8] J. M. D. Murphy and M. G. Egan, “A comparison of PWM strategies for inverter-fed induction motors,” IEEE Trans. Ind. Appl., vol. IA-19, no. 3, pp. 363–369, May/Jun. 1983.
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[9] M. Depenbrock, “Pulse width control of a 3-phase inverter with nonsinusoidal phase voltages,” in Proc. IAS’77, 1977, vol. 1, pp. 399–403. [10] A. M. Trzynadlowski and S. Legowski, “Minimum-loss vector PWM strategy for three-phase inverters,” IEEE Trans. Power Electron., vol. 9, no. 1, pp. 26–34, Jan. 1994. [11] A. M. Hava, R. J. Kerkman, and T. A. Lipo, “A high performance generalized discontinuous PWM algorithm,” IEEE Trans. Ind. Appl., vol. 34, no. 5, pp. 1059–1071, Sep./Oct. 1998. [12] M. Malinowski and M. P. Kazmierkowski, “Adaptive modulator for three-phase PWM rectifier/inverter,” in Proc. EPE-PEMC’00, 2000, vol. 1, pp. 1.35–1.41. [13] V. H. Prasad, D. Borojevic, and R. Zhang, “Analysis and comparison of space vector modulation schemes for a four-leg voltage source inverter,” in Proc. APEC’97, 1997, vol. 2, pp. 864–871. [14] J. W. Kolar, H. Earl, and F. C. Zach, “Calculation of the passive and active component stress of three phase PWM converter systems with high pulse rate,” in Proc. EPE’89, 1989, pp. 1303–1311. [15] D. G. Holmes, “A general analytical method for determining the theoretical harmonic components of carrier based PWM strategies,” in Proc. IAS’98, 1998, vol. 2, pp. 1207–1214. [16] J. W. Kolar, H. Ertl, and F. C. Zach, “Influence of the modulation method on the conduction and switching losses of a PWM converter system,” IEEE Trans. Ind. Appl., vol. 27, no. 6, pp. 1063–1075, Nov./ Dec. 1991. [17] M. Malinowski, “Sensorless Control Strategies for Three-Phase PWM Rectifiers,” Ph.D. dissertation, Univ. Warsaw, Warsaw, Russia, 2001. [18] A. M. Hava, S. Sul, R. J. Kerkman, and T. A. Lipo, “Dynamic overmodulation characteristics of triangle intersection PWM methods,” IEEE Trans. Ind. Appl., vol. 35, no. 4, pp. 896–907, Jul./Aug. 1999. [19] S. Bhattacharya, T. M. Frank, D. M. Divan, and B. Banerjee, “Active filter system implementation,” IEEE Trans. Ind. Appl., vol. 4, no. 5, pp. 47–63, Sep./Oct. 1998. [20] S. Kim, M. H. Todorovic, and P. N. Enjeti, “Three phase active harmonic rectifier (AHR) to improve utility input current THD in telecommunication power distribution system,” IEEE Trans. Ind. Appl., vol. 39, no. 5, pp. 1414–1421, Sep./Oct. 2003. [21] M. J. Newman, D. N. Zmood, and D. G. Holmes, “Stationary frame harmonic reference generation for active filter systems,” IEEE Trans. Ind. Appl., vol. 38, no. 6, pp. 1591–1599, Nov./Dec. 2002. [22] C. Lascu, L. Asiminoaei, I. Boldea, and F. Blaabjerg, “High performance current controller for selective harmonic compensation in active power filters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1826–1835, Sep./Oct. 2007. [23] H. Fujita and H. Akagi, “A practical approach to harmonic compensation in power systems-series connection of passive and active filters,” IEEE Trans. Ind. Appl., vol. 27, no. 6, pp. 1020–1025, Nov./Dec. 1991. [24] L. Asiminoaei, F. Blaabjerg, and S. Hansen, “Harmonic detection methods for active power filter applications,” IEEE Ind. Appl. Mag., vol. 13, no. 4, pp. 22–33, Jul./Aug. 2007. Lucian Asiminoaei (S’03–M’06) received the M.Sc. degree in electrical engineering degree from the Faculty of Shipbuilding and Electrical Engineering, Section of Power Electronics and Advanced Control Systems, “Dunarea de Jos” University of Galati, Galati, Romania, in 1997, and the Ph.D. degree from Aalborg University, Aalborg, Denmark, in 2006. From 1996 to 1999, he was with Iron&Steelworks Sidex S.A., Galati, Romania, as a Maintenance Engineer and in 1999 he moved to the IT Department, IspatSidex LNM Group, Galati, Romania, as a Hardware Engineer. In 2003, he joined the Department of Power Electronics and Drives, Institute of Energy Technology, Aalborg University, being involved in projects sponsored by Danfoss Drives A/S, Denmark and Power Lynx A/S, Denmark. He was a Visiting Scholar at Texas A&M University, College Station. He
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is now with Danfoss Drives A/S, Graaston, Denmark. His areas of interests include harmonic mitigation, harmonic measurement, and design of active and hybrid filters.
Pedro Rodríguez (S’99–M’04) received the B.S. degree in electrical engineering from the University of Granada, Granada, Spain, in 1989, and the M.S. and Ph.D. degrees in electrical engineering from the Universitat Politecnica de Catalunya (UPC), Terrassa-Barcelona, in 1990 and 1994, respectively. In 1990, he joined the faculty of UPC as an Assistant Professor. He became an Associate Professor in 1993. Since 1995, he has been the Head of the Factory Automation Group, Terrassa, Spain. At UPC, he is a member of the Power Quality and Renewable Energy (QuPER) Research Group. He has authored more than 30 published technical papers and has been involved in several industrial projects and educational programs in the field of power electronics and systems. His research interests include modeling and control of power converters, multilevel converters, power conditioning, and renewable energy systems. Dr. Rodríguez is a member of the IEEE Power Electronics, IEEE Industrial Electronics, and IEEE Industry Application Societies.
Frede Blaabjerg (S’86–M’88–SM’97–F’03) was born in Erslev, Denmark, on May 6, 1963. He received the M.Sc.EE. and Ph.D. degrees from Aalborg University, Aalborg, Denmark, in 1987 and 1995, respectively. He was with ABB-Scandia, Randers, Denmark, from 1987 to 1988. He became an Assistant Professor in 1992 at Aalborg University, in 1996 an Associate Professor, and in 1998 a Full Professor in power electronics and drives. Today he is also Dean of the Faculty of Engineering Science and Medicine. In 2000, he was a Visiting Professor with the University of Padova, Padova, Italy, as well as a part-time Programme Research Leader in wind turbines at the Research Center Risoe. In 2002, he was a Visiting Professor at Curtin University of Technology, Perth, Australia. He is involved in more than ten research projects within the industry. Among them is the Danfoss Professor Programme in Power Electronics and Drives. He is the author or coauthor of more than 500 publications in his research fields including Control in Power Electronics (New York: Academic, 2002). He is an Associate Editor for the Journal of Power Electronics and Elteknik. He has been very involved in Danish research policy in the last ten years. His research interests are in power electronics, static power converters, ac drives, switched reluctance drives, modeling, characterization of power semiconductor devices and simulation, wind turbines, and green power inverters. Dr. Blaabjerg is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS and the IEEE TRANSACTIONS ON POWER ELECTRONICS. He is a member of the Danish Academy of Technical Science, the European Power Electronics and Drives Association, and the IEEE Industry Applications Society Industrial Drives Committee. He is also a member of the Industry Power Converter Committee and the Power Electronics Devices and Components Committee, IEEE Industry Application Society. He received the 1995 Angelos Award for his contribution in modulation technique and control of electric drives, the Annual Teacher Prize from Aalborg University, in 1995, the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society in 1998, five IEEE Prize paper awards during the last five years, the C. Y. O’Connor Fellowship from Perth, Australia in 2002, the Statoil-Prize for his contributions in power electronics in 2003, and the Grundfo’s Prize for his contributions in power electronics and drives in 2004.
