Наукові праці ДонНТУ Серія "Інформатика, кібернетика та обчислювальна техніка"
випуск 11(164), 2010
УДК 004.3 Approach to Realization of Compositional Microprogramming Control Unit with Code Converter on Custom-Made Matrix A. A .Barkalov1, I.J. Zelenyova2, A.N. Miroshkin 2, Hathot Biayrek2 1 University of Zielona Gora, Poland
[email protected] 2 Donetsk National Technical University, Donetsk, Ukraine
[email protected],
[email protected] Abstract Barkalov O., Zelenyova I.J., Miroshkin A.N., Hathot Biayrek. Approach to Realization of Compositional Microprogramming Control Unit with Code Converter on Custom-Made Matrix. The method of compositional microprogramming control unit realization on custom matrix is proposed. Using of code converter allows reducing the area of custom-made VLSI in logic circuit of control unit. Analysis of proposed method and results of modeling for flow-charts of control algorithm is carried out. Let initial GSA have starting vertex b 0 , final vertex b E , the set of the operational vertices B1 (the set of states of Moore automata), and conditional vertices set B2 . Vertices b q ∈ B1
Introduction The properties of the interpreted control algorithm have great influence on the hardware amount of corresponding control units. One of such properties is the existence of operational linear chains (OLC) corresponding to the graph-scheme of algorithm (GSA) paths, which include operator vertices only [1]. There are many of the approaches for linear graph-scheme of algorithm interpretation and one of them is the use of compositional microprogram control units (CMCU), which can be viewed as a composition of the finite state machine and microprogram control unit [2]. In this case control unit can be implemented as composition of automaton with “hardware” logic, realizing addressing of transitions, and automaton with “programmable” logic. The given article explains the method of CMCU synthesis with microinstructions code converter. The purpose of the research is realization of logic circuit of control unit on custom-made VLSI as interpretation of linear control algorithm. The task of the research is development of method for CMCU with microinstructions codes converter synthesis of microinstructions addresses that allows reducing the area of custom-made matrix for its logic circuit. The control algorithm is represented in the form of GSA.
contains
microoperations
Y(b q ) ⊆ Y ,
where
Y = {y1 ,...., y N } is the set of microoperations. In the vertices b q ∈ B2 elements from the set of logic conditions X = {x1,...., x N } are contained. Vertices GSA are connected by arches b t , b q , forming the set E . B j = {B0 ,..., BJ −1} is the set of the classes of
pseudoequivalent OLC [2]. Let us introduce some of definitions necessary for the further material explanation. Definition 1: An operational linear chain of GSA is a finite vector of operator vertices α g = {b g (1) ,..., b g (Fg ) } , such that an arch b g (i ) , b g (i +1) ∈ E
corresponds to each pair of
adjacent vertices b g (i ) , b g (i +1) , where i is the component number of vector α g . Definition 2: An operator vertex b q ∈ α g is called the input of OLC α g , if there is an arch
b t , b q ∈ E , such that b t = b 0 or b t ∈ B2 or b t ∉ αg .
Basic definitions and general provisions
Definition 3: An operator vertex b t ∈ D g is
Transformation of microinstruction addresses is oriented at the reduction of hardware amount in CMCU logic circuit. This method uses the transformation of microinstruction addresses of operational linear chains outputs into codes of the classes of pseudoequivalent OLC.
called the output of OLC α g , if there is an arch b t , bq ∈ E , bq ∉ αg .
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where
b q = b E or
b q ∈ B2
or
Наукові праці ДонНТУ Серія "Інформатика, кібернетика та обчислювальна техніка" Any
ОLC
α g can have more than one input,
ОLC
let us designate j input
випуск 11(164), 2010
The CMCU with converter microinstructions (Fig. 1) operates as follows:
α g like I g j , every
of
ОLC contain only one output Og , entering in the set O = {O1,..., O G } of ОLC outputs. The set of operator vertices of GSA is ОLC
C = {α1 ,...., α G } satisfying the following conditions: i j ⎧ ⎪α ∩ α = ∅; (i ≠ j; i, j ∈ [1..G ]), (1) ⎨ 1 2 G ⎪ ⎩α ∪ α ∪ ... ∪ α = B1 At performance of conditions (1) every vertex b q ∈ B1 enters exactly into one ОLC
Figure 1 – Structural diagram of CMCU U1 Pulse Start is used to load a zero address into the counter CT and to set up the flip-flop T (it gives Fetch = 1 ). If microinstruction Y (b q ) , where
α g ∈ C . A set of inputs I(Γ) of the operational
b q ≠ Q g g = [1..G1 ] , is read out of the CM, signal
linear chains of GSA Γ is I(Γ ) =
G
U I (α g ) .
y 0 is generated and content of the counter is incremented, in order to address next microinstruction corresponds to next component of the current OLC. If b q = O g , a transition address is
(2)
g =1
Also we have a set of outputs O(Γ) of the operational linear chains of GSA: O( Γ ) =
generated by combinational circuit CC using outputs of the address transformer AT and logical conditions. If microinstruction with y E = 1 is read out of the CM and flip-flop T is cleared and operation of CMCU terminated. Method of synthesis of CMCU U includes the following stages: 1. Creating the transformation of initial flow-chart. 2. Addition of internal control microoperations y 0 and y E .
G
U O( α g ) .
(3)
g =1
Let
A(b q )
be
a
binary
address
of
microinstructions corresponding b q ∈ B1 includes R A = ⎡log 2 M ⎤ bits, where the total microinstructions is equal to M = B1 microinstruction addressing can be microinstructions corresponding to components of each OLC α g ∈ C :
(4) number of . The natural executed for the adjacent
A (b g (i +1) ) = A (b g (i ) ) + 1 ;
3. Creation of the set C = {α1 ,...., α G } of OLC. 4. Natural addressing of microinstructions. 5. Forming the content of control memory (CM). 6. Splitting the set C of OLC on classes of pseudoequivalent OLC: B j = {B 0 ,..., B J −1} .
(5)
Let us encode each class Bi ∈ Π C by a binary code K(BJ) of R B = ⎡log 2 I⎤ (6) bits, using variables τ r ∈ τ , where τ = R B , for encoding the classes Bi ∈ Π C . It is possible now the initial GSA be interpreted using the model of CMCU with microinstructions codes converter [2], designated in the further symbol U1 (Fig.1), where an address converter AT converts output address of OLC α g ∈ Bi into the codes of classes Bi ∈ Π C .
7. Encoding of classes B j ∈ B . 8. Construction the table of address converter AT. 9. Construction the table of code converter. 10. Creation the logical circuit of CMCU U in the given element basis. Matrix realization of CMCU microinstruction addresses converter
In compositional microprogram control unit, combinational circuit CC implements the input memory functions (7) D = F(τ, x ) . And address converter AT implements functions of the system τ = F(T) . (8)
with
For implementation of the CMCU scheme on custom-made matrices we proposed to represent the CC circuit in the form of conjunctive matrix M1 and disjunctive matrix M 2 , CM is presented as matrix
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Наукові праці ДонНТУ Серія "Інформатика, кібернетика та обчислювальна техніка" M 3 and disjunctive matrix M 4 while the converter
випуск 11(164), 2010
device is introduced as M 5 matrix. (Fig. 2):
Figure 2 —Matrix realization of CMCU U1
C = {α1,..., α 4 } from the set we can now determine G = 4 , α1 = {b1} , α 2 = {b 2 , b3 } , α 3 = {b 4 } , α 4 = {b5 , b 6 } . Then we will create the partition K (Bi ) for our example, which contains blocks {B0 ,..., B2 } , where B0 = {α1} , B1 = {α 2 , α3 } , B2 = {α 4 } . So, for encoding of pseudoequivalent OLC classes B j ∈ Π C it is enough R B = 2 variables
From Fig. 2 we can calculate SCC CMCU , where SCC CMCU is the area of CMCU U:
SCC CMCU = SM1 + SM 2 + SM 3 + SM 4 + SM 5 ;(9) S M1 = 2 * ( L + R B ) * H ;
(10)
SM 2 = H * R A ;
(11)
SM 3 = 2 * (R A + 1) * 2R A ;
(12)
SM 4 = 2 R A * ( N + 2) ;
(13)
SM 5 = 2 R A * R B .
(14)
Example of application of CMCU converter of microinstructions
τ = {τ1, τ2 }. Let us encode classes Bi ∈ Π C in such way: K (B0 ) = 00 ,…, K (B2 ) = 10 . Table of transitions CMCU has the following columns: Bi – class of pseudoequivalent
with
OLC, K (Bi ) – code of class Bi , I g j , A (I g j ) , X h , Φ h , h . Table of transitions for CMCU U1 is given (Table 2). We don’t need to consider transition from OLC α 4 ∈ B2 as it goes to ending node. Applying of method of address converter is similar to applying of converter of states’ codes in codes of classes of pseudoequivalent states of Moore automaton.
Let us consider the example of CMCU synthesis method application with using initial GSA (figure 3). At first we add internal microoperations y0 and y E to the operational vertices and define the set of operational vertices B1 = {b1 ,..., b 6 } ; M = 6 , R A = ⎡log 2 M ⎤ = 3 . Then we try to form the set of operator vertices of initial GSA OLC,
Address
Table 1. Addressing of control memory words for CMCU Content BI ПС y2 y3 y4 yE
Igi
Og
α1
I1
O1
b2
α2
I2
-
0
b3
α2
-
O2
0
b4
α3
I3
b5
α4
1
-
b6
α4
2
O4
D3D2D1
y0
y1
000 001
1 0
0 1
0 0
0 1
0 0
0 0
b0 b1
010
1
0
1
1
0
0
011
0
1
0
0
1
100
0
0
1
0
0
101 110
1 0
0 1
0 0
1 1
0 1
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0 1
I4 I4
O3
Наукові праці ДонНТУ Серія "Інформатика, кібернетика та обчислювальна техніка"
випуск 11(164), 2010
where C rg is boolean variable. It is equal to “1”, if and only if α g ∈ Bi and bit r of K (Bi ) is equal to “1”, A g is a conjunction of variables Q r ∈ Q , which corresponds to address A (O g ) of OLC output α g ∈ Bi . Results of the modelling
Dependence custom-made matrix area on parameters of initial GSA is explored using expressions (9)-(14) and statistics of EXCEL (fig.4). 1800 1600 1400 1200 1000
Suconvert
800
Scmcu
600
Figure 3 – Initial GSA for CMCU U1
400 200
Table 2. Transitions for CMCU with code converter K (Bi ) Bi Xh Φh I g j A(I g j ) h τ1 τ 2 B0
00
B1
01
5 7 9 8 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
0
I2
010
x1
D1
1
I3
100
x1
D2
2
I2
010
x 2 x3
D1
3
Figure 4 –Dependence matrix area on number of transitions Results of research shows that effectiveness of code converter using depends most of all on possibility of classes forming and transition number reducing .
I41
101
x2
D2, D0
4
Conclusion
2
110
x 2x3
D2, D1
5
The proposed CMCU synthesis method targets to decrease in hardware amount, used area of the custom-made matrices. The method is based on encoding of the classes of pseudoequivalent OLC permitting decrease of the transition table lines in comparison with CMCU with base structure. Results of experiments show that the area of matrices is decreased up to 15%. Of course, application of proposed method is possible only for interpretation of linear GSA. The next step in research is exploration of possibility for given method application in case of standard elementary basis (CPLD, FPGA).
I4
With the table we can build system function (2), for example: D1 = F1 ∨ F3 ∨ F5 = τ1 τ 2 x1 ∨ τ1τ 2 x 2 x 3 ∨ τ1τ2 x 2 x 3 .(15) Table of the converter of addresses of microinstructions contains columns: O g , A (O g ) , Bi , K (Bi ) , τ j , g . If α g ∈ B j , then row g of table contains corresponded information. For our example address converter is given in table 3:
Og
Table 3 – Table of code converter g A (O g ) τj Bi K (Bi )
O1 O2
001 011
B0 B1
00 01
τ1
1 2
O3
100
B1
01
τ1
3
O4
110
B2
10
τ2
4
References
1. Barkalov A.A., Titarenko L.A. Synthesis Of Operational And Control Automata. – Donetsk: Unitech, 2005. – 256 pp. 2. Barkalov A.A., Titarenko L.A. Logic Synthesis for Compositional Microprogram Control Units,2008. – 272 pp. 3. Smith M. Application – Specific Integrated Circuits. – Boston: Addison Wesley, 1997. – 836 pp. 4. Baranov S. Logic Synthesis For Control Automata. – Boston: Kluwer Academic Publisher, 1954. – 312 pp. Received 29.03.2010
With the help of this table we can form system of functions G
τ r = ∨ C rg A g , (r = 1,..., R 0 ) , g =1
(16)
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