Architecture, Reconfiguration and Modeling

Muhammad Yasir Qadri and Stephen J. Sangwine (editors)

Multicore Technology: Architecture, Reconfiguration and Modeling

Contents

List of Figures List of Tables

xi xvii

Preface

xix

Contributors

xxv

I

Architecture and Design Flow

1 MORA: High-Level FPGA Programming Using a Many-core Framework Wim Vanderbauwhede, Sai Rahul Chalamalasetti, and Martin Margala 1.1 Overview of the state of the art in high-level FPGA programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Introduction to the MORA framework . . . . . . . . . . . . . 1.2.1 MORA Concept . . . . . . . . . . . . . . . . . . . . . 1.2.2 MORA Tool Chain . . . . . . . . . . . . . . . . . . . . 1.3 The MORA Reconfigurable Cell . . . . . . . . . . . . . . . . 1.3.1 Processing Element . . . . . . . . . . . . . . . . . . . 1.3.2 Control Unit and Address Generator . . . . . . . . . . 1.3.3 Asynchronous Handshake . . . . . . . . . . . . . . . . 1.3.4 Execution Model . . . . . . . . . . . . . . . . . . . . . 1.4 The MORA Intermediate Representation . . . . . . . . . . . 1.4.1 Expression Language . . . . . . . . . . . . . . . . . . . 1.4.2 Coordination Language . . . . . . . . . . . . . . . . . 1.4.3 Generation Language . . . . . . . . . . . . . . . . . . 1.4.4 Assembler . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 MORA-C++ API . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 MORA-C++ by Example . . . . . . . . . . . . . . . . 1.5.3 MORA-C++ Compilation . . . . . . . . . . . . . . . . 1.5.4 Floating-Point Compiler (FloPoCo) Integration . . . . 1.6 Hardware Infrastructure for the MORA Framework . . . . . 1.6.1 Direct Memory Access (DMA) Channel Multiplexing . 1.6.2 Vectorized RC Support . . . . . . . . . . . . . . . . . 1.6.3 Shared Memory Access . . . . . . . . . . . . . . . . .

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4 6 6 6 6 8 8 9 12 12 13 15 16 17 18 19 19 22 27 29 29 30 30 i

ii 1.7

1.8

Results . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.1 Thousand-core Implementation . . . . . . . . . 1.7.2 Results . . . . . . . . . . . . . . . . . . . . . . 1.7.3 Comparison with Other DCT Implementations Conclusion and Future Work . . . . . . . . . . . . . .

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2 Implementing Time-Constrained Applications on a Predictable MPSoc Sander Stuijk, Akash Kumar, Roel Jordans, and Henk Corporaal 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Application modeling and programming . . . . . . . . . . . . 2.3 Platform architecture . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Processing element . . . . . . . . . . . . . . . . . . . . 2.3.2 Network interface . . . . . . . . . . . . . . . . . . . . . 2.3.3 Interconnect . . . . . . . . . . . . . . . . . . . . . . . 2.4 Design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Platform generation . . . . . . . . . . . . . . . . . . . . . . . 2.6 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Throughput guarantees . . . . . . . . . . . . . . . . . 2.6.2 Designer effort . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Overhead . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SESAM Prototyping Solution Nicolas Ventroux, Tanguy Sassolas, Alexandre Guerre, Andriamisaina 3.1 Introduction . . . . . . . . . . . . . . . . . . . . 3.2 Existing work . . . . . . . . . . . . . . . . . . . 3.3 SESAM overview . . . . . . . . . . . . . . . . . 3.4 SESAM infrastructure . . . . . . . . . . . . . . . 3.4.1 Approximate-timed TLM . . . . . . . . . 3.4.2 Interconnections . . . . . . . . . . . . . . 3.4.3 ArchC . . . . . . . . . . . . . . . . . . . . 3.4.4 Instruction Set Simulators . . . . . . . . . 3.4.5 Traffic generators . . . . . . . . . . . . . . 3.4.6 MMU and TLBs . . . . . . . . . . . . . . 3.4.7 CLU . . . . . . . . . . . . . . . . . . . . . 3.4.8 Memory . . . . . . . . . . . . . . . . . . . 3.4.9 DMA . . . . . . . . . . . . . . . . . . . . 3.4.10 Control Manager . . . . . . . . . . . . . . 3.5 SESAM programming and execution models . . 3.5.1 Programming model . . . . . . . . . . . . 3.5.2 Execution models . . . . . . . . . . . . . . 3.5.3 Hardware Abstraction Layer . . . . . . . 3.6 SESAM debug . . . . . . . . . . . . . . . . . . .

32 34 35 38 40

43 44 46 50 51 52 53 54 57 59 60 61 61 62 63

and Caaliph . . . . . . . . . . . . . . . . . . .

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64 66 67 68 69 70 72 73 73 74 74 74 75 75 75 76 77 78 79

iii 3.6.1 GDB stub . . . . . . . . . . . . . . . . . . 3.6.2 Debug and task migration . . . . . . . . . 3.6.3 Specializing GDB’s functionalities . . . . 3.7 SESAM energy modeling . . . . . . . . . . . . . 3.7.1 PowerArchC . . . . . . . . . . . . . . . . 3.7.2 DVFS and DPM . . . . . . . . . . . . . . 3.7.3 Scheduling example . . . . . . . . . . . . 3.8 SESAM exploration . . . . . . . . . . . . . . . . 3.8.1 Dynamic parameters . . . . . . . . . . . . 3.8.2 Application parallelism exploration . . . . 3.8.3 Distributed simulations . . . . . . . . . . 3.9 Use case . . . . . . . . . . . . . . . . . . . . . . 3.9.1 SCMP overview . . . . . . . . . . . . . . . 3.9.2 Implemented applications . . . . . . . . . 3.10 Validation . . . . . . . . . . . . . . . . . . . . . 3.10.1 SESAM accuracy . . . . . . . . . . . . . . 3.10.2 SESAM simulation speed . . . . . . . . . 3.10.3 SESAM sizing example: NoC study . . . . 3.10.4 Performance study in SESAM . . . . . . . 3.10.5 Power management evaluation in SESAM 3.11 Conclusion . . . . . . . . . . . . . . . . . . . . .

II

Parallelism and Optimization

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80 81 83 83 84 86 86 88 89 90 93 94 95 96 98 98 99 99 100 101 104

107

4 Verified Multicore Parallelism using Atomic Verifiable Operations 109 Michal Dobrogost, Christopher Kumar Anand, and Wolfram Kahl 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.1.1 Novelty . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.1.2 Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.1.3 Chapter Organization . . . . . . . . . . . . . . . . . . 112 4.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.1 Map Modification Notation . . . . . . . . . . . . . . . 112 4.2.2 Groups . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.2.3 Disjoint Unions . . . . . . . . . . . . . . . . . . . . . . 114 4.3 Background and Previous Work . . . . . . . . . . . . . . . . 115 4.3.1 Concurrency Verification . . . . . . . . . . . . . . . . . 116 4.3.2 Motivating Example . . . . . . . . . . . . . . . . . . . 117 4.3.3 Strictly Forward Inspection of Partial Order . . . . . . 118 4.3.4 The Follows Map (Φ) . . . . . . . . . . . . . . . . . . 120 4.3.5 Φ Slices . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3.6 Discussion of the Follows Map (Φ) . . . . . . . . . . . 121 4.3.7 Merging Φ Slices to Strengthen our Partial Order . . . 123 4.3.8 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.3.9 Verification Step . . . . . . . . . . . . . . . . . . . . . 125

iv 4.4

4.5

4.6

4.7

4.8

4.9

The Loop AVOp . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Loop AVOp Indexing . . . . . . . . . . . . . . . . . . 4.4.2 Loop definition . . . . . . . . . . . . . . . . . . . . . . Efficient Verification of Looping Programs . . . . . . . . . . 4.5.1 Locally Sequential Loops . . . . . . . . . . . . . . . . 4.5.2 Bumping State to the Next Iteration via Λ . . . . . . 4.5.3 Loop Short Circuit Theorem . . . . . . . . . . . . . . 4.5.4 Verifying Nested Loops . . . . . . . . . . . . . . . . . 4.5.5 Verifier Run Time . . . . . . . . . . . . . . . . . . . . Rewritable Loops . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Motivating example . . . . . . . . . . . . . . . . . . . 4.6.2 The Rewrite Map: ρ . . . . . . . . . . . . . . . . . . . 4.6.3 Formulation of AVOps as Functions on the State . . . 4.6.4 Induced Rewrites and Rewriting AVOps . . . . . . . . 4.6.5 Short Circuit Theorem for Rewritable Loops . . . . . 4.6.6 Verifier Run Time on Rewritable Loops . . . . . . . . 4.6.7 Memory requirements . . . . . . . . . . . . . . . . . . Extension to Full AVOp Set . . . . . . . . . . . . . . . . . . 4.7.1 Extension of AVOp State and Hazard Checking . . . . 4.7.2 Extension of the Rewrite Map . . . . . . . . . . . . . 4.7.3 Extension of Loops for Accessing Global Memory . . . 4.7.4 Extension of Verification Algorithm . . . . . . . . . . Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 Restricted Global Memory Access for Verification . . . 4.8.2 Stronger Short Circuit Theorem for Rewritable Loops 4.8.3 Breaking up AVOp Streams to Increase AVOp Feed Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.4 Verifying the Verifier . . . . . . . . . . . . . . . . . . . 4.8.5 Modifications for Cached Memory Multicore Processors 4.8.6 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 4.8.7 Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . .

126 126 127 129 129 130 131 133 134 135 137 138 139 140 141 143 144 144 144 147 148 150 150 150 150 151 152 152 153 153 153

5 Accelerating Critical Section Execution with Multi-Core Architectures 155 M. Aater Suleman and Onur Mutlu 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.2 The Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3 Accelerated Critical Sections (ACS) . . . . . . . . . . . . . . 159 5.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.2 False Serialization . . . . . . . . . . . . . . . . . . . . 161 5.4 Trade-off Analysis: Why ACS Works . . . . . . . . . . . . . . 161 5.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.5.1 Performance at Optimal Number of Threads . . . . . 163

v 5.5.2

5.6 5.7

5.8

III

Performance when the Number of Threads equals the Number of Contexts . . . . . . . . . . . . . . . . . . . 5.5.3 Application Scalability . . . . . . . . . . . . . . . . . . 5.5.4 ACS on Symmetric CMP . . . . . . . . . . . . . . . . 5.5.5 ACS versus Techniques to hide critical section latency Contributions and Impact . . . . . . . . . . . . . . . . . . . . Related Previous Work . . . . . . . . . . . . . . . . . . . . . 5.7.1 Improving Locality of Shared Data and Locks . . . . . 5.7.2 Hiding the Latency of Critical Sections . . . . . . . . . 5.7.3 Asymmetric CMPs and CoreFusion . . . . . . . . . . . 5.7.4 Remote Procedure Calls . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Systems

164 164 166 166 167 169 169 169 169 170 170

171

6 TMbox: Hybrid Transactional Memory System Nehir Sonmez, Oriol Arcas, Osman S. Unsal, Adri´ an Cristal, and Satnam Singh 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 FPGAs for Architectural Investigation . . . . . . . . . 6.1.2 Transactional Memory . . . . . . . . . . . . . . . . . . 6.1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . 6.2 The TMbox Architecture . . . . . . . . . . . . . . . . . . . . 6.2.1 Interconnection . . . . . . . . . . . . . . . . . . . . . . 6.3 Hybrid TM Support for TMbox . . . . . . . . . . . . . . . . 6.3.1 Instruction Set Architecture Extensions . . . . . . . . 6.3.2 Bus Extensions . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Cache Extensions . . . . . . . . . . . . . . . . . . . . . 6.4 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . 6.4.1 Architectural Benefits and Drawbacks . . . . . . . . . 6.4.2 Experimental Results . . . . . . . . . . . . . . . . . . 6.5 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EM2 : A Scalable Shared Memory Architecture scale Multicores Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Srinivas Devadas 7.1 Background . . . . . . . . . . . . . . . . . . . . . 7.2 Migration-based Memory Coherence . . . . . . . . 7.2.1 Remote-access-only (RA) Architecture . . . 7.2.2 The Execution Migration Machine (EM2 ) . 7.2.3 Hybrid EM2 Architecture . . . . . . . . . . 7.2.4 Hardware-level Migration Framework . . . 7.2.5 Data Placement . . . . . . . . . . . . . . .

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174 174 176 176 177 178 180 182 182 183 185 185 186 187 190

for Large191 Cho, and . . . . . . .

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192 194 195 196 197 198 200

vi 7.3

7.4

7.5

7.6

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Analytical Models: Directory Coherence versus EM2 . . . . 7.3.1 Interconnect Traversal Costs . . . . . . . . . . . . . 7.3.2 Off-chip Memory Access Costs . . . . . . . . . . . . 7.3.3 EM2 Memory Access Latency . . . . . . . . . . . . . 7.3.4 Directory Coherence Memory Access Latency . . . . Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Architectural Simulation . . . . . . . . . . . . . . . . 7.4.2 On-chip Interconnect Model . . . . . . . . . . . . . . 7.4.3 Application Benchmarks . . . . . . . . . . . . . . . . 7.4.4 Directory-based Cache Coherence Baseline Selection 7.4.5 Remote-access NUCA Baseline Selection . . . . . . . 7.4.6 Cache Size Selection . . . . . . . . . . . . . . . . . . 7.4.7 Instruction Cache . . . . . . . . . . . . . . . . . . . 7.4.8 Area and Energy Estimation . . . . . . . . . . . . . Results and Analysis . . . . . . . . . . . . . . . . . . . . . 7.5.1 Advantages over Directory-based Cache Coherence . 7.5.2 Advantages over Traditional NUCA (RA) . . . . . . 7.5.3 Overall Area, Performance and Energy . . . . . . . . 7.5.4 Performance Scaling Potential for EM2 Designs . . . Related Work . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 Thread Migration . . . . . . . . . . . . . . . . . . . 7.6.2 Remote-access NUCA and Directory Coherence . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . .

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201 201 203 204 204 206 206 207 207 208 209 209 210 211 212 212 214 216 218 220 220 221 222

´ Cache-Aware Fair and Efficient Scheduling for CMPs 8 CAFE: Richard West, Puneet Zaroo, Carl A. Waldspurger, and Xiao Zhang 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Cache Occupancy Estimation . . . . . . . . . . . . . . . . . . 8.2.1 Basic Cache Model . . . . . . . . . . . . . . . . . . . . 8.2.2 Extended Cache Model for LRU Replacement Policies 8.2.3 Experiments . . . . . . . . . . . . . . . . . . . . . . . 8.3 Cache Utility Curves . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Curve Types . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Curve Generation . . . . . . . . . . . . . . . . . . . . 8.3.3 Experiments . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Cache-Aware Scheduling . . . . . . . . . . . . . . . . . . . . 8.4.1 Fair Scheduling . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Efficient Scheduling . . . . . . . . . . . . . . . . . . . 8.5 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Conclusions and Future Work . . . . . . . . . . . . . . . . .

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IV

257

Debugging

224 226 227 230 231 234 235 238 241 241 243 244 248 253 254

vii 9 Software Debugging Infrastructure for Multi-Core on-Chip ˇ ˇ c Bojan Mihajlović, Warren J. Gross, and Zeljko Zili´ 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 9.2 Software Debugging . . . . . . . . . . . . . . . . . . 9.2.1 Debugger Programs . . . . . . . . . . . . . . 9.2.2 Fault types . . . . . . . . . . . . . . . . . . . 9.2.3 Multi-threaded Software . . . . . . . . . . . . 9.3 Traditional Debugging Methods . . . . . . . . . . . 9.3.1 Software Instrumentation . . . . . . . . . . . 9.3.2 Scan-chain Methods . . . . . . . . . . . . . . 9.3.3 In-Circuit Emulation . . . . . . . . . . . . . . 9.4 Debugging with Trace Generation . . . . . . . . . . 9.4.1 Triggers . . . . . . . . . . . . . . . . . . . . . 9.4.2 Trace Ordering . . . . . . . . . . . . . . . . . 9.4.3 Debug Interface . . . . . . . . . . . . . . . . . 9.4.4 Data Volume . . . . . . . . . . . . . . . . . . 9.5 Generalized Debugging Procedure . . . . . . . . . . 9.6 Trace Compression Scheme . . . . . . . . . . . . . . 9.6.1 Overview . . . . . . . . . . . . . . . . . . . . 9.6.2 Consecutive Address Elimination . . . . . . . 9.6.3 Finite Context Method . . . . . . . . . . . . 9.6.4 Move-to-Front and Address Encoding . . . . 9.6.5 Data Stream Serializer . . . . . . . . . . . . . 9.6.6 Run-length and Prefix Encoding . . . . . . . 9.6.7 Lempel-Ziv Encoding . . . . . . . . . . . . . 9.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . 9.8 Glossary . . . . . . . . . . . . . . . . . . . . . . . .

V

Networks-on-Chip

Systems259 . . . . . . . . . . . . . . . . . . . . . . . . .

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260 261 261 262 263 264 264 265 266 268 269 270 271 271 273 274 275 276 277 278 280 281 282 283 284

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10 On Chip Interconnects For Multi-core Architectures 287 Prasun Ghosal and Soumyajit Poddar 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.2 Evolution of Interconnects for Multi-core Architectures . . . 288 10.2.1 More than Moore Trends: A New Perspective . . . . . 289 10.2.2 From Single Bus Based to Network-on-Chip Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.2.3 On Chip Applications . . . . . . . . . . . . . . . . . . 292 10.3 Emerging Technologies for Interconnections . . . . . . . . . . 293 10.3.1 Three Dimensional Interconnects . . . . . . . . . . . . 293 10.3.2 Photonic Interconnects . . . . . . . . . . . . . . . . . . 294 10.3.3 Wireless Interconnect Technology . . . . . . . . . . . . 297 10.3.4 RF Waveguide Interconnects . . . . . . . . . . . . . . 298 10.3.5 Carbon Nanotubes (CNT) . . . . . . . . . . . . . . . . 299

viii 10.4 Conclusion and Future Research Directions . . . . . . . . . . 11 Routing in Multi-core NoC Prasun Ghosal and Tuhin Subhra Das 11.1 Introduction . . . . . . . . . . . . . . . . . . . 11.2 Routing Topologies in NoC . . . . . . . . . . . 11.2.1 Topologies in 2D NoCs . . . . . . . . . . 11.2.2 Topologies in 3D NoCs . . . . . . . . . . 11.2.3 Topologies in Optical or Photonic NoCs 11.2.4 Topologies in Wireless NoCs . . . . . . 11.3 Design of Router . . . . . . . . . . . . . . . . . 11.3.1 Channel . . . . . . . . . . . . . . . . . . 11.3.2 Virtual Channel . . . . . . . . . . . . . 11.3.3 Buffer Organization . . . . . . . . . . . 11.4 Switching Techniques . . . . . . . . . . . . . . 11.4.1 Circuit switching . . . . . . . . . . . . . 11.4.2 Packet Switching . . . . . . . . . . . . . 11.5 Routing Flow Control . . . . . . . . . . . . . . 11.5.1 Store-and-Forward . . . . . . . . . . . . 11.5.2 Virtual Cut-Through . . . . . . . . . . . 11.5.3 Wormhole . . . . . . . . . . . . . . . . . 11.6 Traffic Patterns . . . . . . . . . . . . . . . . . 11.6.1 Synthetic Traffic . . . . . . . . . . . . . 11.6.2 Realistic Traffic . . . . . . . . . . . . . . 11.7 Routing Algorithms . . . . . . . . . . . . . . . 11.7.1 Oblivious routing . . . . . . . . . . . . . 11.7.2 Adaptive routing . . . . . . . . . . . . . 11.8 Problems of Routing in NoC . . . . . . . . . . 11.9 Emerging Techniques in NoC Routing . . . . . 11.9.1 Routing in Optical NoC . . . . . . . . . 11.9.2 Wireless NoC . . . . . . . . . . . . . . . 11.10Conclusion . . . . . . . . . . . . . . . . . . . .

300 301

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12 Efficient Topologies for 3-D Network-on-Chip Mohammad Ayoub Khan and Abdul Quaiyum Ansari 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Classification of Network Topologies . . . . . . 12.1.2 Topology Properties . . . . . . . . . . . . . . . 12.1.3 Performance Evaluation Parameters . . . . . . 12.1.4 Basic 3-D Topologies . . . . . . . . . . . . . . . 12.1.5 Power Consumption Issues in 3-D Topologies . 12.2 Related Work . . . . . . . . . . . . . . . . . . . . . . 12.3 Binary Search Tree based Ring Topology . . . . . . . 12.3.1 Number of nodes (N ) at lth level . . . . . . . . 12.3.2 Average Degree (d) of the Network at lth level

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302 303 304 308 311 314 318 318 319 319 319 320 320 321 321 321 321 321 322 323 323 323 327 330 331 331 333 333 335

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336 337 337 339 341 342 343 344 345 347

ix

12.4 12.5 12.6 12.7

12.3.3 Diameter (D) of Level l network Layout and Implementation . . . . . . Discussion and Analysis . . . . . . . . . Conclusions . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . .

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348 349 350 351 353

13 Network-on-Chip Performance Evaluation using an Analytical Method 355 Sahar Foroutan, Abbas Sheibanyrad, and Frédéric Pétrot 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 13.2 Network-on-Chip Concepts . . . . . . . . . . . . . . . . . . . 357 13.2.1 Architectural Parameters . . . . . . . . . . . . . . . . 358 13.2.2 Layered Concept . . . . . . . . . . . . . . . . . . . . . 361 13.2.3 Levels-of-Abstraction . . . . . . . . . . . . . . . . . . . 363 13.2.4 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 366 13.2.5 Parameters Addressed in NoC Performance Evaluation 375 13.3 The State-of-the-Art in NoC Performance Evaluation . . . . 378 13.3.1 Simulation-Based Methods . . . . . . . . . . . . . . . 378 13.3.2 Analytical Methods . . . . . . . . . . . . . . . . . . . 379 13.4 An Analytical Performance Evaluation Method . . . . . . . . 389 13.4.1 The Method . . . . . . . . . . . . . . . . . . . . . . . 391 13.4.2 Validation of the Method . . . . . . . . . . . . . . . . 403 13.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Bibliography

411

List of Figures

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12

MORA-C++ Tool Chain . . . . . . . . . . . . . . . . . . . . MORA Reconfigurable Cell (RC) . . . . . . . . . . . . . . . Block Diagram of the MORA PE . . . . . . . . . . . . . . . MORA Control Unit Flow Chart . . . . . . . . . . . . . . . MORA Address Generator . . . . . . . . . . . . . . . . . . . Reconfigurable Cell Floating-Point Core . . . . . . . . . . . Vector Support for RC Architecture . . . . . . . . . . . . . . Shared Memory Access Interface Architecture . . . . . . . . ADG diagram for the DCT small Algorithm . . . . . . . . . Slice Count for Benchmark Algorithms . . . . . . . . . . . . Effect of vectorization on Slice/BRAM Counts . . . . . . . . Throughput Versus Number of Lanes for 8-bit Benchmarks .

7 8 9 10 11 28 30 33 34 35 36 37

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

SDF3/MAMPS design flow . . . . . . . . . . . . . . . . . . Example SDFG and implementation of actor P . . . . . . . MAMPS platform architecture . . . . . . . . . . . . . . . . . MAMPS scheduling code for processing element . . . . . . . Overview of the SDF3 mapping flow . . . . . . . . . . . . . Dataflow model for interconnect communication in MAMPS Two tile MAMPS platform in XPS . . . . . . . . . . . . . . The SDF graph for the MJPEG decoder . . . . . . . . . . . Measured and guaranteed worst-case throughput . . . . . .

45 47 50 51 55 56 58 59 60

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13

SESAM overview . . . . . . . . . . . . . . . . . . . . . . . . SESAM infrastructure . . . . . . . . . . . . . . . . . . . . . Timed TLM versus Approximate-timed TLM . . . . . . . . Routing example for a Mesh network . . . . . . . . . . . . . SESAM programming model . . . . . . . . . . . . . . . . . . Structure of the debugging solution implemented in SESAM PowerArchC: Power model generation flow . . . . . . . . . . PowerArchC: Power-aware ISS architecture generation . . . DPM and DVFS techniques timing issues . . . . . . . . . . Summary of buffer monitors and scheduling implications . . SESAM exploration tool and environment . . . . . . . . . . SESAM AGP toolchain . . . . . . . . . . . . . . . . . . . . . Example of automatic parallelization . . . . . . . . . . . . .

68 69 70 71 76 80 84 85 87 88 90 91 92 xi

xii

Multicore Technology: Architecture, Reconfiguration and Modeling 3.14 3.15 3.16 3.17 3.18 3.19 3.20

Parallelization of SESAM simulations. . . . . . . . . . . . . SCMP architecture . . . . . . . . . . . . . . . . . . . . . . . Evaluation of SESAM accuracy . . . . . . . . . . . . . . . . SESAM simulation speed . . . . . . . . . . . . . . . . . . . . Network performance results . . . . . . . . . . . . . . . . . . SCMP performance profiling with a variable number of PE . Power Aware scheduling results with the WCDMA application

94 95 98 99 100 102 103

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16

Locally sequential program . . . . . . . . . . . . . . . . Φ is defined for other cores . . . . . . . . . . . . . . . . . Visualization of Φ-dependency. . . . . . . . . . . . . . . Φ map at instruction SendSignal s3 → c3 . . . . . . . . . Φ map at instruction W aitSignal s3 . . . . . . . . . . . . Example using the Loop AVOp . . . . . . . . . . . . . . Example of an unrolled loop . . . . . . . . . . . . . . . . Example with nested loops . . . . . . . . . . . . . . . . . Non-rewritable loop example . . . . . . . . . . . . . . . . Motivating example for loop rewriting. . . . . . . . . . . Motivating example unrolled. . . . . . . . . . . . . . . . Effects of an inner loop . . . . . . . . . . . . . . . . . . . Loop with rewriting verified without fully unrolling. . . . Rewritable Loop unrolled into a loop without a rewrite. Defining diagram for projected rewrite . . . . . . . . . . Accessing global memory . . . . . . . . . . . . . . . . . .

119 121 122 122 123 128 128 129 136 137 138 141 142 142 148 149

5.1

5.7

Amdahl’s serial part, parallel part, and critical section in a multi-threaded 15-puzzle kernel . . . . . . . . . . . . . . . . Accelerated Critical Sections (ACS). . . . . . . . . . . . . . Source code and its execution: baseline and ACS . . . . . . Execution time when number of threads is optimal for each application. . . . . . . . . . . . . . . . . . . . . . . . . . . . Speedup over a single small core . . . . . . . . . . . . . . . . Execution time when number of threads equals number of contexts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACS versus TLR performance. . . . . . . . . . . . . . . . .

6.1 6.2 6.3 6.4 6.5 6.6

An 8-core TMbox infrastructure . . . . . . TMbox MIPS assembly for atomic{a++} Cache state diagram. . . . . . . . . . . . . Eigenbench results on 1–16 cores. . . . . . SSCA2 benchmark results on 1–16 cores. . Intruder benchmark results on 1–16 cores.

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179 183 184 188 188 189

7.1 7.2 7.3

Hybrid migration/remote-access architecture . . . . . . . . . Efficient execution migration in a five-stage CPU core . . . Average memory latency costs . . . . . . . . . . . . . . . . .

198 199 202

5.2 5.3 5.4 5.5 5.6

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158 160 160 163 165 166 167

List of Figures

xiii

7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13

Parallel completion time under different DirCC protocols. . Cache hierarchy miss rates at various cache sizes . . . . . . The performance of DirCC (under a MOESI protocol) . . . Cache hierarchy miss rates for EM2 and RA designs . . . . . Non-local memory accesses in RA baseline . . . . . . . . . . Per-benchmark core miss rates . . . . . . . . . . . . . . . . . Core miss rates handled by remote accesses . . . . . . . . . The performance of EM2 and RA variants relative to DirCC Dynamic energy usage for all EM2 and RA variants . . . . . EM2 performance scales with network bandwidth. . . . . . .

209 210 213 214 215 216 217 218 219 220

8.1 8.2 8.3 8.4 8.5

232 233 234 235

8.10 8.11 8.12 8.13

Accuracy of basic Estimate-M method on dual-core system . Occupancy and estimation error . . . . . . . . . . . . . . . . Two pairs of co-runners in dual-core systems . . . . . . . . . Cache occupancy for four co-runners in a quad-core system Occupancy estimation for an over-committed quad-core system (Part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . Occupancy estimation for an over-committed quad-core system (Part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . Fine-grained occupancy estimation in over-committed quadcore system. . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of memory bandwidth contention on the MPKC missrate curve for the SPEC CPU2000 mcf workload. . . . . . . Miss-ratio curves (MRCs) for various SPEC CPU workloads, ´ versus offline by page-coloring. . . obtained online by CAFE MRC for mcf with different co-runners. . . . . . . . . . . . Vtime compensation. . . . . . . . . . . . . . . . . . . . . . . Cache divvying occupancy prediction. . . . . . . . . . . . . Co-runner placement. . . . . . . . . . . . . . . . . . . . . . .

242 243 248 251 252

9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9

Remote Debugging Scenario – Software View . . . . . . . Debugging multiple cores through IEEE 1149.1 (JTAG) . Debugging a single-core SoC through In-Circuit Emulation Debugging through Trace Generation and ICE . . . . . . . Example: Creating a tracepoint in the GDB debugger . . . Trace-based Debugging Scenario . . . . . . . . . . . . . . . Trace Compression Scheme . . . . . . . . . . . . . . . . . . Finite Context Method . . . . . . . . . . . . . . . . . . . . Huffman Tree for Prefix Encoding . . . . . . . . . . . . . .

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262 266 267 269 270 276 277 279 282

10.1 10.2 10.3

Side view of multi-path interconnect . . . . . . . . . . . . . Network on chip concept . . . . . . . . . . . . . . . . . . . . Reduction of interconnect length from 2D ICs to 3D ICs . .

289 291 294

8.6 8.7 8.8 8.9

236 237 237 239

xiv

Multicore Technology: Architecture, Reconfiguration and Modeling 10.4

10.5 10.6 10.7 10.8

10.9

11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 11.23 11.24 11.25 11.26 11.27 11.28 11.29 11.30

Schematic representation of TSV first, middle, and last processes (The International Technology Roadmap for Semiconductors 2009 for Interconnects 2009) . . . . . . . . . . . . . Schematic of photonic interconnect using micro ring resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A simple schematic of a Micro ring resonator. . . . . . . . . A photonic switch in the left side and a non-blocking photonic router on the right side (Wang et al. 2008) . . . . . . . . . . Torus topology: (a) the photonic network (with the routers shown as yellow boxes), and (b) the electrical network (with the gateways shown as pink boxes) (Wang et al. 2008) . . . The concentrated mesh topology and the wireless routers shown from left to right respectively . . . . . . . . . . . . . Factors affecting the performance of a NoC . . . . Mesh topology . . . . . . . . . . . . . . . . . . . . . Torus . . . . . . . . . . . . . . . . . . . . . . . . . . Folded Torus . . . . . . . . . . . . . . . . . . . . . Octagon . . . . . . . . . . . . . . . . . . . . . . . . Star . . . . . . . . . . . . . . . . . . . . . . . . . . Binary tree . . . . . . . . . . . . . . . . . . . . . . Butterfly . . . . . . . . . . . . . . . . . . . . . . . . Butterfly fat tree . . . . . . . . . . . . . . . . . . . Honeycomb . . . . . . . . . . . . . . . . . . . . . . Mesh-of-tree . . . . . . . . . . . . . . . . . . . . . . Diametric 2D mesh . . . . . . . . . . . . . . . . . . Diametric 2D mesh of tree . . . . . . . . . . . . . . A 9 × 9 Structural Diametrical 2D Mesh . . . . . . A 9×9 Star Type Topology . . . . . . . . . . . . . Custom mesh topology . . . . . . . . . . . . . . . . 3D irregular mesh . . . . . . . . . . . . . . . . . . . Dragonfly topology . . . . . . . . . . . . . . . . . . Wireless mesh . . . . . . . . . . . . . . . . . . . . . MORFIC (Mesh Overlaid with RF Inter Connect) . Hybrid ring . . . . . . . . . . . . . . . . . . . . . . Hybrid star . . . . . . . . . . . . . . . . . . . . . . Hybrid tree . . . . . . . . . . . . . . . . . . . . . . Hybrid irregular topology . . . . . . . . . . . . . . A typical router architecture . . . . . . . . . . . . . Router Data Flow . . . . . . . . . . . . . . . . . . . Different Routing Policies . . . . . . . . . . . . . . West First Turn . . . . . . . . . . . . . . . . . . . . North Last Turn . . . . . . . . . . . . . . . . . . . North First Turn . . . . . . . . . . . . . . . . . . .

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295 295 296 297

298 299 303 304 304 305 305 305 305 306 306 306 307 308 310 311 312 313 313 314 316 317 317 317 318 318 319 320 324 328 328 328

List of Figures 12.1 12.2 12.3 12.4 12.5 12.6

Classification of interconnection networks . . . . . . . . . . Basic Network Topologies . . . . . . . . . . . . . . . . . . . Diameter in a connected graph . . . . . . . . . . . . . . . . 3-D Mesh and Torus Topologies (Khan and Ansari 2011c) . Binary Tree (Khan and Ansari 2011b) . . . . . . . . . . . . Proposed Topology with different levels (l = 1, l = 2, and l = 3) (Khan and Ansari 2011b) . . . . . . . . . . . . . . . . 12.7 Ring Based Tree Topology (Khan and Ansari 2011b) . . . . 12.8 3-D Tree-Mesh . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 Layout of the proposed topology (Khan and Ansari 2011b) . 12.10 Number of nodes in level l (Khan and Ansari 2011b) . . . . 12.11 Degree and Diameter Analysis of the proposed topology (Khan and Ansari 2011b) . . . . . . . . . . . . . . . . . . . 13.1 13.2 13.3 13.4 13.5 13.6 13.7

13.8 13.9

13.10 13.11 13.12 13.13

13.14 13.15 13.16

Operational Layered Concept of a NoC-based SoC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The relation between NoC layers and levels of abstraction from a performance evaluation viewpoint . . . . . . . . . . . A generic design flow for a NoC-based system . . . . . . . . Performance requirements versus performance analysis . . . Optimization loop: architectural exploration and mapping exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . At each router of the path, disrupting packets appear probabilistically in front of the tagged packet . . . . . . . . . . . . Dependency trees corresponding to the latency (a) ‘core to south’, and (b) ‘core to east’ of r3,4 in a 6 × 5 2D-mesh NoC with x-first routing algorithm . . . . . . . . . . . . . . . . . Router delay model related to a 2D-mesh NoC . . . . . . . . Buffer occupancy caused by Pj at time instant (a) t, and (b) t + 3, when Pj is transferred and Pi can be written into the buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The average number of accumulated flits in the output buffer at the arrival of Pi when there is no header contention . . . The order of delay component computation in one iteration Iterative computation for inputs {1, 2, 3, 4} of router r . . . Latency/load curves for the path r2,4 → r4,2 with buffer lengths in flits as indicated and uniform traffic (path latency excludes the source queue waiting time) . . . . . . . . . . . Latency/load curves for the path r2,4 → r4,2 with buffer lengths in flits as indicated and localised traffic . . . . . . . Analytical method for different buffer lengths and 0.01 offered load steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . The average utilization of buffer r3,4 → r4,4 under two traffic distributions . . . . . . . . . . . . . . . . . . . . . . . . . . .

xv 338 339 340 341 344 345 345 346 350 351 352

363 365 367 370 375 392

394 395

399 400 401 402

404 405 406 407

List of Tables

1.1

1.6

Utilization results of Single Precision Floating Point Core on Virtex 4 LX200 . . . . . . . . . . . . . . . . . . . . . . . . . Latency of Shared Memory Interface Modules . . . . . . . . Benchmark Implementation Results (no Vectorization) . . . Benchmark Throughput Results for a Single DMA Channel without RC Vectorization . . . . . . . . . . . . . . . . . . . Benchmark Throughput Results with Multiple DMA Channels and RC Vectorization . . . . . . . . . . . . . . . . . . . DCT Benchmark Throughput Comparison . . . . . . . . . .

2.1

Designer effort . . . . . . . . . . . . . . . . . . . . . . . . . .

61

3.1 3.2 3.3

Hardware Abstraction Layer of SESAM . . . . . . . . . . . Basic remote protocol support commands . . . . . . . . . . Additional remote protocol commands for fast debugging . .

79 81 81

5.1

Best number of threads for each configuration . . . . . . . .

164

6.1 6.2 6.3

LUT occupation of components of the Honeycomb core . . . HTM instructions for TMbox . . . . . . . . . . . . . . . . . TM Benchmarks Used . . . . . . . . . . . . . . . . . . . . .

180 181 185

7.1 7.2 7.3 7.4

Various parameter settings for the analytical cost model the ocean contiguous benchmark . . . . . . . . . . . System configurations used . . . . . . . . . . . . . . . . . Area and energy estimates . . . . . . . . . . . . . . . . . Synthetic benchmark settings . . . . . . . . . . . . . . .

203 206 211 212

9.1 9.2 9.3

Example of CAE with 16-bit Addresses . . . . . . . . . . . . 278 Address Encoding Scheme . . . . . . . . . . . . . . . . . . . 280 Example of Differential Address Encoding – 16-bit Addresses 281

11.1 11.2 11.3

Relative comparison of 2D irregular topologies . . . . . . . . Comparison of optical network topologies . . . . . . . . . . The Wavelength Assignment of 4-WRON . . . . . . . . . . .

309 315 333

12.1

Classification of NoC Topology (Khan and Ansari 2011b) . .

337

1.2 1.3 1.4 1.5

for . . . . . . . .

29 31 35 38 38 39

xvii

xviii 12.2

13.1 13.2 13.3

Multicore Technology: Architecture, Reconfiguration and Modeling Analysis of Network Parameters for Base Module (Khan and Ansari 2011b) . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of Analytical Methods . . . . . . . . . . . . Parameters of the Analytical Performance Evaluation Method Presented in Section 13.4 . . . . . . . . . . . . . . . . . . . . Comparing simulation and analytical tool runtimes . . . . .

350 388 391 408

Contributors

Christopher Kumar Anand Department of Computing and Software McMaster University, Hamilton, Ontario, Canada Abdul Quaiyum Ansari Jamia Millia Islamia New Delhi, India Oriol Arcas Barcelona Supercomputing Center Universitat Politècnica de Catalunya, Spain Caaliph Andriamisaina CEA LIST Gif-sur-Yvette, France Sai Rahul Chalamalasetti Department of Electrical and Computer Engineering University of Massachusetts, Lowell MA, USA Henk Corporaal Department of Electrical Engineering Eindhoven University of Technology, The Netherlands Myong Hyon Cho Massachusetts Institute of Technology Cambridge, MA, USA Adri´ an Cristal Barcelona Supercomputing Center

CSIC - Spanish National Research Council, Spain Tuhin Subhra Das Department of Information Technology Bengal Engineering and Science University, Shibpur, India Srinivas Devadas Massachusetts Institute of Technology Cambridge, MA, USA Michal Dobrogost Department of Computing and Software McMaster University, Hamilton, Ontario, Canada Sahar Foroutan Laboratoire TIMA Grenoble, France Prasun Ghosal Department of Information Technology Bengal Engineering and Science University, Shibpur, India Warren J. Gross Department of Electrical & Computer Engineering McGill University, Montreal, Canada Alexandre Guerre Embedded Computing Lab CEA LIST, Gif-sur-Yvette, France xxv

xxvi


Roel Jordans Department of Electrical Engineering Eindhoven University of Technology, The Netherlands Wolfram Kahl Department of Computing and Software McMaster University, Hamilton, Ontario, Canada Mohammad Ayoub Khan Center for Development of Advanced Computing Noida, India Omer Khan University of Connecticut Storrs, CT, USA Akash Kumar Department of Electrical and Computer Engineering National University of Singapore, Singapore Mieszko Lis Massachusetts Institute of Technology Cambridge, MA, USA Martin Margala Department of Electrical and Computer Engineering University of Massachusetts, Lowell MA, USA Bojan Mihajlovi´ c Department of Electrical & Computer Engineering McGill University, Montreal, Canada Onur Mutlu Department of Electrical and Computer Engineering Carnegie Mellon University, Pittsburgh, PA, USA

Frederic P´ etrot Laboratoire TIMA Grenoble, France Soumyajit Poddar School of VLSI Technology Bengal Engineering and Science University, Shibpur, India Tanguy Sassolas Embedded Computing Lab CEA LIST, Gif-sur-Yvette, France Hamed Sheibanyrad Laboratoire TIMA Grenoble, France Keun Sup Shim Massachusetts Institute of Technology Cambridge, MA, USA Satnam Singh Google, Inc. Mountain View, CA, USA Nehir Sonmez Barcelona Supercomputing Center Universitat Politècnica de Catalunya, Spain Sander Stuijk Department of Electrical Engineering Eindhoven University of Technology, The Netherlands M. Aater Suleman Department of Electrical and Computer Engineering The University of Texas at Austin, Austin, TX Osman S. Unsal Barcelona Supercomputing Center Universitat Politècnica de Catalunya, Spain

Contributors Wim Vanderbauwhede School of Computing Science University of Glasgow, Scotland Carl A. Waldspurger Formerly at VMware Inc. Palo Alto, CA, USA

xxvii Puneet Zaroo VMware Inc. Palo Alto, CA, USA ˇ ˇ c Zeljko Zili´ Department of Electrical & Computer Engineering

Richard West McGill University, Montreal, Canada Department of Computer Science Boston University, Boston, MA, USA Xiao Zhang Nicolas Ventroux Google, Inc. Embedded Computing Lab CEA LIST, Gif-sur-Yvette, France Mountain View, CA, USA

Part I

Architecture and Design Flow

Part II

Parallelism and Optimization

Part III

Memory Systems

Part IV

Debugging

Part V

Networks-on-Chip

12 Efficient Topologies for 3-D Network-on-Chip Mohammad Ayoub Khan Center for Development of Advanced Computing (C-DAC), Ministry of Communications and IT., Govt. of India B-30, Sector 62, Noida, UP, INDIA Abdul Quaiyum Ansari Department of Electrical Engineering Jamia Millia Islamia (Central University) New Delhi, INDIA

CONTENTS 12.1

12.2 12.3

12.4 12.5 12.6 12.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Classification of Network Topologies . . . . . . . . . . . . . . . . . . . . 12.1.2 Topology Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Performance Evaluation Parameters . . . . . . . . . . . . . . . . . . . . 12.1.4 Basic 3-D Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Power Consumption Issues in 3-D Topologies . . . . . . . . . . . Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Search Tree based Ring Topology . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Number of nodes (N ) at lth level . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 Average Degree (d) of the Network at lth level . . . . . . . . . 12.3.3 Diameter (D) of Level l network . . . . . . . . . . . . . . . . . . . . . . . . Layout and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discussion and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

336 337 337 339 341 342 343 344 345 347 348 349 349 350 353

The Network-on-Chip (NoC) represents a relatively new communication paradigm for increasingly complex on-chip networks. The NoC provides techniques for generic on-chip interconnection network (IN) realized by routers that connect processing elements (PEs) like ASICs, FPGAs, memories, IP cores etc. To reduce the latency and wire length we need an efficient interconnection architecture. Performance of the network is measured in terms of throughput. The throughput and efficiency of an interconnect depends on the network parameters for a given topology. Therefore, the topology of any 335

336


communication network has an important role to play for efficient design. The performance of an interconnection architecture depends on degree and diameter. The cost of an interconnection architecture can be defined as a value of the degree × diameter. Three dimensional (3-D) integrated circuits offer a low interconnect latency and area efficient solution for NoC. The 3-D arrangement offers opportunities for new circuit architectures based on the geometric capacity that provides greater numbers of interconnections among multi-layer active circuits. The 3-D NoC can reduce significant amounts of wire length for local and global interconnects. This chapter investigates 3-D topologies for NoC application. Finally, the chapter considers a new design of efficient topology based on ring structures. We have obtained the degree n , while the diameter of a topology is obof proposed topology as 6×(22n −1)−4 −1 tained as D = 1 + 2 × (n − 1). The degree of the proposed topology is 25% less than the torus along with a drastic reduction in the diameter. The layout of the proposed topology could be easily extended to a 3-D NoC architecture by adding a few extra links.

12.1

Introduction

A Network-on-Chip (NoC) can be defined as a communication paradigm that uses multiple processors on a single-chip. The NoC paradigm represents a promising solution for forthcoming complex embedded systems and multimedia applications. The International Technology Roadmap for Semiconductors estimates that NoCs will soon contain billions of transistors running at speeds of many GHz (line-rate), operating below 1 V (Khan and Ansari 2011a). A typical NoC application consists of multiple storage components (memory cores) and processing elements, such as general-purpose CPUs, specialized cores and embedded hardware connected together over a complex communication architecture. The NoC technology has replaced traditional bus architecture with a low-cost point-to-point and packet-based architecture. The NoC solution incorporates a layered network protocol stack analogous to the open system interconnection (OSI) model. The performance of the network is measured in terms of throughput (Abuelrub 2008). The throughput and efficiency of interconnect depends on network parameters of the topology. We can formally define topology as a physical interconnection of the routing elements (R) by the communication channels (Khan and Ansari 2011b). This may be represented by a network graph G = (R, C), where routing elements are the vertices and channels the edges of the graph. R and C are described in equation (12.1) and (12.2) (Khan and Ansari 2011b). R ∈ {r1 , r2 , r3 . . . rn }

(12.1)

C ∈ {c1 , c2 , c3 . . . cn }

(12.2)

Efficient Topologies for 3-D Network-on-Chip

337

TABLE 12.1 Classification of NoC Topology (Khan and Ansari 2011b) Direct Indirect Orthogonal (Mesh and Torus, Tree) Crossbar switch fabric Cube-Connected-Cycles (CCC) Fully-Connected Network Octagon Omega 4-Cube Delta Butterfly Fat-tree Topology

12.1.1

Classification of Network Topologies

The topology of a network determines possible and efficient protocol regulations implemented by routing elements. The topology of a NoC affects the scalability, performance, power consumption, area and complexity of the routing elements (Khan and Ansari 2011b). The NoC topologies can be classified broadly in two categories viz. direct, indirect as shown in Table 12.1 (Khan and Ansari 2011b). In a direct network, the routing element is directly connected to a limited number of neighboring routing elements using a network interface (NI) (Khan and Ansari 2011b). The NI also connects to IP cores. Each routing element performs routing as well as arbitration. The IP element connected to the routing element injects the messages into the network through an injection channel and removes incoming messages through an ejection channel. The injected messages compete with the messages that pass through the routing element for the use of output channels (Khan and Ansari 2011b).

12.1.2

Topology Properties

Interconnection networks can be static, dynamic or hybrid in nature as shown in Figure 12.1. Hybrid networks are those interconnections which have complicated structures such as hierarchical or hyper-graph topologies. In the following section we will present two network families of static and dynamic networks. Figure 12.1 shows the overall classification of interconnection networks. In a static interconnection network, links among different nodes of the system are considered as passive. Thus each node is directly connected to a small subset of nodes by interconnecting links. Each node performs both routing and computations. Here, we present some important properties of topologies other than node degree and diameter. Regularity A network is regular when all the nodes have the same degree.

338

Multicore Technology: Architecture, Reconfiguration and Modeling 2D mesh 3D mesh Torus (k-ary-n-cube)

Mesh Orthogonal topology Direct

Hypercube Other topologies: tree, graph, ring etc.

Interconnection Networks

Crossbar Regular topology Indire ct

Blocking Multista ge

1D unidirectional torus 2D bidirectional torus 3D bidirectional torus

Unidirectional MIN’s Bidirectional MIN’s

Non-blocking

Irregular topology Multiple backplane buses Hybrid

Hierarchical network

Cluster based network

Hypergraph topologies: hypermesh, hyperbus, graph, ring etc.

There are errors in the figure, e.g. Indire and Multista where part of a word has been cutoff. Please supply a new corrected version. FIGURE 12.1 Classification of interconnection networks Symmetry A network is symmetric when it looks the same from each node’s perspective. Orthogonal property A network is orthogonal if the nodes and interconnecting links can be arranged in n dimensions such that the link is placed in exactly one dimension. In a weakly orthogonal topology, some nodes may not have any link in some dimensions. In static networks, the paths for message transmission are selected by a routing algorithm. The switching mechanism determines how inputs are connected to outputs in a node. All the existing switching techniques can also be used in direct networks. As compared to static networks, in which the interconnection links between the nodes are passive, the linking configuration in a dynamic network is a function of the states in the switching elements (SEs). In layman’s terms, the paths between the graph nodes of a dynamic network changes with the change


339

FIGURE 12.2 Basic Network Topologies in the states of the switching elements. The dynamic networks are built using crossbars(especially of size 2 × 2). The dynamic network may consist of single stage or multiple intermediate stages for switching. In an indirect network, the routing elements (switches) are connected to one or many intermediate routing elements. These intermediate nodes are responsible for routing and arbitration. These networks are sometimes referred to as multistage interconnect networks (MIN). A broad classification of NoC topology is shown in Table 12.1.

12.1.3

Performance Evaluation Parameters

Network topologies may be evaluated by the cost (size, degree, diameter and bisection width) and performance measures (Khan and Ansari 2011b). Size The size of a network may be defined as the number of vertices in the graph. Here, we will define some of the basic terminology of performance evaluation parameters (Khan and Ansari 2011b). S(G) = |R|

(12.3)

Degree The node degree is defined as the maximum number of physical links

340

Multicore Technology: Architecture, Reconfiguration and Modeling emanating from a node. The degree of the network may be defined as follows (Khan and Ansari 2011b): n X

Degree(ri ), ∀ri ∈ R

(12.4)

k=1

Diameter The diameter of a network is the maximum inter-node distance, i.e., the maximum distance between any two points in G where distance is the shortest path between (ri , rj ). This should be relatively small if network latency is to be minimized. The diameter is more important with store-and-forward routing than with wormhole routing (Parhami 1999). Consider a connected graph G, in Figure 12.3, d(A, E) = 2 and Diam(G) = 3. Therefore, we can define diameter as follows in the equation (12.5) (Khan and Ansari 2011b). Diameter(G) = max(d(ri , rj ))

(12.5)

FIGURE 12.3 Diameter in a connected graph

Bisection width The Bisection Width (BW ) of a network is defined as the minimum number of channels or links that must be removed to partition the network into two equal size disconnected networks. This is important when nodes communicate with each other in a random fashion. A small bisection width limits the rate of data transfer between the two halves of the network. This may affect performance of communication-intensive algorithms in SoC. Number of edges (Degree) This represents the number of communication ports (edges) required at each node (processing elements). The degree


341

should be a constant independent of network size if the architecture is to be readily scalable to larger sizes (Parhami 1999). The node degree has a direct effect on the cost of network. Channel Width The number of bits that can be sent simultaneously over a communication channel or link. Sometimes, this is loosely defined as the number of wires in the communication channel or link. Channel Rate This defines the peak rate at which a single wire can deliver bits (Khan and Ansari 2011b). Channel Bandwidth This defines the peak rate at which a communication channel or link can deliver bits (Khan and Ansari 2011b). Cost of Network This defines as total number of communication links (Khan and Ansari 2011b).

12.1.4

Basic 3-D Topologies

FIGURE 12.4 3-D Mesh and Torus Topologies (Khan and Ansari 2011c) Various new topologies have been explored to implement 3-D NoC. Some of these are based on basic topologies like mesh and torus that are extensively used in 2-D designs. In a 3-D mesh architecture multiple 2-D meshes are connected using vertical links, i.e. one more dimension Z is added to the regular X and Y dimensions. Similarly a 3-D torus network is the same as a 3-D mesh network except that it contains wrap around edges at the terminal nodes of all axes (Kini, Kumar, and Mruthyunjaya 2009; Rahman and Horiguchi 2004). Consequently the degree increases in both the 3-D networks. The mesh architecture is the most regular and simple architecture that is used in the design of NoCs. The implementation of a mesh network is simple to understand and verify. In a mesh architecture every node is connected to four of

342


its neighbors. In an N -dimensional mesh network every node is connected to 2N of the neighboring nodes. Thus, the degree of a node in an N -dimensional mesh is 2 × N . The number of connections per node remains constant in a mesh network even though the size of the network increases. The performance of a large mesh network degrades due to the increase in the diameter. The diameter of a 3-D mesh can be defined as D = d × (k − 1), where d represents dimension and k is the number of nodes in a plane (Khan and Ansari 2011c). A torus network is same as mesh network with boundary nodes connected by wrap-around edges. These wrap-around edges significantly reduce the overall diameter of the network and thus improve the throughput and latency. The diameter and network cost of the torus are just half of the mesh topology. The degree of the network is 4, the number of nodes N = n × n and the network cost is (4 × n) in an n × n torus (Ki, Lee, and Oh 2009). The architecture shown in Figure 12.4 has an asymmetric number of nodes in planes. There are many SoC applications where we place unequal numbers of IP cores in the planes. Therefore, every plane has a different number of processing elements, and thus produces a different diameter for each plane. Therefore, we have logically partitioned the torus space into quadrants and selected the nearest wrap-around edge to connect the destination node(Khan and Ansari 2011c). The diameter of an asymmetric torus can be defined as follows: j n k j n k j n k y z x + + (12.6) D =d× 2 2 2 where nx , ny , nz is number of nodes in plane x, y and z respectively

12.1.5

Power Consumption Issues in 3-D Topologies

Power dissipation is an important issue in 3-D circuits. The interconnection network has substantial amounts of power dissipation due to interconnects and buffers. For an example the MIT Raw on-chip network consumes 36% of the total chip power and 20% of the total power of the Alpha 21364 microprocessor due to the interconnection network (Soteriou and Peh 2004). Therefore, there is a need for power-aware interconnections and efficient topologies. The existing traditional approaches for power saving are not sufficient to address the needs of power issues in current SoC designs. The power consumption is also affected by IC technology. 3-D IC technology is expected to have lower power consumption than 2-D circuits due to shorter global interconnects. The topology of the NoC also affects the power consumption of the network in many ways. The power consumption can be reduced by using a topology that has minimum network cost. Pavlidis and Friedman (2007) have shown the effect on power for three different types of topologies. When the authors have used 2-D IC technology for a 3-D NoC they found that power consumption is decreased in this topology by reducing the number of hops for packet switching. The 3-D topology can reduce power even in small networks where the number of IPs is very small. However, the power savings are greater in larger


343

networks. In a second approach, the authors have experimented with 3-D IC technology for 2-D NoC, where horizontal bus length has been made shorter by implementing the IPs in more than one physical plane. The greater number of physical planes integrated in a 3-D IC technology provides optimum value for power regardless of the network size and operating frequency. In their third approach the authors have used 3-D IC technology for 3-D topology, where they observed the greatest savings in power in addition to the minimum delay.

12.2

Related Work

Researchers have considered butterfly fat tree (BFT), generic fat tree based interconnection networks for NoC applications (Greenberg and Guan 1997; Grecu et al. 2004; Guerrier and Greiner 2000). Feero and Pande (2009) have experimented a 64-IP SoC with BFT topology that contains 28 switches. Each switch in a BFT network consists of six ports, one to each of four child nodes and two to parent nodes, with the exception of the switches at the topmost layer. When the authors mapped to a 2D structure, the longest interswitch wire length for a BFT-based NoC is l2 DIC/3, where l2 DIC is the die length on one side (Grecu et al. 2004; Pande et al. 2005). Pande et al. (2005) have found that if the NoC is spread over a 20 mm × 20 mm die, then the longest interswitch wire is 10 mm. On the other hand, when the authors mapped the same BFT network onto a four-layer 3D SoC, wire routing became simpler, and the longest inter switch wire length was reduced by at least a factor of two (Feero and Pande 2009). In this work, the load on the router varies. At the bottom layer we have more IPs connected to the router while there are fewer routers at the top layer. Therefore, the numbers of input/output ports and the power dissipation also vary. The diameter of the FAT tree is large with varying node degree. The FAT tree based topology may not be optimum for many NoC applications. Also, a significant amount of research has been conducted with respect to off-chip networks (Pinkston and Duato 2006; Dally and Towles 2003; Duato, Yalamanchili, and Ni 2003). The basic concepts of off-chip networks can be applied to NoCs. The majority of NoC topologies gravitate towards either ring or mesh. The IBM Cell processor, the first product with an NoC, is built on ring topology. The ring topology is largely being used for design simplicity, ordering properties and low power consumption. The IBM Cell architecture (Hofstee 2005; Gschwind et al. 2006) is a joint effort between IBM, Sony and Toshiba to design a power-efficient family of chips targeting game systems. The IBM Cell has been designed on a 90 nm, 221 mm2 chip that can run at frequencies above 4 GHz. This consists of one IBM 64-Four rings that is used to boost the bandwidth in turn that alleviates the latency problem in the network. The Intel Larrabee is also based on two-ring topology

344


FIGURE 12.5 Binary Tree (Khan and Ansari 2011b) (Seiler et al. 2009). Balfour and Dally (2006) have presented a comparison of various on-chip network topologies including mesh, concentrated mesh, torus and fat tree. The MIT’s Raw chip has also used multiple mesh structure on a Tilera TILE64 chip (Wentzlaff et al. 2007).

12.3

Binary Search Tree based Ring Topology

A binary tree is an ordered rooted structure where every node has at most two nodes designated as left or right child node. The maximum depth (height) of a binary tree of n nodes is (n − 1) (every non-leaf node has exactly one child) (Cormen et al. 2010). The minimum depth of a binary tree of n nodes is (n > 0), dlog2 ne (every non-leaf node has exactly two children, that is, the tree is balanced). In what follows we consider a few examples of binary trees with different permutations. A binary search tree (BST) is a tree that satisfies the following criteria. The left node is always less than the root and right node is always greater than the root value (Cormen et al. 2010). A BST algorithm is applied to find out any element in the tree. The BST, by nature, allows us to apply the divide-and-conquer technique easily. ∀y in left subtree of x then [y] ≤ [x]

(12.7)

∀y in right subtree of x then [y] ≥ [x]

(12.8)

In this work the authors have constructed a modified structure of a binary tree that reduces the network diameter and degree. The basic module of the proposed tree is shown in Figure 12.6 (Khan and Ansari 2011b). The structure contains only three nodes. Every node in the basic module is capable of communicating with other nodes directly without any hop. Thus, the diameter of the basic module is 1 only. In Figure 12.6, we have also shown a ring interconnection with l = 1, l = 2 and l = 3. The level is formed by extending terminal nodes. In Figure 12.6, the authors have shown a ring interconnection


(a) l=1(b) l=2

345

(c) l=3

FIGURE 12.6 Proposed Topology with different levels (l = 1, l = 2, and l = 3) (Khan and Ansari 2011b)

FIGURE 12.7 Ring Based Tree Topology (Khan and Ansari 2011b) that has a maximum of 21 nodes at level l = 3 (Khan and Ansari 2011b). In the next section, we present derivation for total number of nodes, average degree, and diameter of the network.

12.3.1

Number of nodes (N ) at lth level

Theorem 7 For a ring based tree having level l and N nodes, then: 1. The total number of nodes N having level l is 3(2l − 1) 2. The total number of terminal nodes T at level l is 3(2l−1 ) Proof 10 The number of nodes at any level l can be derived using induction

346


FIGURE 12.8 3-D Tree-Mesh as follows: Base case : At level l = 1 , the number of nodes N = 3. Clearly true for all as the base module has three nodes. Induction Hypothesis : If we move to the next level l = 2, then the next level has 3 old nodes and 6 new nodes. Therefore, N = 3 + 6. Similarly, we


347

can derive for other levels as follows (Khan and Ansari 2011b): l=3

,

N = 9 + 12

l=4

,

N = 21 + 24

l=5

,

N = 45 + 48

l=6

,

N = 93 + 96

l = 7 , N = 189 + 192 .. .. . . l=n

l=n

,

N = (3(2n−1 ) − 3) + (3(2n−1 )

, ,

N = 3(2.2n − 1 − 1) N = 3(2n − 1 + 1 − 1)

,

N = 3(2n − 1)

,

N = 3(2n − 1)

Therefore, the number of nodes at level l can be written as follows: N = 3(2n − 1)

(12.9)

Proof 11 The number of terminal nodes at any level can be derived by induction. Base case : At level l = 1, the number of terminal nodes T = 3. Therefore, at level l = 1, T = 3 × (2l − 1). Clearly true for all as the base module has three terminal nodes (Khan and Ansari 2011b). l=1

,

T =3

l=2

,

T = 6 = 3(2)

l=3

,

T = 12 = 3(4) = 3(22 )

l = 4 , T = 24 = 3(8) = 3(23 ) .. .. . . l=n

,

T = 3(2n−1 )

Therefore, the number of terminal nodes at level l can be written as follows: T = 3(2n−1 )

12.3.2

(12.10)

Average Degree (d) of the Network at lth level

The degree of a node represents the number of communication ports (edges) required at each node (processing elements). The node degree has a direct effect on the cost of each node, with the effect being more significant for parallel ports containing several wires.

348


Proof 12 In the topology, every internal node has a degree of 4, while every terminal node has a degree of 2. Therefore, degree varies between 2 and 4. The total number of terminal nodes at the lth level is 3(2n−1 ). The total number of internal nodes at lth level is (3 × 2n−1 − 3). Therefore, the degree of internal and terminal nodes can be calculated as follows (Khan and Ansari 2011b): The degree of internal nodes in the network is: 4 × (3(2n−1 ) − 3 The degree of terminal nodes in the network is: 2 × (3(2n−1 ) Total degree of the network would be: 4 × (3(2n−1 ) − 3) + (2 × (3(2n−1 ) = 18 × (2n−1 ) − 12 Therefore, average degree can be defined as: 18 × (2n−1 ) − 12 Total degree of Network = Number of Nodes N 18 × (2n−1 ) − 12 = 3(2n − 1) 6 × (2n−1 ) − 4 = 2n − 1

Please check the −4 in the top line. Is it correct?

Average Degree of the Network at lth level is as follows: D=

12.3.3

6 × (2n − 1)−4 2n − 1

(12.11)

Diameter (D) of Level l network

The diameter of a network is the maximum inter-node distance, i.e., the maximum distance between any two points in the topology where distance is the shortest path between (ri , rj ). We have derived D using induction as follows (Khan and Ansari 2011b): Base case : At level l = 1, every node is connected to all the nodes at unit distance. Therefore, at level l = 1, D = 1 + 2 × (n − 1), where l = n, clearly true for all as the diameter of the base module is 1. Proof 13 At the next level, let l = 2, diameter D could be written as a summation of the diameter of the base module and distance of the left and right networks from the base module. Therefore, at level l = 2, the distance of


349

the left and right networks from the base module is 2 only. Hence, D = 1(base module) + 1(left network) + 1(right network). Similarly, we can verify for the remaining values of l. l = 3, l = 4, l = 5, l = 6, .. .

D=1+2+2=5 D=1+3+3=7 D=1+4+4=9 D = 1 + 5 + 5 = 11 .. .

l = n,

D = 1 + (n − 1) + (n − 1) D = 1 + (2n − 2) D = 1 + 2 × (n − 1)

Therefore, the diameter of the network can be written as follows: D = 1 + 2 × (n − 1)

12.4

(12.12)

Layout and Implementation

The ring topology is simple but it has poor performance when compared to higher-dimensional networks like the mesh, torus, tree etc. The latency, throughput, energy and reliability of higher-dimensional networks are good. A ring has a node degree of two while a mesh or torus has a node degree of four, where node degree in an NoC refers to the number of links (physical ports) in and out of a node. The mesh and torus require more links at routers. The topologies, featured in Figure 12.4, are three-dimensional topologies that map readily to a multiple metal layer. The torus has to be physically arranged in a folded form to equalize wire lengths instead of employing long wrap-around links between edge nodes. The 3-D torus topology has lower hop count (which leads to lower delay and energy) compared to a mesh. On the other hand, the tree topology has the advantage of lower diameter. The topology shown in Figure 12.7 at level l = 3.5 has 29 nodes. Sometimes, traffic across the subnetwork moves through the root node only. The remaining 28 nodes in the network are divided into 4 sub-networks as shown in Figure 12.9. Each subnetwork has 7 nodes with a local root node. To minimize the wiring length, a mesh and torus structure has been adopted as shown. The placement shown of the proposed topology offers simple routing regulations like XY or XYZ for a three dimensional arrangement.

350


FIGURE 12.9 Layout of the proposed topology (Khan and Ansari 2011b) TABLE 12.2 Analysis of Network Parameters for Base Module (Khan and Ansari 2011b) l 1 2 3 4 5 6 .. .

Ni 3 9 21 45 93 189 .. .

Ti 3 6 12 24 48 96 .. .

Average Degree (d) 2 2.6 2.8 2.9 2.9 2.9 .. .

D 1 1 5 7 9 11 .. .

20

3145725

1572864

2.9

39

12.5

Discussion and Analysis

In Figure 12.7, we have shown a tree with l = 3.5 that contains a total of 29 nodes. The equivalent VLSI layout is shown in Figure 12.9. We have presented an exhaustive analysis of the network parameters for the proposed topology as shown in Table 12.2. Based on mathematical analysis we present a graphical analysis among level, number of nodes, degree and diameter as shown in Figures 12.10 and 12.11. The proposed tree topology can have a large number of nodes if sufficient levels are chosen. If we choose l = 1, then we have a total of 3 nodes while the topology can support 3145725 nodes for l = 20. The extended 3-D Mesh-Tree topology as shown in Figure 12.8 will have little increased diameter as 3 + 2 × (1 + 2 × (n − 1)). Here, 2 × (1 + 2 × (n − 1)) is the diameter for the source and destination sub-networks, while 3 is the diameter of 3-D mesh.


351

FIGURE 12.10 Number of nodes in level l (Khan and Ansari 2011b)

12.6

Conclusions

The topology determines possible and efficient protocol strategies implemented by routing elements. The topology of NoC affects the scalability, performance, power consumption, area and complexity of the routing elements. In this chapter, we have constructed a modified structure of ring based binary tree that reduces the network diameter and degree drastically. We have found that the degree of the proposed topology is 25% less than the torus along with a drastic reduction in the diameter of the proposed topology. For a SoC of node 3145725, the diameter of the proposed tree is 39. The diameter of a torus topology for the same number of nodes is approximately 1800, that is too large for a NoC application. We also found that the degree of the presented topology varies between 2 and 3 while the torus has a fixed degree regardless of the number of nodes in the topology. This chapter has demonstrated that both mesh- and tree based NoCs are capable of achieving better performance when instantiated in a 3D IC environment compared to more traditional 2D implementations. However, the proposed tree based topology shows significant performance gains in terms of network diameter, degree and number of nodes. The tree-based NoCs achieve significant gain in energy dissipation and area overhead without any change in throughput and latency. The Networkon-Chip (NoC) paradigm continues to attract significant research attention in both academia and industry. With the advent of 3D IC technology, the achievable performance benefits from NoC methodology will be more pronounced as this chapter has shown. Consequently this will also facilitate adoption of the

352


FIGURE 12.11 Degree and Diameter Analysis of the proposed topology (Khan and Ansari 2011b)


353

NoC paradigm as a mainstream design solution for larger multi-core systems.

12.7

Glossary

Topology: Topology defines logical structure and interconnection between nodes in a network. Multicore: The multi-core processor is a single computing component with two or more independent processors (called ‘cores’) on a single chip. Multiple instructions can be executed in multi-core at the same time, increasing overall speed for programs amenable to parallel computing. Application Specific Integrated Circuits (ASICs): An ASIC is an integrated circuit (IC) that is customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a bluetooth transceiver is an ASIC. Field Programmable Gate Arrays (FPGAs): The FPGA’s function is defined by a user’s program (VHDL/Verilog/Netlist) rather than by the manufacturer of the device. A typical integrated circuit performs a particular function defined at the time of manufacture. In contrast, the FPGA’s function is defined by a program written by someone other than the device manufacturer. System on Chip (SoC): The SoC is a new paradigm for design of VLSI system. The SoC is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. The SoC may contain digital, analog, mixed signal, and often radio frequency functions all on a single chip substrate. Binary Search Tree (BST): The BST is an ordered placement of nodes of binary tree. In a BST, the left node is always less than the root, while the right node is always greater than the root. Intellectual Property Cores (IP): Topology defines physical structure and interconnection between node in a network. Open System Interconnection (OSI): The OSI mode was invented by the International Organization for Standardization(ISO). It is a prescription of characterizing and standardizing the functions of a communications system in terms of abstraction layers.

The definition of IP core does not make sense? Please rewrite. Definitions of IC and EDA deleted (editor).

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Architecture, Reconfiguration and Modeling

Architecture, Reconfiguration and Modeling

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