Architectures for Computer Vision - from Algorithm to

Architectures for Computer Vision from Algorithm to Chip with Verilog Hong Jeong c

2014 John Wiley & Sons Singapore Pte Ltd. Published 2014 by John Wiley & Sons Singapore Pte Ltd.

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Part 1 Verilog HDL Chapter 2 Verilog HDL, Communication, and Control

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The Verilog System

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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The Verilog System

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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The Verilog System

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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The Verilog System

Test Bench

Unit Under Test

Figure: The Verilog system: TB-UUT modules.

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Hello, World!

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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Hello, World!

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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Hello, World!

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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Hello, World!

Hello world in Verilog module main; initial begin $display("Hello, world!\n"); $finish; end endmodule

Hello world in C #include main(); { printf("Hello, world!\n"); }

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Hello, World!

Listing 1: A 4-bit adder:

adder.v

‘timescale 1ns/1ps module adder( input [3:0] a, b, output [3:0] c );

//unit time/precision //ports //input ports //output ports

assign c= a+ b; endmodule

//continuous assignment

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Hello, World!

Listing 2: A test bench:

tb.v

‘timescale 1ns/1ps module tb;

//no ports

//declaration reg [3:0] a, b; wire [3:0] c;

//reg type for storage //wire for connection

//instantiation adder UUT (.a(a),.b(b),.c(c));

//run UUT

//test vector generation initial begin

//run once for simulation

//initialize Inputs a = 0; b = 0; #100;

//execute sequentially //wait 100 ns

//add stimulus here repeat (1000) begin a = a + 1; b = b + 2; #100; end end endmodule c Hong Jeong ( 2015 Wiley & Sons)

Architectures for Computer Vision

//repeat 1000 times //execute sequentially //wait 100ns //repeat end //initial end September 23, 2014

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Hello, World!

Figure: The simulator output: timing diagram.

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Modules and Ports

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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Modules and Ports

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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Modules and Ports

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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Modules and Ports

module A endmodule

module B endmodule

module C endmodule

module D endmodule

module E endmodule

module F endmodule

Figure: A hierarchy of modules.

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Modules and Ports

module B(c,d) input c; output d; wire c; reg d; endmodule

module A reg a; wire b; B(a,b); endmodule

Figure: Connecting two modules by ports.

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Modules and Ports

Listing 3: Module constructs module module_name (port-name, port-name,...,port-name)

//port declarations input declarations output declarations inout declarations

//port directions

//type declarations net declarations //data and variable declarations variable declarations parameter declarations //parameter declarations

//functions and tasks function declarations //function definition task declarations //task definition

//execute once for TB initial begin instantiations end

//one-time execution statements //instantiation of other modules

//procedural statements always begin c Hong Jeong ( 2015 Wiley & Sons)

//statements for a design Architectures for Computer Vision

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Modules and Ports

procedural statements end endmodule

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UUT and TB

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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UUT and TB

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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UUT and TB

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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UUT and TB

Listing 4: The test bench constructs module testbench_name instantiation

//instantiation of UUT

initial begin procedural-statement ... procedural-statement end endmodule

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//one time execution //test vector generation //checking and //report

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UUT and TB

UUT TB

UUT

Comparison

Pattern Algorithm

(a) The connection

(b) The TB structure

of UUT-TB

Figure: The UUT and the TB.

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Data Types and Operations

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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Data Types and Operations

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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Data Types and Operations

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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Data Types and Operations

Listing 5: Arrays [MSB_1:LSB_1]...[MSB_n:LSB_n] variable_identifier [MSB_1:LSB_1]...[MSB_m:LSB_m]

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Data Types and Operations

Example (Arrays) Examples of arrays are as follows: reg reg reg reg

a[7:0]; [7:0] b; c[7:0][0:255]; [0:7] d [0:255];

//8 1-bit scalar register //1 8-bit vector register //8 x 256 array of 1-bit //256 8-bit vector indexed from 0 to 7

//The followings are allowed only in SystemVerilog. reg [1:3][7:0] e; reg [1:3][7:0] f[0:255] reg [1:3][7:0] g[1:2][0:255]

c Hong Jeong ( 2015 Wiley & Sons)

//24-bit 3-field vector //256 24-bit 3-field vectors //512 24-bit 8-field vectors

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Data Types and Operations

Example (Strengths and delays) Some typical examples are as follows. trireg a; //charge trireg (small) #(0,0,100) b; //charge trireg (large) unsigned [0:7] c; //charge and #(10) and1 (out,input1,input2); //delay and #(10,20) and2 (out,input1,input2); //delay bufif0 #(1,2,3) buff0 (i01,io2,dir); //delay bufif0 #(1:2:3,4:5:6,7:8:9) buff1 (io1, io2, dir);

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strength medium strength and delay with range

//delay

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Data Types and Operations

Example (Expressions) Some examples are as follows. &4’b1001=0 false: 4’b0000!, true: 4’b0010! {2’b10,2’b01} = 4’b1001 4’b0100 & 4’b01xz = 4’b0100 ~2’b10 = 2’b01 16’b0,8’bz01 = 8’bzzzzzz01 true: 2’b10 < 4’b010 2’h06 == 4’b0110 X ? Y:Z

c Hong Jeong ( 2015 Wiley & Sons)

//reduction //logic value //concatenation //bit-wise logic //bit-wise complement //bit-wise //logic statement //logic statement //if X is true then Y, else Z

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Assignments

Contents Computer Architectures for Vision Algorithms for Computer Vision Computing Devices for Vision Design Flow for Vision Architectures The Verilog System Hello, World! Modules and Ports UUT and TB Data Types and Operations Assignments Structural-Behavioral Design Elements Tasks and Functions Syntax Summary Simulation-Synthesis Verilog System Tasks and Functions c Hong Jeong ( 2015 Wiley & Sons)

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Assignments

Contents (cont.) Converting Vision Algorithms into Verilog HDL Codes Design Method for Vision Architecture Communication by Hierarchical Name Reference Synchronous Port Communication Asynchronous Port Communication Basic Communication between SystemVerilog and C++ Packing and Unpacking Module Control Procedural Block Control Image Processing System Taxonomy of Algorithms and Architectures Neighborhood Processor BP Processor DP Processor Forward and Backward Processors c Hong Jeong ( 2015 Wiley & Sons)

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Assignments

Contents (cont.) Frame Buffer and Image Memory

Multidimensional Array

Queue

Stack

Linear Systolic Array

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Assignments

Example (Continuous assignments) The two expressions are effectively the same. Continuous declaration wire (strong1, pull0) b = a;

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Declaration, assignment wire b; assign (strong1, pull0) b = a;

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Assignments

Example (Delays) The continuous assignment with delay. wire #100 a; assign wire c = (#20) a + b;

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Assignments

Example (Strengths) The strengths for a continuous assignment. assign (strong1, pull0) b = a; assign (pull0, strong1) b = a; assign (pull0, pull1) b = a;

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//the same as below //wrong

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Assignments

Example (Blocking and nonblocking assignments) Swapping values. Blocking statements

Nonblocking statements

always @(posedge clock) begin c = a; //temporary variable c a = b; b = c; end //always

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always @(posedge clock) begin b