Arithmetic Algorithms and Circuits to Convert MVL to MVL Coded Decimal and Vice Versa Hassan Amine Osseily
Ali Massoud Haidar
Electrical Department, Faculty of Engineering Beirut Arab University Beirut-Lebanon E-mail:
[email protected]
Computer Department, Faculty of Engineering Beirut Arab University Beirut-Lebanon E-mail:
[email protected]
Abstract— The purpose of this paper is to present new algorithms and circuits to convert from MVL (Multiple Valued Logic) to MVL Coded Decimal (MVL-CD) and vice versa. We will introduce two conversion techniques: the first one is called "Addition-Subtraction technique" (AST) while the other method is called "Division-Multiplication Technique" (DMT). Based on AST, we will develop the algorithm and circuit of converters for quaternary and quinary systems. The Addition technique will be applied for converting from MVL to MVL-CD while Subtraction is used for reverse operation. In addition, we will develop the algorithm and circuit of DMT converter for quinary system by using delta gate [8] elements. The division technique will be used to convert MVL to MVL-CD while multiplication will be used for the inverse conversion. At the end of this paper, a brief comparison will show the advantages and disadvantages of these methods in terms of cost and performance. Moreover, we will compare our techniques with other authors' methods and algorithms.
I.
INTRODUCTION
In binary logic [1,2], the conversion from binary to binary coded decimal ,or the inverse, could be done easily since we behave only with simple numbering set {0,1}. In higher valued logic [3,4,5] such as ternary {0,1,2}, quaternary {0,1,2,3} and quinary {0,1,2,3,4}, the matter of conversion becomes different and done in a very difficult way. Many methods of conversion from MVL to MVL coded decimal were considered [6,7] such as the counters comparison, look up table, shift and addition operations algorithm. A novel circuit is proposed in this paper based on delta gate [8] that gives a lowest cost and high speed of performance. The MVL-CD numbers are useful wherever decimal information is transferred into or out of any MVL computerized unit. The advantage of this code is the simplicity to transfer from and to decimal numbers where we need only to remember the MVL numbers from 0 to 9. The disadvantage of this code occurs when performing the arithmetic operations such as addition and subtraction. The result of addition of two MVLCD numbers could be incorrect for some cases where we have to use an arithmetic technique to correct the result. The number sets of quaternary (Qa), quinary (Qi), quaternary coded decimal
(QaCD) and the quinary coded decimal (QiCD) are all summarized in the table 1. TABLE 1: TABLE OF QUATERNARY AND QUINARY NUMBERS Decimal
Qa
Qa-CD
424140
Qi
Qi-CD
525150
0
0
00 00
0
00 00
1
1
00 01
1
00 01
2
2
00 02
2
00 02
3
3
00 03
3
00 03
4
10
00 10
4
00 04
5
11
00 11
10
00 10
6
12
00 12
11
00 11
7
13
00 13
12
00 12
8
20
00 20
13
00 13
9
21
00 21
14
00 14
10
22
01 00
20
01 00
11
23
01 01
21
01 01
….
….
….
…..
….
21
111
02 01
41
02 01
….
…
….
….
….
99
1203
21 21
344
14 14
From table 1, we can note that there are six numbers in quaternary {22, 23, 30, 31, 32, 33} do not belong to QaCD set.
To correct these numbers and making them belong to QaCD, we just add the quaternary number 12 (6 in decimal) to each quable. Consider the following example: Decimal
Qa-CD
55
11 11
87
20 13
14 2
(31 30)
30 and 31 do not belong to QCD set; we have to add 12 to 30 and 31 as follows: 31 30 +12 12 01 10 02 The result becomes correct. For quinary system, we can note that there are fifteen quinary numbers {20,21,22,23,24,30,31,32,33,34,40,41,42,43,44} do not belong to QiCD set. To correct these numbers and making them belong to QiCD, we just add the quinary number 30 (15 in decimal) to each quibble. Consider the same previous example:
Decimal
•
Logic Circuit of Qa/Qa-CD Converter
To develop a conversion algorithm that can convert any quaternary N to Qa-CD, we will apply a loop of addition of the number 12 to the number N. To do that, we have to split the quaternary set into intervals to know how many times we should run the loop. If we take intervals consisting each of ten quaternary numbers, here we shall add one time 12 to numbers between 10≤ N < 20 and twice to the numbers 20≤ N < 30 and three times to the numbers 30 ≤ N< 40 and so on. In general: n * 10 ≤ N < (n+1) * 10 ADD n*12
10 10
87
13 12
33 = 3 x 10 + 3 Therefore, to convert it into Qa-CD system, we have to repeat the addition of 12 to the quaternary (201) three times. The result will be (03 03) which belongs to Qa-CD and equals to the decimal 33. Figure 1, shows a converter block diagram that can convert a quaternary number with 4 quats into a Qa-CD code where the quaternary number 1203 (99 in decimal) is the maximum quaternary value that can be converted. The equivalent Qa-CD number in this case will be 21 21 having 4 digits (or 2 quables).
(23 22)
23 and 22 do not belong to QiCD set; we have to add 30 to 23 and 22 as follows: 23 22 +30 30 01 04 02 The result becomes correct. II.
(1)
For example, the decimal number 45 = (231) Qa, can be written as follows:
Qi-CD
55
14 2
A. MVL to MVL-CD using the Addition Technique
ADDITION-SUBTRACTION TECHNIQUES (AST)
AST technique can be applied to all MVL systems where it has the same concept and the same form of circuit diagram the main change is the radix of the system. In this paper, we will discuss the cases of quaternary and quinary systems and we will build the logic circuits by using blocks of adders and subtractors where we can generalize it to fit all multi-valued system and for any length of numbers. Figure 1. Qa to Qa-CD Using Addition Technique
For the first clock cycle, the quaternary number will be added to 12 at the adder and will be subtracted by 22 at the subtracter. For the second cycle, the transfer units transfer to a feedback state to repeat the addition and subtraction operations. This will continue for many clock cycles until we get a negative result at subtracter output. In this case, the quinary logic transfer unit will stop the addition and subtraction operations by taking a command from the sign digit of the subtracter. The Q-CD number is obtained at the output of the adder.
B. MVL-CD to MVL Using the Subtraction Technique To convert MVL-CD to MVL, we follow exactly the inverse of previous algorithm. The addition technique becomes subtraction and the conversion algorithm for quaternary becomes as follows: n * 10 ≤ N < (n+1) * 10 SUB n * 12
(3)
moreover, the algorithm for quinary becomes •
Logic Circuit of Qi/Qi-CD Converter
n * 10 ≤ N < (n+1) * 10 SUB n * 30
To develop an algorithm and circuit for quinary system, we follow the same procedures of quaternary where we will get the same block diagram. The quinary algorithm is similar to the equation (1) but with replacing the quaternary number 12 by the quinary 30 n * 10 ≤ N < (n+1) * 10 ADD n * 30
(2)
The figure 2 shows the logic circuit of quinary to quinary coded decimal converter with capabilty to convert all numbers from 000 up to 344 (99 in decimal). The equivalent QiCD number in this case will have 4 digits (or 2 quibles).
III.
(4)
DIVISION-MULTIPLICATION TECHNIQUE
We have noted from the previous method that it contains many addition and subtraction operations even for small quaternary or quinary numbers. This will make the elements cost quite high and the performance quite low. For that, we will introduce a new technique of conversion and we will develop the corresponding logic circuit by using delta gates [8] as a basic switching element. The output of quinary δ gate [8] is defined as: A if a=b (5)
δ(A,B;a;b) = B otherwise Where, - A,B,a,b belong to the quinary set Q={0,1,2,3,4} - a, b: control variables - A, B: residue variables The symbol of this logic gate is as follows:
Figure 3. Symbol of δ gate
based on the δ gate, any quinary logic function of one input variable x can be represented by the equation (6) and be realized with four δ gates as shown in Figure 3. ƒ(x)=δ((ƒ(i0),δ(ƒ(i1),δ(ƒ(i2),δ((ƒ(i3), ƒ(i4);i3;x);i2;x);i1;x);i0;x) Figure 2. Qi to Qi-CD Using Addition Technique
(6)
Figure 4. Network of ƒ(x)
B. MVL to MVL-CD using the Division Technique •
Division Algorithm for (Qi / QiCD Converter)
To convert a quinary number CBA into a quinary coded decimal number with the form "dc ba" where the digits A,B,C,a,b,c,d belong to the quinary set {0,1,2,3,4}, we refer to the table 1. from this table, we can conclude the equations of a,b,c and d. as follows. a=A b = 0 if CB is an even number
(7) (8)
b = 1 if CB is an odd number
(9)
dc = (CB / 2) if CB is an even number
(10)
dc = (CB–1) / 2 if CB is an odd number
(11)
It is very clear that equations 10 and 11 behave with division by "2" operation. •
Example 1
Let Q1 be a quinary number Q1=231 (equal to 66 in decimal) and we want to convert it into Qi-CD system. The result will be obtained directly from the equations (7,8,9,10,11) of a,b,c and d where A=1, B=3 and C=2: a=A=1 b=1 because CB=23 is odd (13 in decimal) dc=(CB-1)/2 = (23-1)/2 = 11 => c=1, d=1 Then the Qi-CD equivalent to the quinary number 231 is: Qi-CD=dc ba = 11 11 (or 66 in decimal)
•
Logic Circuit of Qi-QiCD Converter Using δ gate
To construct the logic circuit of the Qi / Qi-CD converter which is based on the division by 2 algorithm, we have to return to equations 7,8,9,10 and 11.Using δ gate, the logic circuit that verifies these equations is shown in Figure 5 with an example of quinary input 333:
Figure 5. Q to Qi-CD converter using δ gate
The circuit consists of three main branches that are needed to determine b, c and d while a is connected directly to A. The first circuit aims to determine if CB is even or odd by giving at its output "b" 0 for even numbers and one for the odd ones. The second circuit’s role is to represent the function of "c" that can be done by several δ gates as shown. The third circuit is designed to give at its output "d" 0 if C=0 and 1 if C=2,3 From the output of these circuits, we will find that the converted number in Qi-CD is 14 03 or 93 in decimal. Remembering that the maximum value of "C" is 3 since the maximum number can be converted by this circuit is 344.
•
Generic Circuit to Convert Quinary to Quinary Coded Decimal Using Delta Gate.
The previous circuit is converting quinary numbers from 000 to 344 (99 in decimal). To generalize this circuit, we can use it as main unit to develop converters with higher capacity of conversion.
We will add new steps to the previous algorithm in order to be able to convert any quinary number. The following circuit is intended to convert quinary numbers from 0 to 12444 (equivalent to decimal 999)
Figure 6. Q to Qi-CD converter using δ gate
This circuit could be developed easily to convert any quinary numbers. B. MVL-CD to MVL Converter using Technique •
Multiplication Figure 7. Qi-CD to Q converter using δ gate
Algorithm
•
To convert from quinary coded decimal to quinary system and based on the equations 7,8,9,10 and 11, we can simply deduce the following equations: A=a CB=2 * dc+ b
The previous circuit is converting quinary coded decimal numbers from 00 00 to 14 14 (99 in decimal). To generalize this circuit, we can use it as main unit to develop converters (12) with higher capacity of conversion. (13)
it is very clear that equations 12 and 13 behave with multiplication by "2" operation. •
Example 2
Let dc ba = 12 01 be a quinary coded decimal equivalent to the decimal number 71 the conversion of this QiCD number to Qi system in the form CBA is done by using the equations 12 and 13. A=a=1 CB=2*12+0=24 Then the equivalent in quinary is CBA =241 which is equal to 71 in decimal. •
Generic Circuit to Convert Quinary Coded Decimal to Quinary Using Delta Gate.
The following circuit diagram can convert quinary coded decimal numbers from 00 00 00 up to 14 14 14 (equivalent to decimal 999) As an example let us convert the QiCD 12 03 11 (736 in decimal) the output of first converter will be equal to quinary 121 and the output of the second converter will be equal to 103. the final output of quinary adder will give the quinary number 10421 which the Qi equivalent to the QiCD number 12 03 11.
3.2.3 Logic Circuit
The logic circuit that verifies these equations is shown in Figure 7 with a quinary coded decimal input 1201 where the result is quinary given at the outputs and will be equal to 241. this circuit could convert quinary-coded decimals from 00 00 to 12 12: Figure 8. Q to Qi-CD converter using δ gate
Already we have seen the circuit design of numbers set {00,01,…99} now, we will develop the design of number set from 000 up to 999. We know that any number could be written as summation of several terms like (736=700+36).Then for the term 36 can be converted by using the previous designed converter. For the term, 700 we can build another converter, which can convert the hundreds 100,200,300,400,500 up to 900 from QiCD to Qi. TABLE 2: TABLE OF QUINARY EQUIVALENTS TO HUNDREDS fe-dc-ab
Decimal
EDC 4 3 2
Qi-CD
BA
555
5150
01 00 00
100
004
00
02 00 00
200
013
00
03 00 00
300
022
00
04 00 00
400
031
00
10 00 00
500
040
00
11 00 00
600
044
00
12 00 00
700
103
00
13 00 00
800
112
00
14 00 00
900
121
00
V.
C = (e * 4)
(14)
D = (e + 4) for f = 0 or e = 0
(15)
E = 1 for f = 1 and
e≠0
e ≠ {0,1}
(16) (17)
Using the equations 14, 15, 16 and 17, the circuit can be developed easily to convert any quinary numbers. IV.
CONCLUSION
As a conclusion, the converter using DMT is more efficient with costless. The speed of conversion is very important since we behave with cascading switching elements. Quinary logic is the ideal approach to reach the decimal system. For that, we have designed a quinary converter with no clock pulse to synchronize the sequence and time of execution and we have shown that quinary set as it is divisor of decimal, we have seen that all quinary sets treated in a similar way to decimal system. MVL to MVL-CD converters are here intended to display as decimals all quaternary or quinary information in order to be understood by users who need only to read results from these MVL logic or arithmetic units.
For f=e=0 the conversion of "dc be" will be done through the first converter (00 to 99). For other cases, the equations of EDC can be written as follows:
D = (e + 3) for f = 1 and
we found that operation of shifting, addition and subtraction will need a memorized units and registers to store the numbers then we need many clock cycles to synchronize the execution steps which could take lot of time especially when converting large numbers. The methods of conversion using DivisionMultiplication algorithm and their developed logic circuits were found the best as cost wise and performance. For a Qi / QiCD converter as shown on figure 5, the number of element of δgates is 16 while the number of elements that is required to build a similar converter using the shifting and addition technique [6] is much bigger and could exceed 200 since we need to build first many shift registers and many adders. In addition, it requires more than 10 clock cycles at least to perform a number such as 344, while in division technique; it is clearly that this number can be converted with one clock cycle.
COMPARAISON WITH OTHER TECHNIQUES
This paper presented the development of a new technique concerning the conversion through quinary system to quinary coded decimal system and vice versa using division and multiplication by "2" algorithm and using delta gates to construct their logic circuits. This technique is a novel method of conversion comparing with other algorithms and models. The advantages of this technique are the design simplicity and the high performance compared with all other methods. This technique can be generalized for any length of MVL numbers. Comparing with the method of shifting and addition [6] and with Addition Subtraction Technique explained in this paper,
REFERENCES [1] Morris Mano and Charles R. kime “Logic and Computer Design Fundamentals” second edition, PP.3-24 Prentice-Hall publishing New Jersy, 2001. [2] Albert Paul Malvino, “Digital Computer Electronics” second edition, Tata McGraw-Hill publishing Company Limited, NEW DELHI, 1994. [3] Goerge Epstein, “Multiple–Valued Logic Design: an introduction” . PP.1251University of North Carolina, computer science department, USA. 1993. [4] Goerge Epstein, “The Development of Multiple–Valued Logic as Related to Computer Science” . Computer, Vol. C-9, PP.20-33, Indiana University, USA. September 1974. [5] Sasoa, T., “Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arraya”, IEEE Trans. On Comp., Vol. C-30 No. 9, pp. 635-643, September 1981. [6] Lu, H.; Lee, S.C. “MCD-to-m-valued and m-valued-to-MCD converters” Proceedings of the Eighteenth International Symposium on Multiple-Valued Logic, 1988 Spain Page(s):364 – 370 [7] Adham S.M.I, Abdulkarim M.A.H “Ternary to Ternary Coded Decimal Conversion Using CMOS Integrated Circuits” Proceedings of the Fifteen International Symposium on Multiple-Valued Logic, 1985 Spain Page(s):371 – 381. [8] A. M. Haider, C.Zukeran. C.Afuso and T.Yamashiro.“Design of a Quaternary δ-gate and its characteristics” IEICE. conference.pp.1-114. 1991.
