ARM SYSTEM DEVELOPER'S GUIDE

ARM SYSTEM DEVELOPER'S GUIDE DESIGNING AND QPTIMIZING SYSTEM SOFTWARE

ANDREW

N. 5LOSS

DOMINIC 5YMES CHRIS WRIGHT WITH A CONTRISUTION SY JOHN RAYFIELD

AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS· SAN DJEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO

ELSEVIER

Morgan Kaufmann is an imprint ofElsevier

M(~® MORGAN KAUFMANN PUBLISHERS

CONTENTS

ii

ABOUT THE AUTHORS PREFACE

Xl

CHAPTER

1

ARM EMBEDDED SYSTEMS

3 4

The RISC Design Philosophy The ARM Design Philosophy Embedded System Hardware Embedded System Software Summary

6 12 15

ARM PROCESSOR FUNDAMENTALS

19

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

21 22 29 33 34 37 38 43

1.1

1.2 1.3

1.4 1.5

5

CHAPTER

2

Registers Current Program Status Register Pipeline Exceptions, Interrupts, and the Vector Table Core Extensions Architecture Revisions ARM Processor Families Summary

CHAPTER

3

INTRODUCTION TO THE

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

ARM INSTRUCTION SET

Data Processing Instructions Branch Instructions Load-Store Instructions Software Interrupt Instruction Program Status Register Instructions Loading Constants ARMv5E Extensions Conditional Execution Summary

47 50 58 60 73 75 78 79 82 84 V

VI

Contents

CHAPTER

4

INTRODUCTION TO THE THUMB INSTRUCTION SET

4.1 4.2 4.3 4.4

4.5 4.6 4.7

4.8

4.9

Thumb Register Usagc ARM~Thumb Interworking Other Branch Instructions Data Processing Instructions Single-Register Load-Store Instructions Multiple- Register Load-Store Instructions Stack Instructions Software Interrupt Instruction Summary

87 89

90 92

93 96

97 98 99

100

CHAPTER

5

EFFICIENT C

5.1 5.2

5.3 5.4 5.5

PROGRAMMING

Overview of C Compilers and Optimization Basic C Data Types C Looping Structures Register Allocation

103 104 lOS

113 120

Function Calls

122

5.6 5.7

Pointer Aliasing Structure Arrangement

127 130

5.8 5.9

Bit-fields

133

Unaligned Data and Endianness Division Floating Point Inline Functions and lnline Asscmbly Portability Issues Summary

136 140 149 149 153

5.10 5.11 5.12

5.13 5.14

ISS

CHAPTER

6

WRITING AND OPTIMIZING ARM ASSEMBLY CODE

157

6.1

158

6.2

6.3 6.4 6.5 6.6 6.7 6.8

Writing Assembly Code Profiling and Cyde Counting Instruction Scheduling Register Allocation Condirio nal Execution Looping Constructs Bit Manipulation Efficient Switches

163 163 171

180 183

19\ 197

Contents

6.9 6.10

Handling Unaligned Data Summary

vii

201 204

CHAPTER

7

OPTIMIZED PRIMITIVES

207

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9

208 212 216 238 241 248 253 255 256

DoubIe- Precision Integer Multiplication Integer Normalization and Count Leading Zeros Division Square Roots Transeendental Functions: log, exp, sin, cos Endian Reversal and Bit Operations Saturated and Rounded Arithmetic Random Number Generation Summary

CHAPTER

8

DIGITAL SIGNAL PROCESSING

259

8.1 8.2 8.3 8.4 8.5 8.6

260 269 280 294 303 314

Representing a Digital Signal Introduction to DSP on the ARM FlR filters UR Filters The Discrete Fourier Transform Summary

CHAPTER

9

EXCEPTION AND INTERRUPT HANDLING

9.1 9.2 9.3 9.4

Exception Handling Interrupts Interrupt Handling Schemes Summary

317 318 324 333 364

CHAPTER

10

FIRMWARE

367

10.1 Firmware and Bootloader 10.2 Example: Sandstone 10.3 Summary

367 372 379

viii

Contents

CHAPTER

11

EMBEDDED OPERATING SYSTEMS

381

11.1 11.2 11.3

381 383 400

Fundamental Components Example: Simple Little Operating System Summary

CHAPTER

12

CACHES

403

12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8

404 408 418 423 423 443 456 457

The Memory Hierarchy and Cache Memory Cache Architecture Cache Policy Coprocessor 15 and Caches Flushing and Cleaning Cache Memory Cache Lockdown Caches and Software Performance Summary

CHAPTER

13

MEMORY PROTECTION UNITS

461

13.1 13.2 13.3 13.4

463 465 478 487

Proteeted Regions Initializing the MPU, Caches, and Write Buffer Demonstration of an MPU system Summary

CHAPTER

14

MEMORY MANAGEMENT UNITS

491

14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12

492 493 501 501 506 510 512 513 515 520 545 545

Moving from an MPU to an MMU How Virtual Memory Works Details of the ARM MMU Page Tables The Translation Lookaside Buffer Domains and Memory Access Permission The Caches and Write Buffer Coprocessor 15 and MMU Configuration The Fast Context Switch Extension Demonstration: A Small Virtual Memory System The Demonstration as mmuSLOS Summary

Contents

ix

CHAPTER

15

THE FUTURE OF THE ARCHITECTURE BY JOHN RAYFIELD

549

15.1 15.2 15.3

550 560 563 563 566

ISA

15.5

Advanced DSP and SIMD Support in ARMv6 System and Multiprocessor Support Additions to ARMv6 ARMv6Impiementations Future Technologies beyond ARMv6 Summary

ApPENDIX

A

ARM AND THUMB ASSEMBLER INSTRUCTIONS

569

A.l A.2 A.3

569 570 573 620 631

AA

A.5

Using This Appendix Syntax Alphabetical List of ARM and Thumb Instructions ARM Assembler Quick Reference GNU Assembler Quick Reference

ApPENDIX

B

ARM AND THUMB INSTRUCTION ENCODINGS

637

B.l B.2 B.3

637 638 645

ARM Instruction Set Encodings Thumb Instruction Set Encodings Program Status Registers

ApPENDIX

c

PROCESSORS AND ARCHITECTURE

647

C.l C.2

647 647

ARM Naming Convention Core and Architectures

ApPENDIX

D

INSTRUCTION CYCLE TIMINGS

651

D.l D.2 D.3

651 653 654 655 656 658 659 661

DA

D.5 D.6 D.7 D.8

Using the Instruction Cyde Timing Tables ARM7TDMI Instruction Cyde Timings ARM9TDMI Instruction Cyde Timings StrongARMl Instruction Cyde Timings ARM9E Instruction Cyde Timings ARMIOE Instruction Cyde Timings Intel XScale Instruction Cyde Timings ARMll Cyde Timings

X

Contents

ApPENDIX

E

SUGGESTED READING

667

E.l E.2 E.3

667 667

EA

ARM References Algorithm References Memory Management and Cache Architecture (Hardware Overview and Reference) Operating System References

INDEX

667 668 669