aspects of balanced ternary arithmetics implemented ... - heim.ifi.uio.no

ASPECTS OF BALANCED TERNARY ARITHMETICS IMPLEMENTED USING CMOS RECHARGED SEMI-FLOATING GATE DEVICES Ph.D. thesis

Henning Gundersen May 2008

Acknowledgments This thesis is a part of my work for my Ph.D. in Nanoelectronic at the Microelectronics Systems Group (MES) at the Institute of Informatics at the University of Oslo. This thesis is written using the powerful text processing language tool, LATEX I want to thank all of my friends at the Microelectronics Systems Group, Ph.D. students, master students and employees. During my years at the Department of Informatics I met a lot of interesting people. Their humour really kept me going. Furthermore a lot of funny and not always relevant discussions with H˚ avard K. Riis and Johannes G. Lomsdalen made life memorable. I especially would like to thank my supervisor, Professor Yngvar Berg, for never losing faith, my co-advisor, Dag T. Wisland, Snorre Aunet, for his academic and non-academic discussions, Tor Sverre ’Bassen’ Lande, for his knowledge in analog design, my friend Bjørn Solberg, for proof reading, my colleagues at Telenor, my patience and helpful wife Heidi for support and love and last but not least my two lovely daughters Ina and Matilde for their patience and understanding when I was not there.

Blindern, May 19, 2008

Henning Gundersen

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Abstract Mostly all electronics used in computers today are based on binary logic. However, does the binary logic have the capacity to be the leading technology in the future? Thus I raise the question: why not use ternary logic? The optimal base for developing hardware is proven to be 2.71. The closest integer to this optimal base is base 3, which corresponds to the ternary numbering system. This thought is not new to computer scientists. In 1958 a ternary computer was built in Russia, and as early as 1840 a self-taught English mathematician, Thomas Fowler, invented a ternary calculating machine. This thesis deals with some novel applications which can benefit from using ternary logic in current computer designs. I have proposed several ternary circuit designs. The circuits are implemented using recharged semi-floating gate (RSFG) CMOS transistors. A novel balanced ternary adder seems to be the most promising one. This new adder can directly replace any ordinary binary solution. These applications can use any available CMOS process and no post processing is needed, but for the moment there are some limitations. This is novel technology which needs some more research to reach the robustness level of current designs. Currently it does not exist, electronic components which in its nature have three stable states. Binary logic uses transistors which can be switched ’on’ or ’off’. At the moment, this is a limitation in the relation to the development of ternary architectures. However, my qualified guess is that ternary logic will be a leading technology in the future.

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Contents 1 INTRODUCTION 1.1 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 List of Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Overview of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 FLOATING GATE TRANSISTORS 2.1 Introduction . . . . . . . . . . . . . . . . . . . . 2.2 Floating Gate (FG) MOS Transistor . . . . . . 2.2.1 The Floating Gate Capacitors . . . . . . 2.2.2 Capacitive Voltage Division Model . . . 2.2.3 Charge Loss on the Floating Gate Node 2.2.4 Inverter Based Structures . . . . . . . . 2.2.5 Split-Gate Inverter Structure . . . . . . 2.2.6 Common Gate Inverter Structure . . . . 2.3 Non-Volatile FG Transistors . . . . . . . . . . . 2.3.1 Fowler Nordheim Tunneling . . . . . . . 2.3.2 Hot Carrier Injection . . . . . . . . . . . 2.3.3 UV Activated Programming . . . . . . . 2.4 Volatile FG Circuits . . . . . . . . . . . . . . . 2.4.1 Recharged Floating Gate . . . . . . . . 2.4.2 Pseudo Floating Gate . . . . . . . . . . 2.4.3 Recharged Semi-Floating Gate . . . . . 2.4.4 Clock Generator . . . . . . . . . . . . . 2.5 Auto-Zero Element . . . . . . . . . . . . . . . . 2.5.1 Removing the Auto-Zero Clock Signal . 2.6 Limitations Using 90nm CMOS Technology . . 2.6.1 Max Clock Frequency . . . . . . . . . . 2.6.2 Parasitic Capacitance . . . . . . . . . . 2.6.3 Gate Leakage in Thin Oxide Layers . . 2.7 Measurement and Results . . . . . . . . . . . . 2.7.1 Gain . . . . . . . . . . . . . . . . . . . . 2.8 Summary . . . . . . . . . . . . . . . . . . . . . V

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1 2 2 4 5 5 6 7 7 8 9 9 9 10 10 10 10 11 11 11 12 12 13 13 13 13 14 14 15 15 16

VI 3 MULTIPLE-VALUED TECHNOLOGY 3.1 Introduction . . . . . . . . . . . . . . . . 3.1.1 History . . . . . . . . . . . . . . 3.2 Multiple-Valued Logic . . . . . . . . . . 3.2.1 Notation . . . . . . . . . . . . . . 3.2.2 Radix and Complexity . . . . . . 3.2.3 Modes of Operation . . . . . . . 3.2.4 Noise Margins . . . . . . . . . . 3.2.5 Completeness . . . . . . . . . . . 3.2.6 MVL-Inverter . . . . . . . . . . . 3.2.7 Logic Operations . . . . . . . . . 3.2.8 Down Literal Circuits . . . . . . 3.2.9 Pass Gate Circuits . . . . . . . . 3.2.10 Voltage Comparators . . . . . . . 3.2.11 Max and Min Functions . . . . . 3.3 Measurement and Results . . . . . . . . 3.4 Summary . . . . . . . . . . . . . . . . .

CONTENTS

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4 TERNARY LOGIC 4.1 Introduction . . . . . . . . . . . . . . . . . . . . 4.2 The Balanced Ternary Numbering System . . . 4.3 Search Trees Using Balanced Ternary Notaion . 4.3.1 The More, Less or Equal (MLE) Circuit 4.4 Signal Refreshment . . . . . . . . . . . . . . . . 4.4.1 A Ternary Switching Element . . . . . . 4.5 Fault Tolerant Logic . . . . . . . . . . . . . . . 4.6 Measurement and Results . . . . . . . . . . . . 4.7 Summary . . . . . . . . . . . . . . . . . . . . .

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5 TERNARY ARITHMETICS 5.1 Introduction . . . . . . . . . . . . . . . . . . . 5.1.1 Balanced Ternary Addition . . . . . . 5.1.2 Balanced Ternary Multiplication . . . 5.1.3 Balanced Ternary Division . . . . . . 5.2 Balanced Ternary Adder Implementation . . 5.2.1 Fast Addition Using Balanced Ternary 5.3 A Balanced Ternary Multiplication Circuit . 5.4 Measurement and Results . . . . . . . . . . . 5.5 Summary . . . . . . . . . . . . . . . . . . . .

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6 CONCLUSIONS AND FUTURE WORK 6.1 Summary . . . . . . . . . . . . . . . . . . 6.1.1 Ternary Logic . . . . . . . . . . . . 6.1.2 Ternary Adder Structures . . . . . 6.1.3 Hardware . . . . . . . . . . . . . . 6.1.4 Results . . . . . . . . . . . . . . .

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CONTENTS 6.2

VII

Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7 PUBLICATIONS 49 7.1 PAPER I: Max and Min Functions Using Multiple-Valued Recharged SemiFloating Gate Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 PAPER II: A Novel Ternary Switching Element Using CMOS Recharged Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.3 PAPER III: A Novel Ternary More, Less and Equality Circuit Using Recharged Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.4 PAPER IV: Fault Tolerant CMOS Logic Using Ternary Gates . . . . . . . . 71 7.5 PAPER V: A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.6 PAPER VI: Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . 85 7.7 PAPER VII: A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A ADDITIONAL INFORMATION 99 A.1 Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.1.1 Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.1.2 The Prototype Printed Circuit Board . . . . . . . . . . . . . . . . . 102 B ABBREVIATIONS

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VIII

CONTENTS

Chapter 1

INTRODUCTION ”There’s many pleasant properties to balanced ternary arithmetic, and it just has this little problem that it’s easier to build binary than ternary, but if we had, you know, if it would turn out that chips would handle ternary just as well, then I think we’d all be using it.” - Donald Knuth, 2002 My research with floating gate transistors started back in 1998, with my master thesis ”Design of Low Voltage Analog Amplifiers Using Floating Gate Transistors” [24]. My Ph.D. thesis focuses on ternary applications, which is somewhere between the binary and the analog world. Ternary logic is a subset of Multiple-Valued Logic (MVL). MVL has in the last few decades been proposed as a possible alternative to binary logic. Whereas binary logic is limited to only two states, ”true” and ”false”, ternary logic has three states, ”true”, ”false” and ”unknown”. Multiple-valued logic is able to replace these with finitely or infinitely numbers of values. So why use ternary logic? It has been said, that the optimal numbering system is the base 3, depending on the use of hardware. When looking at the rw -product1 , we notice that if the rw-product is held constant, the optimal point is 2.71 -the natural logarithm (e). Base 3 is closer to 2.71828 than the binary numbering system, which uses base 2. This special property is not new for computer scientists; however it is difficult to build ternary hardware reliable. In 1958, Nikolai P. Brusenzov and his team constructed the world’s first and still unique ternary computer at the University of Moscow. It was named Setun, after a river floating through the campus, and confirmed that it was possible to build a ternary computer. Setun gained a lot of interest among western scientists. Unfortunately, the development of ternary architectures was not keeping up with the speed of the binary counterparts. Use of transistors have forced the developers to use binary solutions, because a transistor has two stable states; ”on” or ”off”. Somewhere between the two stable states, it is an analog state. Donald Knuth, a famous computer scientist who wrote ”The Art of Computer Programming”, said ”If it would have been possible to build reliable ternary architecture, everybody would be using it” [44]. This is one of my motivations to use Recharged Semi-Floating Gate (RSFG) technology to cope with balanced ternary logic. 1

r is the radix and w is the width of the word

1

2

CHAPTER 1. INTRODUCTION

By using this technology, we hopefully are one step closer to find a possible solution to a reliable ternary hardware. This thesis presents some novel applications to be used in MVL logic (MAX, MIN and NOT). A novel adder structure which can be used in balanced ternary ALU’s2 . A complete ALU is not presented, however some small bricks, which can be used for implementation, are covered in this thesis. The RSFG technology is a new approach, coping with ternary logic; however there are still several issues which need to be investigated closer into, in the future. This thesis only scratches the surface of MVL, but I hope my contributions one day will lead to a fully functional balanced ternary CPU. I point to my references for more detailed information of the MVL technology.

1.1

Main Contributions

The following section will give a survey of my contribution to ternary and multiple-valued logic. A list of my publications will follow and I will put them in the context of their research field, and there after give a short abstract of the papers.

1.1.1

List of Publications

PAPER I: Max and Min Functions Using Multiple-Valued Recharged SemiFloating Gate Circuits This paper is in the research field of Multiple-Valued Logic (MVL). It covers some elementary function used in multiple-valued logic; MAX, MIN, MV-Inverter, and the Down Literal Circuit (DLC). The main contribution of this paper is the realization of the functions using the recharged semi-floating gate transistor (RSFG) technology. The simulations results are done in a 350nm CMOS process. However, later I have implemented a MAX circuit using a 90nm CMOS process from STMicroelectronics. The result of the measurements of the MAX circuit is provided in Chapter 3. PAPER II: A Novel Ternary Switching Element Using CMOS Recharged SemiFloating Gate Devices My second paper is in the research field of ternary logic. Refreshing of signals is important when signals are interfaced with other devices in a large logic design. In the binary world an inverter can be used as a refresh element. In ternary logic a refresh element is more complex. This paper presents a novel refreshing method which hopefully can be used in ternary logic. The circuit is thoroughly analysed and simulation results are provided. PAPER III: A Novel Ternary More, Less and Equality Circuit Using Recharged Semi-Floating Gate Devices The third paper is in the research field of ternary logic. An optimal search-tree-structure is proven to be a balanced ternary tree structure. This paper presents a new comparison circuit which can be used in balance ternary search-tree-structures. This circuit compares 2

The ALU (Arithmetic Logic Unit) is the heart of a CPU, it does all the arithmetic operations in a modern CPU

1.1. MAIN CONTRIBUTIONS

3

two one trit numbers, and tells if it is equal-to, less-than or more-than. Simulation results in 90nm CMOS process is provided, the measurement of the circuit is presented in Chapter 4. PAPER VI: Fault Tolerant CMOS Logic Using Ternary Gates This paper is in the research field of ternary logic. This paper presents some methods to reduce effects of defects which appear in the manufacturing of large VLSI/ULSI circuits. Use of capacitors in the VLSI design could introduce better fault tolerance. In a floating gate design, capacitors are introduced. This will reduce the effect of DC shift on the input of the devices. Therefore stuck-at, stuck-on and stuck-off faults3 will not be destructive when redundancy is applied. PAPER V: A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices The fifth paper is in the research field of ternary arithmetic. A novel ternary full adder, which uses balanced ternary notation, is presented. The adder is realized by using RSFG transistors. This was my first attempt; to realize a fully functional balanced ternary adder. The simulation results are promising, however the measurements which are supported in Chapter 5, shows there is still improvement to be done. Later the adder is modified and the new adder structure is used in PAPER VI and PAPER VII. PAPER VI: Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices Paper six is in the research field of ternary arithmetic. The use of counters introduces many opportunities to make efficient adder structures. This paper is a further development of the adder presented in the previous, PAPER V. The adder structure is named counter instead of adder. The balanced ternary (BT) counters can be used in almost every adder structure, which makes these counters as a very important brick in ternary arithmetic circuits. The paper gives examples of Wallace tree structures and (13,3) counters, made by using simple BT counters. Paper six also compares a traditional binary adder structure with a BT counter structure, which shows the advantage to achieve when using BT counters in the aspects of resolution and power consumption. PAPER VII: A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices This publication is in the research field of ternary arithmetic. The paper presents a possible implementation and examples of a complete multiplication circuit, using balanced ternary architectures. It also shows that it is possible to multiply both negative and positive numbers using the same architecture. The outcome will lead to faster multiplication circuits, and less complex architectures.

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Stuck-xx-faults can be seen as defects in this context

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1.2

CHAPTER 1. INTRODUCTION

Overview of the Thesis

The thesis consists of three parts. Part 1; chapter 1-6, which is the main thesis, Part 2; chapter 7, which is the total amount of publications, and Part 3; Appendix, which covers measurement information. CHAPTER 1 - INTRODUCTION Gives a brief introduction and motivation for the thesis. CHAPTER 2 - FLOATING GATE TRANSISTORS Presents the floating gate (FG) transistor technology, the early history to future trends. In addition a detailed focus into non-volatile and volatile FG structures. Some fundamental volatile FG circuits are presented. Furthermore some measurements and analyses of a 90nm CMOS process are presented. [PAPER II, III, V] [31, 29, 28]. CHAPTER 3 - MVL TECHNOLOGY Presents the fundamental theory and history of the MVL technology, this chapter gives an overview of the proposed MVL circuits. Deeper evaluation of the applications is presented in the papers. My contribution to MVL are covered in the papers [PAPER I, II] [26, 31]. CHAPTER 4 - TERNARY LOGIC Presents the ternary logic historically and furthermore the focus I think will be present in the future. My proposed applications focus on design using RSFG-CMOS technology. A comparison circuit and a refreshing element are presented; the functionality is briefly covered. Aspects of fault tolerance in ternary logic are discussed. The following articles cover my contribution to ternary logic, and give a more thoroughly presentation of the proposed circuits. [PAPER II, III, IV] [31, 29, 9]. CHAPTER 5 - TERNARY ARITHMETICS Presents some simple novel ternary arithmetic applications, which I will claim as my main contribution to ternary logic. An analyse and characterization of the results are presented, while a complete analysis is given in the published papers [PAPER V, VI, VII] [27, 28, 30]. CHAPTER 6 - CONCLUSIONS AND FUTURE WORK Gives a summary and presents the conclusion of the thesis. CHAPTER 7 - PUBLICATIONS Is a collection of the published articles, giving the base for the thesis. APPENDIX - ADDITIONAL INFORMATION Supports measurement information of the prototype chip.

Chapter 2

FLOATING GATE TRANSISTORS ”Use of volatile floating-gate transistors shows large potentials in the ease of operating of the floating-gate voltage. To fully use this advantage, may give a new branch of floating-gate circuits.” - Øivind Næss, 2005

2.1

Introduction

Floating-Gate MOS transistors have been used for several years to store digital information in EPROMS, EEPROMS and flash memories [68]. The first floating gate structure reported, used in a memory application, was in 1967 by D. Kahng together with S.M. Sze . It was a non-volatile storage information mechanism [42]. However, as stated in the article by V. Beiu et al. [4], as early as in 1966, the first CMOS capacitive solution was patented by Burns and Powlus, figure 2.1 (a) [15]. In 1992 Shibata and Ohmi rediscovered and improved the method of using multiple inputs to a floating gate transistor, figure 2.1 (b) [63, 64]. The floating gate voltage was established as a weighted capacitive voltage summation. This way of using the floating gate, introduced some interesting analog and digital information-processing circuits. Foe example D/A converters [64] and multiple-input floating gate amplifiers [74]. Shibata and Ohmi named these devices neuMOS transistors. Yang, Andreou and Boahen named it Multiple-Input Floating-Gate Transistors, FGMOS [74]. The interest of using FG transistors started at University of Oslo back in the early 1990s, with the use of FG transistors as an analog memory in neural nets. One problem with floating gate is, after the fabrication processes some charges are left in the floating gate, thereby causing fluctuations of inversion threshold from device to device. To remove this charge Shibata proposed to use UV (UV light) irradiation technique to remove the charge, this is a well known method used in EPROM erasing [65, 66]. A further improvement was exploited in 1996, at the University of Oslo, where a new programming scheme of floating gates was developed by T. S. Lande et al. by using UV light to fully program the FG circuits [47]. It was further improved by Y. Berg et al. in 1997 [10]. This method is called FGUVMOS programming scheme. 5

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CHAPTER 2. FLOATING GATE TRANSISTORS

(a) First CMOS capacitive solution, 1966 [15]

(b) Neuron 1991 [63, 64]

MOSFET

(neuMOS),

Figure 2.1: Floating gate structures

2.2

Floating Gate (FG) MOS Transistor

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), also called a MOS transistor, operates on the conductivity modulation principle in a thin semiconductor layer, using a controlling electric field to give amplifying and switching functions between two of the three electrical terminals (gate, drain and source). The history of the MOS transistor goes back to 1926. The principle of operation was first presented by Lilienfeld [50]. In the 60s almost all the integrated circuits used bipolar transistors. Bipolar transistors were around 100 times faster than MOS transistors, however they consumed more amount of power, required more silicon area, and used a much more complicated and costly manufacturing process. In the 70s, development of MOS technology grew rapidly and replaced bipolar technology as the vehicle of choice for complex integrated circuits, and it became a commercial success with the introduction of memory- and µprocessor circuits. Today it dominates the production of VLSI circuits in the electronic industry. A FG transistor is a regular MOS transistor, where the input gate is capacitive coupled, and the gate node is not externally connected. This gives the same operation regions, current and intrinsic capacitances as an ordinary MOS transistor. The gate voltage is dependent of the initial charge and the input voltage of control gate. It is possible to have multiple input signals as shown in figure 2.2. The output voltage (Vout ) will be a function of the input voltages, based on the capacitive voltage division model described in 2.2.2.

2.2. FLOATING GATE (FG) MOS TRANSISTOR C1

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Vd

V1

Idsn C2

V2

Vfg


Ci Vi Vs

Figure 2.2: A n-input NMOS FG transistor

2.2.1

The Floating Gate Capacitors

Interpoly Capacitors Interpoly Capacitors are capacitors implemented by using two layers of polysilicon on top of each other. The first two papers are using a 350nm CMOS process from AMS, which provides Poly1 and Poly 2 layers, making it suitable for interpoly capacitors used by FG transistors. This is why interpoly capacitors where used in the initial circuit designs [PAPER I, II] [26, 31]. Metal-to-Metal Capacitors Recent CMOS processes have several metal layers. STMmicroelectronics 90nm process supports 7 metal layers, but this process has one single poly layer, which is the reason why I decided to use Metal-to-Metal capacitors. These capacitors have less capacitance/mm2 and use more space than a similar interpoly capacitor. By using stacking we able to reduce the area which we need in order to build a capacitor, since 7 metal layers are available. The capacitors in this thesis are planar capacitors and do not take advantage of total stacking. MOS Capacitance By using the gate as one plate, and the drain-source channel as the second one, it is possible to make a MOS capacitance device. It is important to keep the transistor in strong inversion to maintain linearity of the capacitance [49].

2.2.2

Capacitive Voltage Division Model

The voltage of the floating gate shown in figure 2.2 is dependent of the initial charge and a weighted sum of all inputs. A simple floating gate voltage can be expressed as follows: Vf g =

Ci Vi + C2 V2 + .... + Ci Vi CT

(2.1)

where CT is the total capacitance seen from the floating gate. This model is derived from a small signal analysis hence Vd = Vs = gnd. Using a more comprehensive model, including

8

CHAPTER 2. FLOATING GATE TRANSISTORS

the parasitic capacitances. Figure 2.3, gives the following floating gate voltage: Vf g

P

Cox ψs + Q + in=1 Cn Vn + Cf s Vs + Cf d Vd = P Cox + Cb + Cf s + Cf d + in−1 Cn

(2.2)

Where ψ is the surface potential in the channel, Q is the net charge stored on the floating gate. The surface potential ψ is a slowly varying function of the gate voltage, and can be simplified to the expression using the two first terms in a taylor serie: ψ ≈ ψ0 + κVf g Where κ = ψ=

Cox Cox +Cdep

=

1 n

ombining the equviations 2.2 and 2.3 gives

Cox + Cf b + Cf s + Cf d + CT

Where CT =

Cox Cdep Cox +Cdep

(2.3)

Pi

n=1 Cn

ψ0 +

+ Cf b + Cf s + Cf d + C1

Cfd

n=1 Cn Vn

+ Cf s Vs + Cf d Vd (2.4) CT

n=1 Cn .

C1

Cfd Q

V1

 

Pi

Pi

Vd

Q

V1

1Q+ n

Vd



Ids C2 V2 Ci Vi

V2 Cfs

Cfs

Ci

Vs

(a) Schematic

Cdep



Vi

 

Cfb

Cox Vfg

C2

Vfg  



Vs

Cfb

(b) Equvialent model

Figure 2.3: Capacitive division model, (a) Schematic of the transistor model with the parasictic capacitors included. (b) Equivalent capacitive divider model

2.2.3

Charge Loss on the Floating Gate Node

Aggressive downscaling of the transistor gate, and thinner gate oxide, makes it difficult to make a genuine floating gate device. In a 90nm process, the gate dielectric SiO2 is in the range of 12-16˚ A(1.2-1.6 nm) [48], which results in a constant gate tunnelling leakage current. Measurement on the the 90nm CMOS process from STMicroelectronics shows If g typical 1nA [34]. The leak current will make a constant charge loss. This makes it difficult to produce genuine floating gate transistor structures. To solve this problem a novel recharge scheme of the floating gate must be exploited. The problem is discussed in section 2.4.

2.2. FLOATING GATE (FG) MOS TRANSISTOR

2.2.4

9

Inverter Based Structures

A traditional CMOS digital structure uses stacking of more than two transistors to make a logical port. By using the floating gate technology this is not necessary. All structures uses height of two, a PMOS stacked on a NMOS. The functionality of the digital logic is made by capacitive division.

2.2.5

Split-Gate Inverter Structure

A split gate inverter structure has a separate capacitor of both the NMOS- and the PMOS transistor as shown in figure 2.4 a). A split gate structure can use minimum length and width NMOS and PMOS transistors. By using an appropriate programming technique of the floating gate of the NMOS and PMOS transistor, it is possible to compensate for the different βs of these transistors [13].

2.2.6

Common Gate Inverter Structure

A common gate structure has a common capacitor connected to both gates of the NMOS and the PMOS, as shown in figure 2.4 b). In a common gate structure the NMOS and PMOS has to be matched. In the STMicroelectronic 90nm process the PMOS has to be ≈ 3.5 times the width of the NMOS, due to the mobilityfactor(µ) of electrons. It also reduces the area needed for the capacitors, compared to a split-gate structure.

Cip

Ci VIN

 

 

VOUT VIN

 

 

VOUT

Cin

(a) Split gate inverter structure

(b) Common gate inverter structure

Figure 2.4: Gate structures used in FG technology

10

2.3

CHAPTER 2. FLOATING GATE TRANSISTORS

Non-Volatile FG Transistors

Floating gate transistors need a programming technique to control the charge of the floating gate. Non-Volatile FG or genuine Floating Gates [51] are structures where the gate are only connected to capacitors, as mentioned in section 2.2.3. In newer CMOS technology with thin gate oxide, SiO2 , there is a constant gate tunnelling current leakage, which makes it difficult to make a Non-Volatile FG structure. To solve this problem the gate oxide has to be a high resistance material (High-k dielectric), or it is possible to use an older CMOS process technology. In 2004, Intel demonstrated a 0.8 nm physical SiO2 in their research laboratory. Although transistors with the 0.8 nm gate oxide still show the expected device characteristics, the gate dielectric has become so thin that we are literally running out of atoms for further scaling [16].

2.3.1

Fowler Nordheim Tunneling

Fowler Nordheim tunnelling is a post programming process for FG structures. It is a well known method for a charge transport through the silicon dioxide. This technique was discovered as early as 1928 when researchers Ralph H. Fowler and Lothar W. Nordheim, who gave the name to this method, discovered that electrons with sufficient electronic field can tunnel through an energy barrier [22]. This method makes it possible to program the FG. However, as a result of the high voltage required, the SiO2 will gradually break down, resulting in leakage through the dioxide.

2.3.2

Hot Carrier Injection

Hot carrier injection, or hot-electron injection, is another method for controlling the charge of the floating gate. Hot carrier injection is the phenomenon in solid state devices or semiconductors where either an electron, or a ”hole”, gains sufficient kinetic energy to overcome a potential barrier, resulting in a ”hot carrier”, and then migrates to a different area of the device [19]. The term usually refers to the effect in a MOSFET where a carrier is injected from the silicon substrate to the gate dielectric. For a SiO2 dielectric, to enter the conduction band of the dielectric, an electron must gain a kinetic energy of 3.3eV .

2.3.3

UV Activated Programming

UV Activated Programming is a method explored at the university of Oslo in 1996 [47]. The advantage of the UV-activated mechanism is that the programming can be done without any high voltage or a special CMOS process. The UV programming is discussed in detail in my master thesis [24], and by Snorre Aunet in his Dr. Scient thesis ”Real-time Reconfigurable Devices Implemented in UV-light Programmable Floating-Gate CMOS” [3].

2.4. VOLATILE FG CIRCUITS

2.4

11

Volatile FG Circuits

Floating gate circuits need to be initialized, either once initially or frequently. The once and for all initialization is synonymous with programming. By recharging the floating gate frequently, we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges. The reset or recharge scheme can be used to overcome some problems associated with floating-gate circuit design [5]. Thin gate oxide in modern CMOS processes makes it almost impossible to make a genuine floating gate structure, because of the constant gate current leakage (as discussed in 2.2.3). Volatile Floating gate transistors are not genuine floating gates, since the gate node is not completely isolated. There are several methods to maintain the charge on the floating gate node, pseudo, semi, recharged or a combination. The methods are discussed in the following section.

2.4.1

Recharged Floating Gate

Recharged floating gate is also known as switched or clocked floating gate transistors. This method was presented by Kotani et al. in 1998 [45]. It makes it easy to control the charge on the floating gate. However, the transmission gate used for the clocking introduces a constant leakage current. This makes the circuit more suitable to be used in digital applications, with sufficient clock frequency.

2.4.2

Pseudo Floating Gate

Instead of using a switch to control the floating gate, a very large valued resistor (quasi/pseudo infinite device) is introduced. This method was first presented at the IEEE Midwest Symposium on Circuits and Systems in 2002 [71], and is discussed in the IEEE Transactions on Circuits and Systems-II journal in 2003 written by Ramirez-Angulo et. al. [58]. At the University of Oslo the use of this method has been exploited by Ø. Ness [52] and is discussed in detail his Ph.D. thesis [51]. The advantage of this method is the fact that the floating node is set to a well defined operation point without any post-processing. Since there is no clock switching, this method is also applicable in analog FG circuits.

+ CLK

Pe Ci

VIN

Ci

+ CLK  

 

 

 

VOUT

VIN



 

 

 

VOUT

Ne

Figure 2.5: A typical recharged semi-floating gate binary inverter.

12

2.4.3

CHAPTER 2. FLOATING GATE TRANSISTORS

Recharged Semi-Floating Gate

This recharge strategy is slightly different than the reset condition in clocked-Neuron-MOS logic proposed by Kotani et.al. [45]. This is the reset scheme that is presented in this Ph.D. thesis. When resetting or recharging a gate, the inputs are recharged simultaneously and not set to a reference voltage, normally Vss or Vdd . By using a common gate inverter based structure, figure 2.5, when being in recharge mode, the gates are short-circuited and the output and the semi-floating-gate of a logic gate is forced to V2dd . The recharge scheme is similar to biasing single-ended auto-zeroing comparators which have been used in highspeed flash AD converters. The main purpose of the recharge scheme is to initialize, or recharge the semi-floating-gates, to an equilibrium state which can be utilized to yield fast binary and multiple-valued signal processing. In addition, we may reduce the effect of mismatches, especially transistor mismatches, and power supply noise. The recharge scheme provides a simple, fast and accurate recharge to the equilibrium state for all gates regardless of logical depth. We use the term Recharge Logic (RL) or Recharge SemiFloating-Gate Logic (RSFGL) for the circuits used in this thesis [8]. The SFG circuits are recharged to the initial equilibrium state, namely V2dd . A simple binary single input gate, namely an inverter, is shown in figure 2.5. By equalizing the transfer parameters βn and βp of the N- and P-transistor, we obtain an equilibrium state when the recharge clock is 1. The output and gate are driven toward Vdd 2 . When the recharge clock is 1, we have two distinct cases. Assuming that the input signal is initially 1 (Vdd ), the SFG voltage can be expressed as ( V2dd ) x ( 1 + ki ), where ki = Ci /Ct and Ct is the total capacitance seen by the SFG, and the output is equal to 0. The output and the SFG will be forced toward V2dd simultaneously. The recharge current which will pull the SFG down towards V2dd , is larger than the equilibrium current (Ibec ). We define the recharge rise time tr as the time required to recharge the output from 0 to Vdd Vdd 2 (and the SFG simultaneously). If the input signal is initially 0 the SFG voltage is ( 2 ) x (1 - ki ) and the output is 1. The recharge current will be reduced compared to the former case, due to body effect of the n-channel recharge transistor. In order to achieve a correct recharge to the equilibrium state in a chain of gates, we need to recharge all gates and all inputs simultaneously. Additionally, we need to develop a synchronization scheme for the recharge. We define the recharge fall time tf as the time required to recharge the output from 1 to V2dd . The recharge frequency is twice the frequency of the input signal. By recharging the semi-floating-gate (SFG) we do not only avoid the problems linked to programming or initializing of the floating gates, instead we do convert the non-volatile floating gates to semi-floating-gates. The control of the actual floating gate charges, in terms of predictable long term charge restoration, becomes easier. The SFG is not influenced by a random FG charge distortion due to a periodic or frequent charge restoration or reset. The recharge of the SFGs is accomplished by a local recharge transistor or a pass gate temporarily connecting the output to the floating gate of a gate [6].

2.4.4

Clock Generator

Recharged Semi Floating Gate circuits need a recharge scheme. This is the reason why we need a clock generator to generate the refresh clock. An example of a simple clock generator is shown in figure 2.6. A simple clock generator can be made by using three

2.5. AUTO-ZERO ELEMENT

13

inverters [PAPER III] [29]. This simple clock generator generates the two clock phases +CLK and −CLK, the characteristics are shown in figure 2.7. The reference clock could be any periodic signal, for instance a sinus signal. The clock generator should have the driving possibility of driving several circuits, and therefore the transistors have to be wider than minimum. REF

 

− CLK

+ CLK

Figure 2.6: A simple clock generator.

2.5

Auto-Zero Element

The Auto-Zero element (AZE) can be seen as a signal converter [PAPER II, III, V] [31, 29, 28]. By using the AZE we are able to use DC signals in addition to a conventional binary signal as input to the FG circuits. When interfacing with a binary signal the clock frequency has to be twice the input frequency of the binary signal. Examples of auto-zero elements are seen in figure 2.8. Figure 2.8 (a) consists of two pass gate circuits which is opposite clocked. The upper has V2dd as input, the lower Pass Gate circuit has the input signal Vin as input. Measured typical output characteristics of the circuit in figure 2.8 (a) is presented in figure 2.10 and figure 2.11. The discussion of the results is focused in section 2.7. Figure 2.8 (b) shows another solution. It has stacked transistors, resulting in limitations on use in very high frequency applications, due to body effect. The N and P transistors (diode coupled) connected to the rails need to have matched transfer parameters (βn and βp ). The two solutions uses an equal amount of transistors, because the V2dd input on a) is made using a diode coupled N and P transistor.

2.5.1

Removing the Auto-Zero Clock Signal

When interfaced with other logic components, which is not RSFG compliable, we need to remove the recharge clock. This can be done using a recharge-remover as shown in figure 2.9. This makes it simple to implement the RSFG circuits in any logic design.

2.6 2.6.1

Limitations Using 90nm CMOS Technology Max Clock Frequency

The simulation result I have done of the 90nm CMOS process from STMicroelectronics shows that switching at ≈ 10GHz of binary inverters is possible to achieve. However, due to total load capacitance of the FG devices, the frequency of the presented RSFG circuits in this thesis is limited to MAX 2GHz. The applications used in this thesis are designed for 1GHz switching frequency at a load of 10fF.

14

CHAPTER 2. FLOATING GATE TRANSISTORS

REF

0.5 0 −0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10 − CLK

0.5 0 −0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10 + CLK

0.5 0 −0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

Figure 2.7: Characteristics of the simple clock generator implemented in 90nm CMOS technology, the reference clock is 1 GHz

2.6.2

Parasitic Capacitance

When designing a MOS Transistor in a VLSI design, there are many non-desirable effects to consider. One of these effects is the parasitic capacitance. Most of this effect is taken into consideration in the different simulation models (ie. BSIM3 Spice models). There are major parasitic capacitances between metal layers, so thoroughly routing is of significant value. In the CMOS transistor itself, the most dominant parasitic capacitance is the gate capacitance Cgtot = Cgd + Cgs , in the 90nm this is in a order of ≈ 1fF. This means that the input capacitor (Ci ) of the FG circuit, has to be more than Cgtot . The other overlap capacitance Cdb + Csb B the output is −1. II. F UNDAMENTAL B UILDING BLOCKS USED IN R ECHARGE S EMI -F LOATING G ATE (RSFG) D ESIGN This paper will not cover the fundamental theory of RSFG devices [3]. It is only the building blocks used in the ternary MLE circuit that will be focused in this paper. 1 The performance number gives the average choices you have to go through to find the right choice.

TABLE I T HE TRUTH TABLE OF THE TERNARY M ORE , L ESS AND E QUALITY (MLE) CIRCUIT

-1

0

1

-1

0

1

1

0

-1

0

1

1

-1

-1

0

A. Floating Gate Transistors The multiple-input FG transistors can be used to simplify the design of multiple-valued logic [4]. The initial charge on the floating-gates may vary significantly and therefore impose a very severe inaccuracy, unless we do apply some form of initialization. Some work on floating-gate reset strategies have been presented by Kotani et.al. [5], and by Berg et.al. [3]. B. Recharge Semi-Floating Devices As mentioned, FG circuits need to be initialized, either once initially or frequently. The once and for all initialization is synonymous with programming. By recharging the SFG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges. The reset or recharged scheme can be used to overcome some problems associated with the floating-gate circuit design [3]. The recharged condition is different than the reset in clocked-Neuron-MOS logic proposed by Kotani et.al. [5]. When reseting or recharging a gate, the inputs are recharged simultaneously and they are set to a reference voltage, normally Vdd /2. While recharging, the gates are short-circuited and the output and the semi-floating-gate of a logic gate is forced to Vdd /2. The recharged scheme is similar to biasing of single-ended auto-zeroing comparators, which have been used in highspeed flash AD converters. The main purpose of the recharged scheme is to initialize or recharge the semi-floating-gates to an equilibrium state, which can be utilized to yield fast binary and multiple-valued signal processing. In addition we may reduce

the effect of mismatches, especially transistor mismatches, and power supply noise. The recharged scheme provides a simple, fast and accurate recharge to the equilibrium state for all gates regardless of logical depth. We use the term Recharged Logic (RL) or Recharged Semi-Floating- Gate Logic (RSFGL) for the circuits presented in this paper [6]. The SFG circuits are recharged to the initial equilibrium state, namely Vdd /2 or Gnd, since the supply voltage is +/- 0.5 Volt. C. The simple clock generator All RSFG devices uses a clock scheme, to generate the precharge and recharge period [7]. The ternary MLE circuit uses a simple clock generator, figure 1, to generate an inverted and a non-inverted clock pulse. The clock generator circuit uses three minimum sized inverters.

REF

a valid recharge signal [8]. The AZC has two Pass-Gate Circuits, clocked with opposite clock phase. The upper Pass-Gate Circuit in figure 3 has VDD 2 (Gnd) as input, and the lower Pass-Gate circuit has VIN as input. In the recharge period the upper Pass-Gate circuit will set the output signal VOU T and it will be set to Gnd, since the supply voltage is +Vdd and -Vss . In the precharge period, determined by the lower Pass-Gate circuit, the output signal VOU T will be equal to VIN . Examples of input and output signals from the Auto-Zero Circuit (figure 3) are shown in figure 4. This figure shows the two inputs, VIN 1 , and VIN 2 and the two Auto Zeroed outputs VOU T 1 and VOU T 2 , which will be the inputs to the RSFG devices. The input signals are stairs signals, with three significantly levels (Ternary signals).

− CLK + CLK

+ CLK + CLK

Ne

Fig. 1. Schematic diagram of the simple Clock Generator Circuit. The design comprises three inverters coupled in series. The transistor sizes are P e (w=460nm, l=100nm) and N e (w=120nm, l=100nm)

VDD/2 Pe

VOUT VIN

− CLK

Ne

0.5 REF

VOUT

AZC

VIN

0

Pe − CLK

−0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10 − CLK

0.5

+ CLK

Fig. 3. Schematic diagram of the Auto-Zero circuit. The transistor sizes are P e (w=130nm, l=100nm) and N e (w=130nm, l=100nm)

0 −0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

0.5 VIN 1

+ CLK

0.5 0

0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

−0.5 0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

Fig. 2. A plot of the input and output signals from the simple Clock Generator Circuit in figure 1

VOUT 1

0.2

0.5 0 −0.5

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10 VOUT 2

Figure 2 shows the characteristics of the simple clock generator in figure 1. The non-inverted clock pulse is the output of inverter #2 (+ CLK) and the inverted clock pulse is the output of inverter #3 (- CLK). The input reference clock is a 1 GHz sinus-wave (REF).

0

x 10 VIN 2

0

x 10

0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

D. The Auto-Zero Circuit (AZC) The input stage of an RSFG device needs an Auto-Zero Circuit as shown in figure 3. An Auto-Zero circuit can be seen as a signal converter, which converts an input signal to

Fig. 4. Plots of the input and output signals from the Auto-Zero Circuit in figure 3.

+ CLK 0.5

Cf

Pe

Ci VIN

VIN

+ CLK

Ci Cf

VOUT VIN

0

VOUT −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

Ne

x 10

Fig. 5. Schematic diagram of the Semi Floating Gate MVL inverter, which generates the Ternary NOT function. The transistor sizes are P e (w=460nm, l=100nm) and N e (w=120nm, l=100nm) Ci = 2f F, Cf = 1f F

VOUT

0.5

0

−0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

E. The Recharge Semi-Floating Gate (RSFG) Ternary Inverter The Recharge Semi-Floating Gate (RSFG) MVL inverter [7] in figure 5 is an important application, it can generate the NOT function in ternary logic. A truth table of a Ternary NOT function is shown in table II. In order to make voltage TABLE II

Out

-1

1

0

0

1

-1

mode multi-valued signal, high accuracy and linearity is necessary, since the voltage levels for each level is an equal division of the supply voltage. This is the reason why the MVL inverter is a key element in Multi-Valued Logic [3]. A MVL inverter, also called an analog inverter, is an inverter with a negative feedback mechanism (Cf ). The voltage gain T = −1. The voltage gain is of this circuit is Av = VVOU IN determined by the capacitive division factor ki and kf ( Cf Ci and kf = Ctotal ). The transfer characteristic is ki = Ctotal given by equation 1. VIN and VOU T are the voltages on the input and the output terminals. VDD is the supply voltage [9]. VOU T = VDD − VIN

III. T HE T ERNARY M ORE , L ESS AND E QUALITY (MLE) C IRCUIT The Ternary More, Less and Equality (MLE) circuit in figure 7 has two inputs, VIN 1 and VIN 2 . It is made of two Auto-Zero Circuits (AZC) and two ternary inverters (Ternary NOT).

T HE TRUTH TABLE OF THE TERNARY NOT FUNCTION

In

Fig. 6. A plot of the input (Vin ) and output (Vout ) signals from the SemiFloating Gate MVL Inverters in figure 5, which shows the Ternary NOT function.

(1)

Ideally Ci = Cf , however Cf has to be smaller than Ci due to the output conductance and the parasitic capacitance, Cgd [9]. The ternary input signal (VIN ) and the ternary output signal (VOU T ) are shown in figure 6. The input signal is a 9 trits2 word (-1 -1 -1 0 0 0 1 1 1) and the output word is (1 1 1 0 0 0 -1 -1 -1) which corresponds with the truth table of the Ternary NOT function, shown in table II. 2 One trit has 3 values, the values are (-1, 0, 1), it is analogous to bit in the binary world (0, 1).

The two inputs VIN 1 and VIN 2 are stairs signals as shown in figure 4. The input signals go through an Auto-Zero block (AZC) , the Auto-Zero Block is seen in figure 3. The AZC is clocked with +CLK and −CLK from the simple Clock Generator, the two inverters are clocked with +CLK to operate as inverters. If they where clocked with −CLK it would have been a latch element [10]. The input vector 1 and input vector 2 are balanced ternary signals. VIN 1 is (-1 0 1 -1 0 1 -1 0 1) and VIN 2 is (-1 -1 -1 0 0 0 1 1 1). Both input signals are Auto Zeroed (INPUT 1 and INPUT 2). The signal amplitude is +/- 0.4V olt, supply voltage is +/- 0.5V olt. This gives us a dynamic voltage range of 80%. The ternary MLE circuit is made with only to ternary inverters as shown in figure 7, which comprise a compact design. The output of the MLE circuit is defined by equation 2: OU T P U T = N OT (IN P U T 1 − IN P U T 2)

(2)

This is achieved by using a ternary NOT function on INPUT 2, which is a ternary inverter with voltage gain Av = −1. The output stage of the MLE circuit is a two input Ternary NOT with voltage gain Av = −2. The output is the inverted SUM of the two inputs (see equation 2). The output gain is -2, because logic levels “1” should be “-1” not ”- 12 ”. 4 Ideally C5 = C3 +C but due to the output conductance and 2 the parasitic capacitance Cgd , mentioned in section II-E, 4 C5 = C3 +C . The output vector in figure 8 is (0 -1 -1 1 0 -1 4

1 1 0) which verifies the truth table of the presented MLE circuit shown in table I. The logic levels at the output, (see figure 9), are within their boundaries. The boundaries for logic level “-1” are between -500mV and -300mV. Logic level “0” is defined when the boundaries are -150mV to 150mV, and for logic level “1” it is 300mV to 500mV. This means if the output signal is within these boundaries, the logic levels are recognized. If the output signal are between 150mV to 300mV and -300mV to 150mV the signal is undefined. In order to have a well-defined balanced ternary signal, the output signal can be refreshed using a Ternary Switching Element [8]. After the refreshing element the signal will be in the middle of their boundaries.

AZC

INPUT 1

0.3 0.2 0.1

0

0 −0.1 −0.2 −0.3

−1

−0.4 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

+ CLK + CLK

− CLK

Clock Generator. The supply voltage is only +/- 0.5 Volt. This circuit is a fundamental building block in a fast ternary search tree structure.

C5

C2

C3

+ CLK C1

VIN 2

1

0.4

Fig. 9. The noise margins, which shows the boundaries for the logic levels.

+ CLK

VIN 1

0.5

OUTPUT

C4

AZC INPUT 2 INPUT 2 INV − CLK

Fig. 7. Schematic diagram of the Ternary More, Less and Equality (MLE) circuit. The transistor sizes are P e (w=460nm, l=100nm) and N e (w=120nm, l=100nm), C2 , C5 = 1f F and C1 , C3 , C4 = 2f F .

The More, Less and Equality (MLE) Circuit has been evaluated with Cadence
R Analog Design Environment, by using the CMOS090 GP process parameters from STMicroelectronics, this is a 90nm General Purpose Bulk CMOS Process with 7 metal layers. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates.

INPUT 1

R EFERENCES 0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

INPUT 2 INV

INPUT 2

x 10 0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10 0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

OUTPUT

x 10 0.5 0 −0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

Fig. 8. A plot of the input and output signal from the More, Less and Equality (MLE) Circuit in figure 7.

IV. C ONCLUSIONS In this paper a novel ternary More, Less and Equality (MLE) Circuit has been presented. It has a compact design with only two ternary inverters. It operates with a clock frequency at 1 GHz. The total power dissipation is less than 200µW att, including the Auto Zero Circuit and the Simple

[1] B. Hayes, “Third Base,” American Scientist, Volume 89, Number 6, pp. 490–494, Nov-Dec 2001. [2] D. Knuth, The Art of Computer Programming, Second edition. AddisonWesley Publishing Company, 1981. [3] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin, “Novel Recharge Semi-Floating-Gate CMOS Logic For Multiple-Valued Systems,” Proceedings of the 2003 IEEE International Symposium on Circuits And Systems in Bangkok, 2003. [4] T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring GateLevel Weighted Sum and Threshold Operations,” IEEE Transactions on Electron devices, vol. 39(6), pp. 1444–1455, 1992. [5] K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked NeuronMOS Logic Circuits Employing Auto Threhold Adjustment,” IEEE International Solid-State Circuits Conference(ISSCC), pp. 320–321,388, 1995. [6] Y. Berg, S. Aunet, Ø. Næss, O. Mirmotahari, and M. Høvin, “Binary to Multiple-Valued Recharge Converter for Multiple-Valued CMOS logic,” ECCTD’03-Euopean Conference on Circuit Theory and Design,Cracow, Poland, pp. 349–352, 2003. [7] H. Gundersen and Y. Berg, “MAX and MIN Functions Using MultipleValued Recharge Semi-Floating Gate Circuits,” Proceedings of the 2004 IEEE International Symposium on Circuits And Systems in Vancouver, 2004. [8] Y. Berg and H. Gundersen, “A Novel Ternary Switching Element Using CMOS Recharge Semi-Floating Gate Devices,” Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic in Calgary, pp. 54 –58, May. 2005. [9] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen, “Ultra-Low-Voltage Floating Gate Transconductance Amplifiers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001. [10] O. Mirmotahari and Y. Berg, “A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic,” Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic in Tokyo, pp. 135– 138, 2003.

7.4

PAPER IV: Fault Tolerant CMOS Logic Using Ternary Gates

Yngvar Berg, Rene Jensen, Johannes Lomsdalen, Henning Gundersen and Snorre Aunet Department of informatics, University of Oslo Proceedings of 37th International Symposium on Multiple-Valued Logic, ISMVL, Oslo Norway, May 14-15, 2007, ISBN 0-7695-2831-1

71

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Fault tolerant CMOS logic using ternary gates. Yngvar Berg, Rene Jensen, Johannes Lomsdalen, Henning Gundersen Snorre Aunet Microelectronic Systems Department of Informatics University of Oslo Oslo, Norway Email: [email protected]

Abstract In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130nm and 0.35µm CMOS processes are given.

2 Faults and redundancy In this section we will discuss briefly common CMOS failures[3]. The failures considered are • Stuck-at faults. – Stuck at VDD (SA1). A node is assumed to be stucked at VDD independently of signal values or other failures. We assume that the node will not be affected by currents pulling the the node towards gnd. The failures can be caused by defect pMOS transistor(s) pulling a node to VDD with a current larger than the ON current provided by operative transistors. – Stuck at gnd (SA0). A node is assumed to be stucked at gnd independently of signal values or other failures. We assume that the node will not be affected by currents pulling the the node towards VDD .

1 Introduction

The technology trend introduces a wide variety of problems related to reliability of circuits. The ever increased integration of devices on a single die raises the probability of erroneous components in the die. The increasing probability of faults in a circuit increase the demand of fault tolerant logic. The most reasonable way to overcome the reliability problems is to build fault tolerant circuits. Floating-gate CMOS[1] can be used to overcome some of the problems due to stuck-at failures. In this paper we present a ternary logic gate which is fault tolerant. I section II we discuss briefly some common faults in CMOS circuits, and in section III we introduce a semi-floating-gate[2] (SFG) majority-3 (MAJ3) ternary inverter which reduces the effect of faults compared to standard CMOS gates. In section IV we present a fault tolerant redundant ternary SFG gate.

• Stuck-open faults. – MOSFET stuck-open (SOFF). A transistor that can not be turned on, is assumed to deliver a minimum current given by the OFF state of a transistor. – Interconnect stuck-open (IOFF). Floating nodes. Normally modelled by unconnected transistor terminals. An unconnected gate terminal may be equivalent to a SOFF or even a SON failure. • Stuck-closed faults.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

– MOSFET stuck-closed (SON). A transistor that can not be turned off, is assumed to deliver a maximum current given by the ON state of a transistor.

C X

X F

F

C x

x (a)

(b)

Figure 1. Redundancy by (a) connecting two redundant signals X and x directly (wired-or), and (b) connecting two redundant signals through capacitive connections.

• Resitive shorts. – MOSFET shorts. Equivalent to a SON failure. – Shorts to VDD . Equivalent to SA1 failure. – Shorts to gnd. Equivalent to SA0 failure. – Shorts between nodes (bridge) (RBR). Resistive bridge between nodes, gate outputs or feedback. In addition we have to consider faults associated with floating capacitors: • Floating capacitor stuck-open (COFF). An input capacitor with zero capacitance. Equivalent to a input stuck at (SA) fault. • Floating capacitor stuck-closed (CON). Resistive connection between an input signal and a floating gate. Redundancy has been used as a general method to overcome failures in CMOS circuits. The most common redundancy realization is a triple modular redundancy[4].

2.1

Redundancy

Transistor open and closed failures can be compensated for by using redundancy and simply wiring together redundant gates[4]. Stuck-at failures, however, are not necessarily compensated for by this strategy due to limited driving capability of the transistors. As shown in Figure 1 (a) redundancy is implemented by connecting two (or more) signals. In this case the result is determined by the driving capabilities of the gates proving signals X and x. If one of the signals is stuck-at 0 or 1 we can assume that the stuck-at failure will dominate and the redundant (and normal operative) gate will not provide a correct logic level for F . In the case of a SON failures two redundant gates may be pulling F in opposite directions with the same current levels and thus leaving a unknown or intermediate logic level at F . If three or more redundant gates are used a SON failure will not be visible at F providing that the input signals to the gates are correct. Bridge

faults may determine the signal value of F dependent on the bridge resistance, driving capabilities of the gates involved and/or faults associated with the respective gates. Bridge failures (RBR) share some similarities with cross talk noise and can reduce robustness and noise margins in a system. The node F is not likely to experience a bit error due to bridge failures or cross talk directly. However due to the a severe degradation of the time constant as a consequence of this failures a signal F may not respond fast enough compared to the operating frequency of the system, and F may therefor be interpreted incorrectly by the preceding gate. By connecting two or more gates, errors due to SOFF and IOFF faults can be avoided. In Figure 1 (b) redundancy is implemented by connecting two (or more) signals through capacitive connections. In the case of stuck-at failures associated with X or x the driving capabilities of the two redundant gates providing these signals will not dominate the node F significantly. If X is stuck at 0 or 1 then a voltage change at x will be transfered to F through the floating capacitor. The change in F will be less than if both X and x changes in the same direction. The only severe problem may arise if X and x changes in opposite directions. In addition we may have to consider a possibility of a stuck at fault at F itself. In the case of SON and SOFF failures the same arguments can be applied. There will only be a significant problem if the redundant signals switches in opposite directions. In the case of bridge (RBR) faults the combination of signals through capacitive connections will reduce the probability of an error.

3 Ternary recharge logic Any floating-gate (FG) circuit need to be initialized, either once or frequently. By recharging a SFG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges. When reseting or recharging a gate the inputs are recharged simultaneously and not set to a reference voltage, normally Vss or Vdd . While recharging, the semi-floating-gate of a logic gate is forced to Vdd /2. The clocked-Neuron-MOS logic was proposed for binary logic gates and for threshold gates [5, 6]. The recharge scheme is similar to biasing of single-ended auto-zeroing comparators which have been used in high-speed flash AD converters. The main purpose of the recharge scheme is to initialize or recharge the semifloating-gates to an equilibrium state which can be utilized to yield fast binary and multiple-valued signal processing [2]. In addition we may reduce the effect of mismatches, especially transistor mismatches, and power supply noise. The recharge scheme provides a simple, fast and accurate recharge to the equilibrium state for all gates regardless of logical depth. The logic gate output are recharged to a spe-

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

φ

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Figure 3. Ternary majority-3 gate. Figure 2. SFG inverter. YZ X

cific value, namely Vdd /2 and the SFG are recharged to the initial equilibrium state, namely Vdd /2. The precharge/recharge voltage is VDD /2 witch is neither logic 0 or 1. The recharge level can be defined as 1/2, or alternatively 0 if voltage level 0 is defined as −1 and VDD is defined as 1. This is called balanced ternary notation. The input signal to a SFG gate is not processed through its level, the change in voltage level from the recharge level determines the change in the output of the gate. Normally the inputs signals will be +1 or −1. If, however, the input is fixed to any voltage level, both during recharge and evaluate, there will be no change and the input will not influence on the logical operation of the gate.

3.1

Faults

We can analyze the SFG inverter, shown in Figure 2, in terms of response to an internal fault, assuming that the input signal is correct. The transistor faults can be located at the output Ep or En or in the switch providing the feedback from the output to the semi floating gate node (SFGN). 3.1.1 Fault in the switch (TG) A SOFF fault in the switch will not influence significantly on the operation of the circuit if the switch is a transmission gate (TG). The effect of a SOFF in one of the feedback transistors will be visible both as a minor deviation from the defined initial state (logic 0) and an increased recharge delay. A SON fault in one of the recharge transistors will effectively pull the SFGN and the output towards the initial state at a rate determined by the driving capabilities or effective resistance of the transistor with the SON fault. We can assume that the gate will respond to an input change with a voltage change in the right direction, the response will, however, be less than expected and temporary. A SON fault in the transmission gate will not result in a output change in the wrong direction. The most severe error is that the gate will not respond to an input signal and thus the output will be stucked at VDD /2 (SA). Note that any static signal, independently of the static voltage will be received and interpreted equivalently. A feedback bridge is equivalent to a TG SON fault.

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YZ X -1-1 -1+1 +1+1 +1-1 -1 +1 +1 -1 +1 +1 +1 -1 -1 -1

Boolean

Ternary

Figure 4. Boolean and ternary majority-3 gate function. A ternary 0 implies an error due to a fault.

3.1.2 Faults in the output transistors If one of the output transistors is SOFF the output will be precharged close to the supply rail of the normally operating transistor. The gate will only respond marginally to an input signal. The voltage change will be in the correct direction. In the case where one of the output transistor is SON a similar situation will occur. The precharge value will be close to the supply feeding the SON transistor and the gate will respond to an input signal with a attenuated voltage change in the correct direction. 3.1.3 Interconnect stuck-open The gate will respond to this failure similar to SOFF fault in one of the output transistors. The IOFF fault will effectively generate a static output voltage.

3.2

SFG ternary majority-3 gate

A ternary majority-3 SFG gate, with two transistors, is shown in Figure 3. The increased complexity in logic operation is not dependent on an increased number of transistors and thus the probability of transistor faults will not increase with the complexity of the gate. We have to consider possible faults associated with the capacitors. There are two faults to be considered, namely open (COFF) and closed (CON). For a single input SFG inverter a CON fault will actually be beneficial because the input signal will not be attenuated. A COFF fault may further lead to a leakage problem and a voltage change possibly in the wrong direction. For a multiple input SFG gate a CON fault may result in a logic error. If X = Y = +1 and Z = −1 the correct operation of the gate is −1, if however, the ca-

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

pacitor connected to Z is CON the output will most probably be +1. This error depends on timing details. Normally the gate providing the input signal X will see a capacitance equal to C in addition to parasitic capacitance (Cpar ) in the gate itself. If the capacitor connecting X to the SFGN is CON the load capacitance seen by the input X will be increased from C + CparX to 3C + CparX + 2Cg + 2Cdif f where 2Cg + 2Cdif f ≈ CparX and C > CparX . Hence the load capacitance has been tripled and therefore the timing response is changed. If the frequency is high the extra load on X may reduce the effect of a CON fault. If the CON resistance is high compared to a transistor resistance in the on state, the disturbance from an input through the CON will be reduced further. If the floating capacitance are metal metal capacitors the CON resistance is equivalent to a bridge resistance between the metal layers. Bridge faults can be divided into two groups, hard or soft, depending on the resistance. Only hard bridge faults may cause problems to a redundant majority-3 gate. If the frequency of the system is very high the extra load will reduce the effect of a CON fault. The response of the majority3 gate is shown in Figure 4. A ternary 0 implies an error due to a fault. 3.2.1 Response to faults Fault TG short TG nMOS open

TG pMOS open

TG open nMOS SOFF pMOS SOFF nMOS SON pMOS SON

Output ≈ VDD /2 reduced +1 increased −1 increased recharge delay reduced −1 increased +1 increased recharge delay reduced ±1 ≈ VDD ≈ 0 (gnd) ≈ VDD ≈ 0 (gnd)

Response 0 ±1 ±1

(0) 0 0 0 0

Table 1. Internal transistor faults in the majority-3 SFG gate and output response. Note that none of the faults will generate an incorrect output transition. No combination of faults will generate a false output transition.

The effect of internal SFG gate faults are given in Table 1. None of the internal faults, or combination of faults, will produce a false output transition. A false output transition can only be observed if the gate receive a false input transition. The response and output error for different input faults are shown in Table 2. Single and triple SA failures provide

Input fault Single SA Double SA Triple SA Single CON Double CON Triple CON RBR

Response ≈ VDD /2 Dep. on a single input ≈ VDD /2 transition dependent on timing details wired or of two inputs wired or wired inputs

Output error 0 (worst case) logic 0 (0/none) (0/none) (0/none) (0/none)

Table 2. Input faults and response. An output error equal to 0 implies a ternary 0. A ternary 0 implies an inactive and not a faulty transition. COFF faults are equivalent to SA faults.

a ternary 0 output which is not as critical as a false transition. For double SA faults the response is determined by the single input which is not SA. In this case the gate operates logically as a SFG single input inverter. If X and Y is SA0 or SA1, which are equivalent to [X, Y ] = [0, 0], the output will be Output = −1 · Z. If for example the correct input should have been [X, Y, Z] = [+1, +1, −1] the gate input will be [X, Y, Z] = [0, 0, −1] due to a double SA fault. The response will be Output = +1 in contrast to the correct output Output = −1. COFF errors are equivalent to SA errors. CON faults are more critical and timing dependent. The recharge condition is not influenced by CON faults because all nodes are driven to VDD /2. For a single CON fault there will be a resistive connection between one of the inputs and the semi-floatinggate. In the case were the two other inputs are not equal the SFG node is directly dominated by the input connected through the resistor. The SFG node will be driven towards the single input through the resistive connection. The delay of the input will be increased due to the resistor and additional capacitances associated with the SFG node including the other input capacitors. If the SFG is unable to response to the change in input the output will be a ternary 0, otherwise the output will process the correct transition. If however the faultless inputs are equal the only severe problem arises when the resistance between a single input and the SFG node is very small and the operating frequency is very low. In this case the single input may override the other inputs and create a false transition. If a double CON fault is evident ad the resistance of the two resistive connections are not in the same order of magnitude a false output transition may occur in the presence of two nonequal false inputs. If the resistances are approximately equal the two inputs will drive the SFG in opposite directions and the effect is no change of the SFG node due to the CON faults. If all in-

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

x

C

φ

C

Rp

C

SFGN

2

Level3

90

φ En

Figure 5. Ternary redundant majority-3 gate.

4 Redundant ternary SFG majority-3 gate The redundant majority-3 gate is shown in Figure 5. In general, the noise margin will be reduced when increasing the number of inputs. In this case we use a double set of inputs which will not reduce the gain or noise margin. On the other hand, the effect of a CON fault will be further reduced due to a significant increase in delay for the input signal connected to a CON capacitor. The response to input 011 for a simple majority-3 gate (3 inputs) and a redundant majority-3 gate (6 inputs) is shown in Figure 6. The minimum supply voltage for the simple gate is 190mV yielding a output signal more than 75% of the input transition and a gain equal to 1.2 for a input transition equal to VDD /4 = +1/2. The response for a redundant gate assuming that there is a COFF fault or a static input signal is shown in Figure 6. The minimum supply voltage is 250mV . In this case the SFG node voltage change due to a single input signal is ∆VSF G = 0.15 · VDD /2 = 37.5mV . Note that the SFG is balanced in the equilibrium state, given that IEp = IEp , when the input signal arises. If the supply voltage is 250mV the circuit operates in weak inversion and relative transconductance and gain is quite high. If the supply voltage is 1.5V the voltage change for the SFGN is 225mV . The probable effect of one input fault for wired redundancy, MAJ-3 SFG and redundant MAJ-3 SFG gates are shown i Table 3. A single fault will not influence the operation of the gate. If two input faults are present the worst case scenario is a ternary 0 output which will not affect the following gate.

1.8 1.6

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30

puts capacitances are CON and the resistances are equal all inputs will act as wired or connected and a correct output transition will occur. An input bridge fault (RBR) will effectively reduce the swing of one or two inputs if they experience opposite transitions. An input bridge will not lead to a false transition. Given a suitable operating frequency the MAJ-3 SFG gate is not likely to produce a false transition for any single fault. Only double input SA faults are critical.

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Figure 6. Ternary majority-3 gate response to input XY Z equal -1+1+1. The dashed lines correspond to input -1+1+1/2 which is modelled as a dc input for z due to an error associated with the gate producing z. The minimum supply voltage required for simple majority-3 SFG gate is 190mV assuming floating input capacitors equal to three times the parasitic capacitance seen bay the semi floatinggate node. By using redundant input signals the minimum supply voltage becomes 250mV .

Simulated (spice and the 0.35µ AMS CMOS process) response of a redundant MAJ-3 SFG gate to different input faults is shown in Figure 7. The clock frequency is 200M Hz. X (and x) and Y (and y) have transitions in opposite directions and the response of the gate is dependent on Z and z. The response to a stuck at fault on the input z is shown as Vsa and Z equal to Y. Vsch2 resembles a response to a hard bridge fault or short circuit of the input capacitor associated with the input z. The resistance i parallel to the short circuited capacitor is 100kΩ. Vscs2 resembles a response to a soft bridge fault or short circuit of the input capacitor associated with the input z. The resistance i parallel to the short circuited capacitor is 1M Ω. The correct respone of the MAJ-3 gate in this case is to invert the signal Z (and z). As can be seen in Figure 7 the redundant MAJ3 gate respond correctly to the input signals at 200M Hz. For the input SA fault the timing response is affected. Note that the hard bridge fault (CON) has less impact than a soft bridge fault (CON). Simulated (spice and 0.35µ CMOS) response of a redundant MAJ-3 SFG gate to different input faults is shown in Figure 8. X (and x) and Y (and y) have transitions in the same direction and the response of the gate is independent on Z and z. Vsch resembles a response to a hard bridge fault or short circuit of the input capacitor associated with the input z. Vscs resembles a response to a soft bridge fault or

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

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Wired err. logic logic none

MAJ-3 error 0 (logic) 0 logic logic

Red. MAJ-3 err. none none none none none

1 0

X and x

Inp. fault SA RBR IOFF COFF CON

Table 3. The probable effect of one input fault for wired redundancy, MAJ-3 SFG and redundant MAJ-3 SFG gates.

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short circuit of the input capacitor associated with the input z. Given the inputs X= x =Y= y, the response of the redundant MAJ-3 gate should be unaffected by the thrird input Z and z. Given a clock frequency of 200M Hz the circuit operates correctly. In this case the circuit is less affected by a soft CON fault than by a hard CON fault.

Vscs2

0

5 Conclusion

2 1 0 6 Time [ns]

Figure 7. Simulated (spice and the 0.35µ AMS CMOS process) response of a redundant MAJ-3 SFG gate to different input faults.

In this paper we presented fault tolerant CMOS logic using redundancy and ternary signals. Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied.

X and x Y and y

References [1] T. Shibata and T. Ohmi. “ A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations”, In IEEE Transactions on Electron Devices, vol 39, 1992.

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[3] C. Constantinescu. “Trends and challanges in VLSI circuit reliability”, IEEE Micro, Volume: 23, Issue: 4, July-Aug. 2003.

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[2] Y. Berg, S. Aunet, Ø. Næss and O. Mirmotahari. “Basic Multiple-Valued Functions Using Recharge CMOS Logic”, Proceedings, 34th Int. Symposium on Multiple-Valued Logic, 2004 .

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[4] B.W. Johnson. “Design and Analysis of Fault-Tolerant Digital Systems”, Addison-Wesley Publishing Compant 1989, ISBN 0-201-07570-9.

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Figure 8. Simulated (spice and 0.35µ CMOS) response of a redundant MAJ-3 SFG gate to different input faults.

[5] K. Kotani, T. Shibata, M. Imai and T. Ohmi. “ClockedNeuron-MOS Logic Circuits Employing Auto-ThresholdAdjustment”, In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995. [6] R. Lashevsky, K. Takaara and M. Souma “Neuron MOSFET as a Way to Design a Threshold Gates with the Threshold and Input Weights Alterable in Real Time”, IEEE TT13.11-1.4, 1998, pp. 263–266.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

7.5

PAPER V: A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

Henning Gundersen and Yngvar Berg Department of informatics, University of Oslo Proceedings of 36th International Symposium on Multiple-Valued Logic, ISMVL, Singapore May 17-20, 2006, ISBN 0-7695-2532-6

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A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices Henning Gundersen and Yngvar Berg Department of Informatics, Microelectronic Systems Group, University of Oslo Blindern, NO-0316, Oslo, Norway Email: henningg@ifi.uio.no

Abstract— This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is R Analog Design Environment, with simulated by using Cadence CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

d) Addition and subtraction are essentially the same operation: just negate one number, and afterwards do an adding operation. The multiple-input Floating-Gate (FG) transistors can be used to simplify the design of multiple-valued logic [4]. The initial charge on the floating-gates may vary significantly and therefore impose a very severe inaccuracy, unless we do apply some form of initialization. Research on floating-gate reset strategies have been presented by Kotani et.al. [5], and by Berg et.al. [6].

I. I NTRODUCTION Humans count by tens, machines count by twos, this sums up the way we do arithmetic today. However, there are countless other ways to count. This paper will present a ternary adder which uses base 3 representation. ’Ternary numbering systems is the most efficient of all integer bases’ as Brian Hayes claims in his article Third Base[1]. Ternary number systems use number representation with radix=3, compared with binary, which uses radix=2. Another way of representing a ternary number is by using a balanced ternary notation. ’Perhaps the prettiest number system of all’ as Donald Knuth said in his book, The Art of Computer Programming [2]. In the balanced ternary the digits are also powers of 3, as in ordinary ternary numbers, but they are ’balanced’ since they are symmetrical about zero. Another approach by using ternary logic in fast adder design, is presented by Rajashekhara et.al. [3] A given example of a balanced ternary number is the decimal number 23. It is written in balanced ternary notation as: 1011. This numeral is interpreted as: 1x33 + 0x32 − 1x31 − 1x30 , or 27 + 0 - 3 - 1, in decimal notation. The balanced ternary number system has also some nice properties: a) Negation is easy, change 1 with 1, and vica versa. If we use the example -23, the result will be 1011 in balanced ternary notation. b) The sign of a number is given by its most significant nonzero ’trit1 ’ c) The operation of rounding to the nearest integer is identical to truncation. 1 One trit has 3 values, the values are (-1, 0, 1), it is analogous to bit in the binary world (0 , 1).

Floating-Gate (FG) circuits need to be initialized, either once initially or frequently. The once and for all initialization is synonymous with programming. By recharging the FG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges, and we convert the non-volatile floating gates to Semi Floating-Gates (SFG)[6]. The reset or recharged scheme may be used to overcome some problems associated with the floating-gate circuit design. The recharged condition is different than the reset in clocked-Neuron-MOS logic proposed by Kotani et.al. [5]. When reseting or recharging a gate the inputs are recharged simultaneously and are not set to a reference voltage. While recharging, the gates are short-circuited using a local recharge switch (+Clk), the output and the semi floating-gate on the input is forced to Vdd /2, see figure 1. The recharged scheme is similar to biasing of single-ended auto-zeroing comparators, which have been used in highspeed flash AD converters. The main purpose of the recharged scheme is to initialize or recharge the semi-floating-gates to an equilibrium state which can be utilized to yield fast binary and multiple-valued signal processing. In addition we may reduce the effect of mismatches, especially transistor mismatches, and power supply noise. The recharged scheme provides a simple, fast and accurate recharge to the equilibrium state for all gates regardless of logical depth. We use the term Recharged Logic (RL) or Recharged Semi-Floating Gate Logic (RSFGL) for the circuits presented in this paper [7]. The SFG circuits are recharged to the initial equilibrium state, namely Vdd /2.

Proceedings of the 36th International Symposium on Multiple-Valued Logic (ISMVL’06) 0-7695-2532-6/06 $20.00 © 2006

IEEE

Cf

This paper will present a novel carry free Balanced Ternary Adder (BTA) using Recharged Semi-Floating Gate (RSFG) devices. The truth table of the presented adder is shown in table I. Section II will briefly cover some of the building blocks used in Recharged Semi-Floating Gate design. In section III we will look closer to the realization of the voltage mode Balanced Ternary Adder (BTA).

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Fig. 2. Schematic diagram of the Recharged Semi-Floating Gate MVL Inverter, which generates the Ternary NOT function. The transistor sizes are Pe (w = 460nm and l = 100nm) and Ne (w = 120nm and l = 100nm) TABLE II T HE TRUTH TABLE OF THE TERNARY NOT FUNCTION

II. F UNDAMENTAL B UILDING BLOCKS USED IN R ECHARGED S EMI -F LOATING G ATE (RSFG) D ESIGN A. The Recharged Semi-Floating Gate (RSFG) Inverter

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Fig. 1. Schematic diagram of a Recharged Semi-Floating Gate Inverter. The transistor sizes are Pe (w = 460nm and l = 100nm) and Ne (w = 120nm and l = 100nm)

The input stages needs an Auto-Zero Circuit (AZC) as shown in figure 3. An Auto-Zero circuit can be seen as a signal converter which converts an input signal to a valid recharge signal [10]. The recharge frequency is twice the frequency of the input signal. The AZC has two Pass-Gate Circuits, clocked + Clk

A Recharged Semi-Floating Gate (RSFG) inverter is shown in figure 1. The RSFG inverter act just like a ordinary inverter, except that it has a local feedback switch (+Clk) connected between the input gates and the output. By equalizing the βs we obtain an equilibrium state when the recharged signal is 1, and the output and the gate are driven towards Vdd /2. The recharge frequency is twice the frequency of the input signal. B. The Recharged Semi-Floating Gate (RSFG) Ternary Inverter The Recharge Semi-Floating Gate (RSFG) MVL-Inverter [8] in figure 2 is an important application. This is a key element in Multi-Valued Logic [6]. A MVL inverter, also called an analog inverter, is an inverter with a negative feedback mechanism, Cf [9]. The voltage gain of this circuit out is Av = ΔV ΔVin = −1. The transfer characteristic of the analog inverter is given by equation1. Vout = Vdd − Vin

(1)

A MVL inverter can be used to generate the NOT or the Negation function in ternary logic. A truth table of a Ternary NOT function is shown in table II.

Pe

IEEE

Vout

− Clk

Vin

AZC

Vout

Ne

Vin Pe − Clk

+ Clk

Fig. 3. Schematic diagram of the Auto-Zero circuit The transistor sizes are Pe (w = 130nm and l = 100nm) and Ne (w = 130nm and l = 100nm)

with the opposite clock phase. The upper Pass-Gate Circuit in figure 3 has Vdd /2 as the input, and the lower Pass-Gate has Vin as input. The output signal Vout will then have the signal level of Vdd /2, in the recharge period, which is set by the upper Pass-Gate circuit, and Vin in the precharged period. The X and Y signals shown in figure 5 are examples of Auto-Zeroed input signals.

Proceedings of the 36th International Symposium on Multiple-Valued Logic (ISMVL’06) 0-7695-2532-6/06 $20.00 © 2006

+ Clk

Ne

Vdd/2

+ Clk

CARRY DETECT C1

+ Clk

+ Clk

AZC C2 − Clk

i4

i1

C16

C20

+ Clk

+ Clk

C−HIGH

C3

C12

+ Clk

C18

C13 C4

+ Clk

+ Clk

i9

i7

SUM 1

AZC C5 − Clk

i2

C−LOW

i5

C6

SUM−CARRY

+ Clk X

AZC − Clk

C7

+ Clk

C8

C9

C11

+ Clk

+ Clk C10

i3 Y

C14

C17

C21

+ Clk

+ Clk C19

C15 i8

i6

i 10

SUM 0

AZC − Clk

PRE−ADDER

Fig. 4. Schematic diagram of the Balanced Ternary Adder (C1, C2, C3, C4, C5, C6, C7, C8, C11, C12, C13, C16, C17, C20, C21 = 1f F, C9, C15 = 1.5f F, C10 = 7f F, C14 = 3f F, C18 = 2f F, C19 = 4f F )

III. T HE BALANCED T ERNARY A DDER A Balanced Ternary Adder (BTA) takes two Ternary inputs (X and Y) and generate the SUM output (S0 and S1), and it offers carry free addition. The truth table of the BTA is shown in table I. The complete schematic diagram of the Balanced Ternary Adder circuit is shown in figure 4. A. The Pre-Adder stage The Pre-Adder stage is a simple adder. The Pre-Adder adds the two input signals X and Y electrically, using a two-input MVL inverter. The Pre-Adder stage consists of capacitors C7, C8, C9, C10, C11 and Inverter i3 and i6. Inverter i3 is a two inputs MVL inverter. Input signal X is connected to C7 and the Y signal is connected to C8. The two input signals will be added together and inverted. The output signal from i3 has to be amplified and inverted. This is done by the ternary inverter i6, the ternary output signal from the Pre-Adder stage is shown in figure 5. The output signal of the Pre-Adder is not correct. When both X and Y is high (1) or when both X and Y are low (1), the signal has to be inverted to generate a correct SUM 0 signal which correspond to the truth table I. B. The Carry detect stage The Carry detect stage will either detect when both X and Y is high or both X and Y is low. Furthermore this will generate a Binary high- or low-Carry signal. The Carry detect stage consists of C1, C2, C3, C4, C5, C6 and four inverters i1, i2, i4 and i5. The main idea is to use the threshold elements i1 and i2, a three input FG inverter, to detect the carry signal. To detect carry high, the three input FG inverter i1 is used. The Auto-Zeroed X is connected to C3, Auto-Zeroed Y is

connected to C2. C1 is connected to a Auto-Zeroed gnd signal. If both X and Y is high, the inverter i1 will set the output Low, else the output will be determined by the Auto-Zeroed gnd signal, and the output of i1 will be set high. The output will only be set low if both X and Y is High. The logic levels of X and Y, if they are high is = 900mV . The gnd signal is 0 V. Since all of the inputs have the same weight, (C1=C2=C3) hence it will be set low only when both X and Y are 1. Carry low detection is done in the same manner, except if both X and Y are low, the output of inverter i2 is set high, else the output is set low. As figure 4 shows C4 is connected to the Auto-Zeroed Vdd and all of the input capacitors has the same weight (C4=C5=C6). The logic levels of X and Y low (1) are 100mV and Vdd = 1.0V , hence both X and Y have to be low to set inverter i2 high. Inverter i4 and i5 equalize and inverts the signal, the output of the Carry detect stage, C-LOW and C-HIGH is shown in figure 5. Inverter i7 is a binary to ternary converter. It makes a summation of C-LOW and CHIGH. The output signal SUM-CARRY in figure 5 is a ternary representation of the Carry signals. C. The output stages 1) SUM 1: To generate the SUM 1 signal we only need a ternary inversion of the SUM-CARRY signal, this is done by the ternary inverter i9. 2) SUM 0: To generate SUM 0 we need to invert the PREADDER output signal either when both X and Y are low or high at the same time. This is achieved by the two input MVL inverter i8. C14 has to be twice the value of C15 to achieve this. The output of i8 is the inverted SUM 0 signal, this is why the output has to be inverted in inverter i10, which generate

Proceedings of the 36th International Symposium on Multiple-Valued Logic (ISMVL’06) 0-7695-2532-6/06 $20.00 © 2006

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X1

Y1

X0

Y0

1 X

BTA

BTA

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

S1

2

S1

−8

x 10 Y

1

BTA

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

S2

SUM 1

x 10

S2

1

BTA

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

SUM 0

x 10 1

S2

S1

S0

0.5

0

Fig. 6. 0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

An example of a 2 trits Balanced Ternary Adder

2

PRE−ADDER

−8

x 10

Cf

1

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

+Clk

2 −8

C−LOW

x 10 1

Ci

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Y

2

S1

−8

C−HIGH

x 10

BTA

1

X

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

SUM−CARRY

S0

Fig. 7.

x 10

A Balanced Ternary Subtractor Circuit

1

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

R EFERENCES

2 −8

x 10

Fig. 5. Simulation results for the Balanced Ternary Adder shown in figure 4.

the correct SUM 0 signal shown in figure 5. Furthermore this correspond with the truth table I. Figure 6 shows an example of a two trits adder, using the Balanced Ternary Adder blocks. D. The subtraction circuit To make a balanced Ternary Subtraction Circuit either X or Y need to be inverted as shown in figure 7. Y is inverted using the RSFG Ternary Inverter shown in figure 2. This application generates the balanced ternary subtraction, X − Y . IV. C ONCLUSIONS In this paper a novel Balanced Ternary Adder (BTA) has been presented. A subtraction circuit using the BTA, can easily be made by a ternary inversion of one of the input signals. It offers carry free addition, and this adder can be used as a building block in designing a fast multiplier circuit. It operates at a clock frequency at 1 GHz. The supply voltage is only 1.0 Volt.

[1] B. Hayes, “Third Base,” American Scientist, Volume 89, Number 6, pp. 490–494, Nov-Dec 2001. [2] D. Knuth, The Art of Computer Programming, Second edition. AddisonWesley Publishing Company, 1981. [3] T. N. Rajashekhara and I. E. Chen, “A Fast Adder Design Using SignedDigit Numbers and Ternary Logic,” Southern Tier Technical Conference 1990, Proceedings of the 1990 IEEE, pp. 187–194, 1990. [4] T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring GateLevel Weighted Sum and Threshold Operations,” IEEE Transactions on Electron devices, vol. 39(6), pp. 1444–1455, 1992. [5] K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked NeuronMOS Logic Circuits Employing Auto Threhold Adjustment,” IEEE International Solid-State Circuits Conference(ISSCC), pp. 320–321,388, 1995. [6] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin, “Novel Recharge Semi-Floating-Gate CMOS Logic For Multiple-Valued Systems,” Proceedings of the 2003 IEEE International Symposium on Circuits And Systems in Bangkok, 2003. [7] Y. Berg, S. Aunet, Ø. Næss, O. Mirmotahari, and M. Høvin, “Binary to Multiple-Valued Recharge Converter for Multiple-Valued CMOS logic,” ECCTD’03-Euopean Conference on Circuit Theory and Design,Cracow, Poland, pp. 349–352, 2003. [8] H. Gundersen and Y. Berg, “MAX and MIN Functions Using MultipleValued Recharged Semi-Floating Gate Circuits,” Proceedings of the 2004 IEEE International Symposium on Circuits And Systems in Vancouver, 2004. [9] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen, “Ultra-Low-Voltage Floating Gate Transconductance Amplifiers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001. [10] Y. Berg and H. Gundersen, “A Novel Ternary Switching Element Using CMOS Recharged Semi-Floating Gate Devices,” Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic in Calgary, pp. 54 –58, May. 2005.

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7.6

PAPER VI: Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Henning Gundersen and Yngvar Berg Department of informatics, University of Oslo Proceedings of 37th International Symposium on Multiple-Valued Logic, ISMVL, Oslo Norway, May 14-15, 2007, ISBN 0-7695-2831-1

85

86

Fast Addition Using Balanced Ternary Counters Designed With CMOS Semi-Floating Gate Devices Henning Gundersen and Yngvar Berg Department of Informatics, Microelectronic Systems Group, University of Oslo Blindern, NO-0316, Oslo, Norway Email: [email protected]

Abstract This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.

1

Introduction

Nowadays nearly all addition done in an arithmetic unit (ALU) in a modern computer, uses binary operands. By using ternary notation we can take advantage of the possibilities lying in the ternary numbering system. If we are using balanced ternary numbers, also called Signed-Digit Numbers [12], we can add both negative and positive numbers without any use of a sign bit. The so-called ’Brousentsov’s Ternary Principle’ of computer design was initially realized in the Setun computer [14] and this computer was based on the ’ternary-symmetrical number system’, which is another name for the balanced ternary notation. As early as 1840 Thomas Fowler, a self-taught English mathematician, invented a ternary mechanical calculating machine which used balanced ternary notation. All details on the calculating machine was lost, until recently. A research project, started in 1997, have managed to get the information which was needed to create a complete historical replica [4]. Fowler used the terms -, 0 and + for a negative, a zero and a positive number. In this paper the terms 1, 0 and 1 will be used. There has been several attempts to implement arithmetic applications by using the ternary numbering system, but they lack commercial success [8] [3].

1.1

The Balanced Ternary Numbering System

Brian Hayes claims in his article Third Base [7] ’Ternary numbering systems are the most efficient of all integer bases’. In the balanced ternary notation the digits are also powers of 3, as they are in ordinary ternary numbering systems. However they are ’balanced’ since they are symmetrical about zero. Balanced ternary notation is ’Perhaps the prettiest number system of all’ as Donald Knuth says in his book, The Art of Computer Programming [10]. A balanced ternary number 1011 (2310 ), is interpreted as: 1x33 + 0x32 − 1x31 − 1x30 , or 27 + 0 - 3 - 1, in decimal notation. The balanced ternary number system has some advantageous properties: a) ’Ternary inversion’ [14] is easy, change 1 with 1, and vice versa. If we use the example -23, the result will be 1011 in balanced ternary notation. b) The sign of a number is given by its most significant nonzero ’trit1 ’ c) The operation of rounding to the nearest integer is identical to truncation. d) Addition and subtraction are essentially the same operation: just apply the rules of ’ternary inversion’ to one of the operands, and afterwards do an adding operation. The truth table of the rule of ’ternary inversion’ is shown in table 1. Table 1. The rule of ’ternary inversion’ x

1

0

1

x

1

0

1

1 One trit has 3 values (1, 0, 1), it is analogous to bit in the binary world (0 , 1).

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

1.2

Balanced Ternary Counters

A balanced ternary counter (BTC) is comparable with a ternary full adder, where the carry signal can have all logic values (1,0 and 1)2 . A balanced ternary adder sums up the inputs Xi , where i is number of trits of the same weight, and gives an output in balanced ternary notation. Truth tables of balanced ternary counters are shown in table 2 and table 4. A (4,2) counter corresponds to a 4-input ternary full adder, where the carry signal can take all three logic values. This paper present balanced ternary adder structures, using (3,2) and (4,2) ternary counters, it has also been called 4 to 2 reducers [15]. A (4,2) ternary counter has 4 balanced ternary inputs (X1 ..X4 ) and two balanced ternary outputs (S0 , S1 ). An interesting ternary full adder implemented in Depletion/Enhancement CMOS technology was presented in 1985 [9], but it didn’t achieved any commercial success. Earlier work on this problem was a balanced ternary adder which were presented in Singapore at the ISMVL conference in 2006 [6]. This was a balanced (2,2) ternary adder, it had two balanced ternary inputs (X and Y) and two balanced ternary outputs (S0 , S1 ).

to semi floating gates (SFG)[1]. The reset or recharge scheme may be used to overcome some problems associated with the floating-gate circuit design. The capacitors in the CMOS recharged SFG design, presented in this paper, are metal plate capacitors based on vertical coupling capacitance between stacked metal plates.

1.3.1

Cf

1.3

Xi

-4

-3

-2

-1

0

1

2

3

4

S0

1

0

1

1

0

1

1

0

1

S1

1

1

1

0

0

0

1

1

1

i=1

Recharge Semi-Floating Gate Devices

The multiple-input floating-gate (FG) transistors can be used to simplify the design of multiple-valued logic [13]. The initial charge on the floating-gates may vary significantly and impose a very severe inaccuracy, unless we do apply some form of initialization. Research on floating-gate reset strategies have been presented by Kotani et.al. [11], and by Berg et.al. [1]. Floating-gate (FG) circuits need to be initialized, either once initially or frequently. The once and for all initialization is synonymous with programming. By recharging the FG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floatinggate charges, and it converts the non-volatile floating gates 2 The logic levels are:

1V

1 = 100mv, 0 = 500mv and 1 = 900mv , Vdd =

+ Clk

Pe Cf Ci

Vin

Ci + Clk

Vout

Vin

Vout

Ne

Figure 1. Schematic diagram of the Recharged SemiFloating Gate MVL Inverter, which generates the Ternary NOT function. (Pe : w/l = 460nm/100nm and Ne : w/l = 120nm/100nm)

Table 2. The truth table of a balanced ternary (4,2) counter
4

The Recharged Semi-Floating Gate (RSFG) Ternary Inverter

The Recharge Semi-Floating Gate (RSFG) MVLInverter in figure 1 is an essential building block [5]. It is a key element in Multi-Valued Logic [1]. The Clk pulse (+Clk) is given by the recharge frequency, which is twice the frequency of the input signal. The voltage gain of Ci out this circuit is Av = ∆V ∆Vin = Cf = −1, if the input capacitor(Ci ) is equal to the feedback capacitor(Cf ). The transfer characteristic of an ideal analog inverter is given by equation1 [2]. Vout = Vdd − Vin

(1)

A MVL inverter can be used to generate the ’ternary inversion’, x = x, as shown in table 1.

2

Implementation of the Balanced Ternary (4,2) Counter

A schematic diagram of the presented balanced ternary (4,2) counter is shown in figure 2. The (4,2) counter is implemented using CMOS recharged semi-floating gate (SFG) devices.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

X1

C1

1 0 1 0

C2

CARRY DETECT

+ Clk

+ Clk

00 11

X2

C3

1 0 1 0

X3

i1

i2 C23

C25

+ Clk

+ Clk

C4

11 00

X4

C5 C18

+ Clk

C−HIGH

C24 C19

i5

i6

SUM 1

C6 − Clk

C−LOW

11 00 00 11

C7

+ Clk

+ Clk

C8

1 0 11 00 00 11 1 0 0 1

SUM 1 i3

i4

C9

C10

C13

C20

C22

C14

+ Clk

+ Clk C21

C15 i7

i8

SUM 0

C16 ADDER C17

Figure 2. A Schematic diagram of the balanced ternary (4,2) counter (C1 ..C4 , C7 ..C10 , C14 ..C19 = 500.5aF, C5 , C6 = 374.4aF, C13 = 1.503f F, C20 , C22 , C25 = 374.4aF, C21 = 6.69f F, C23 = 423.2aF, C24 = 1.234f F )

2.1

The Balanced Ternary (4,2) Counter

2.1.1

The Carry Detect Stage

The carry detect stage
4 generates a ternary carry signal, when the input signals i=1 Xi is less than −2 and greater than 2. This is achieved by using a 5 input threshold circuit (i1 and i3). By focusing at figure 2 we can see that the 4 inputs X1 ..X4 , are compared to the clock pulse ’+Clk’ and ’-Clk’, connected respectively to input capacitors C5 and C6 . The upper circuits i1 and i2 generates the binary ’CHIGH’ signal, which is set to the logic level ’1’ when the sum of the inputs Xi , are greater than 2. The input capacitors C1 ..C4 are equal. Capacitor
4 C5 determines the threshold of i1, by comparing the i=1 Xi with the ’+Clk’ signal (The ’+Clk’ signal is in phase with reference clock). ’C-LOW’ is set in a similar way, except it will be set to logic level ’1’, when the sum of the inputs Xi is less than -2. The threshold of i3 is determined by the capacitor C6 , which is connected to the ’-Clk’ signal (The ’-Clk’ is in opposite phase with the reference clock). The inverter i5 is a binary to ternary converter, it converts the two binary carry signals (C-LOW, C-HIGH) to a balanced ternary carry signal (SU M 1).

2.1.2

The Output Stages, SUM 0 and SUM 1

To generate the correct ’SUM 1’ signal, we need to do a ternary inversion of the output signal of inverter i5 (SU M 1), this is done by using the ternary inverter i6. The adder circuits i7 and i8, generates the ’SUM 0’ signal. This is done by weighting the inverted ’SU M 0’ three times the input signals Xi , by choosing C13 three times larger than each of the input capacitors C14 ..C17 (C13 = 1.50f f F, C14 ..C17 = 500.5aF ). Figure 3 shows a typical plot of the SUM 0 and SUM 1 signal at a 1 GHz clock frequency. This verifies the logical operation of the BT (4,2) counter circuit shown in table 2. To make a (3,2) counter, we just need to apply a small modification, we can easily remove three of the input capacitors from the (4,2) counter, as shown in figure 4. Or we can connect one of the inputs of the (4,2) counter to logic level ’0’ =Vdd /2.

3

Ternary Applications Ternary Counters

Using

Balanced

A balanced ternary (13,3) counter can be made by using 5 ternary (4,2) counters, as shown in figure 5. The

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

Table 4. The truth table of the balanced ternary (13,3) counter
13 i=1 Xi

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

S0

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

S1

1

1

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

S3

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

C10

C12

+ Clk C1

X1

1

+ Clk

CARRY DETECT

0

+ Clk

C−HIGH

0.5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

C−LOW

1.8

C11

C2

i4

i3

SUM 1

−8

x 10

X1 00 11

X2

1

11 00 00 11

0.5 0

X2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

X3

X3

1

C7

0 1 1 0 0 1

C9

C3 + Clk

C4 C8

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 C5

−8

x 10 1 X4

_____ SUM 1

+ Clk

0.5 0

− Clk

00 11 11 00 00 11

i1

i2

SUM 0

C6

0.5 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

SUM 0

x 10

Figure 4. A block diagram of a balanced ternary (3,2) counter

1 0.5 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

SUM 1

x 10 1 0.5 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8 −8

x 10

Figure 3. Typical outputs from the (4,2) balanced ternary counter shown in figure 2

truth table of the (13,3) counter can be seen in table 4. A block diagram of the complete 4 trits balanced ternary parallel adder using (4,2) BTC’s is shown in figure 6. The input vectors are: Xi = [1110], Yi = [1111], Xi = [0010], which correspond with 15-32+3=-14 in decimal notation. The SU M =[1111]3 =−1410 . Figure 7 verifies the operation of the circuit. It is also possible to build a Wallace tree structure by using balanced ternary counters. A Wallace tree adder sums up all trits of the same weights in a merged tree, and do not add the partial products in pairs as a balanced ternary parallel adder does. Figure 8 shows a balanced ternary Wallace tree adder.

3.1

Advantages Using Balanced Ternary Counters

Mostly all of the binary adder structures are directly convert able to balanced ternary adder structures. This means you can be able to replace the binary full adders with ternary

balanced counters, and still have the same functionality. However there is an advantage using balanced ternary notation, you do not have to worry about the sign bit, and you need less trits to make the same resolution. Figure 6 shows a 4-trits parallel balanced ternary adder (BTA), which is comparable with a 6-bit ripple carry adder if we consider the resolution. To build a 6-bit ripple carry adder we need 6 full-adders (FA), compared to 4 balanced ternary counters (BTC). A typical binary FA uses 28 transistors, the presented BTC uses 32 transistors. This gives us, a 4-trits balanced ternary adder needs 128 transistors, compared to a binary 6-bits adder which needs 168 transistors. See table 3. A 11-bit FA uses 308 transistors this is comparable with a 7-trits BTA which uses 224 transistors. Figure 9 shows this graphically, even for low resolutions it is better to use a parallel BTA compared to a binary ripple carry adder. It is also possible to make carry-save adder structures using balanced ternary counters. This makes it easy to implement balanced ternary counters in fast addition structures, based on binary logical adder theory. A floating gate structure will generally generate a larger chip area compared to a conventional design because of the capacitors. By using very small metal-capacitors and using stacking, we are able to minimize the chip area. The used 90nm CMOS process from STMicroelectronics, has 7 metal layers.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

X13 X12 X11 X10

X9 X8 X7 X6

(4,2)

(4,2)

(4,2)

BTC

BTC

BTC

Table 3. Comparison between a binary ripple carry adder and a parallel balanced ternary adder

4

Bits

Resolution

Transistors

Trits

Resolution

Transistors

1

2

28

1

3

32

2

4

56

2

9

64

3

8

84

3

27

96

4

16

112

4

81

128

5

32

140

5

243

160

6

64

168

6

729

192

7

128

196

7

2187

224

8

256

224

8

6561

256

9

512

252

9

19683

288

10

1024

280

10

59049

320

11

2048

308

11

177147

352

12

4096

336

12

531441

384

13

8192

364

13

1594323

416

14

16384

392

14

4782969

448

15

32768

420

15

14348907

480

16

65536

448

16

43046721

512

(4,2) BTC

(4,2) BTC

S2

References [1] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin. Novel Recharge Semi-Floating-Gate CMOS Logic For MultipleValued Systems. Proceedings of the 2003 IEEE International Symposium on Circuits And Systems in Bangkok, 2003.

S1

S0

Figure 5. A balanced ternary (13,3) counter Z3 Y3 X3

Z2 Y2 X2

(4,2) BTC

Conclusions

In this paper, a balanced ternary adder structures using balanced ternary counters has been presented. It has the benefitcal properties as following: 1. There is no reason to worry about the sign bit, since the structures use balanced ternary notation. 2. The resolution compared to numbers of transistor gives a higher resolution than with a typical binary solution, this is shown graphically in figure 9. It is possible to build fast addition structures, using the theory from the binary world. The simulation results shows that the circuits may be able to operate at clock frequency of 1 GHz. The circuits can be made using a conventional CMOS process. We are using a 90nm general purpose bulk CMOS process from STMicroelectronics with 7 metal layers.

X5 X4 X3 X2 X1

Z1 Y1 X1

(4,2) BTC

S4

S3

S4

S3

S3

Z0 Y0 X0

(4,2) BTC S2

S2

S2

C0

(4,2) BTC S1

S1

S1

S0

S0

Figure 6. A Block schematic diagram of a 4 trits parallel balanced ternary adder

[2] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen. UltraLow-Voltage Floating Gate Transconductance Amplifiers. IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001. [3] K. Diawuo and H. T. Mouftah. A Three-Valued CMOS Arithmetic Logic Unit Chip. Proceedings of the 17th IEEE International Symposium on Multiple-Valued Logic, pages 215–220, 1987. [4] M. Glusker, D. M. Hogan, and P. Vass. The Ternary Calcualating Machine of Thomas Fowler. IEEE Annals of the History of Computing, pages 4–22, 2005. [5] H. Gundersen and Y. Berg. MAX and MIN Functions Using Multiple-Valued Recharged Semi-Floating Gate Circuits. Proceedings of the 2004 IEEE International Symposium on Circuits And Systems in Vancouver, 2004. [6] H. Gundersen and Y. Berg. A Novel Balanced Ternary Adder Using CMOS Recharged Semi-Floating Gate Devices. Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic in Singapore, page 18, 2006. [7] B. Hayes. Third Base. American Scientist, Volume 89, Number 6, pages 490–494, Nov-Dec 2001. [8] A. Herrfeld and S. Hentsche. Ternary Multiplications Using 4-Input Adder Cells and Carry Look-Ahead. Proceedings of

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

X9

X8

X7

X6

X5

X4

X3

X2

X1

S0

1 0.5 0

0

1

2

3

4

5

6 −9

x 10

S1

1

(3,2)

(3,2)

(3,2)

BTC

BTC

BTC

0.5 0

0

1

2

3

4

5

6 −9

x 10

S2

1 0.5 0

0

1

2

3

4

5

(3,2) BTC

6 −9

x 10

(3,2) BTC

S3

1 0.5 0

0

1

2

3

4

5

6 −9

x 10

S4

1

(3,2) BTC

0.5 0

0

1

2

3

4

5

6 −9

x 10

Figure 7. Typical output signals (S0..S4) of the 4 trits parallel adder shown in figure 6. SU M = [01111]. The clock frequency is 1 GHz

[10] [11]

[12]

[13]

[14]

[15]

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07) 0-7695-2831-7/07 $20.00 © 2007

Figure 8. A balanced ternary Wallace tree adder, using (3,2) ternary counters

10

10

Ripple carry adder Parallel balanced ternary adder 8

10

6

Resolution

[9]

the 29th IEEE International Symposium on Multiple-Valued Logic, 1999. A. Heung and H. T. Mouftah. Depletion/Enhancement CMOS For a Low Power Family of Three-Valued Logic Circuits. IEEE Journal of Solid-State Circuits, VOL. sc-20, NO. 2, pages 609–616, April 1985. D. Knuth. The Art of Computer Programming, Second edition. Addison-Wesley Publishing Company, 1981. K. Kotani, T. Shibata, M. Imai, and T. Ohmi. Clocked Neuron-MOS Logic Circuits Employing Auto Threhold Adjustment. IEEE International Solid-State Circuits Conference(ISSCC), pages 320–321,388, 1995. T. N. Rajashekhara and I. E. Chen. A Fast Adder Design Using Signed-Digit Numbers and Ternary Logic. Proceedings of the 1990 IEEE International Symposium on MultipleValued Logic, pages 187–194, 1990. T. Shibata and T. Ohmi. A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Transactions on Electron devices, 39(6):1444–1455, 1992. S. Stakhov. Brousentsov’s Ternary Principle, Bergman’ Number System and Ternary Mirror-symmetrical Arithmetic. The Computer Journal, Vol. 45, No.2, pages 221–236, 2002. Z. G. Vranesic and V. C. Hamacher. Threshold Logic in Fast Ternary Multipliers. Proceedings of the 1975 IEEE International Symposium on Multiple-Valued Logic, pages 373–387, 1975.

(3,2) BTC

10

4

10

2

10

0

10

0

100

200 300 Number of transistors

400

500

Figure 9. Resolution compared to number of transistors of the presented parallel balanced ternary adder and a typical binary ripple carry adder

7.7 PAPER VII: A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices

Henning Gundersen and Yngvar Berg Department of informatics, University of Oslo Proceedings of 24th IEEE Norchip Coference, NORCHIP, Link¨ oping Sweden, Nov. 20-21, 2006, ISBN 0-4244-0772-9, Page 205-208

93

94

A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices Henning Gundersen and Yngvar Berg Department of Informatics, Microelectronic Systems Group, University of Oslo Blindern, NO-0316, Oslo, Norway Email: [email protected]

Abstract— This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with Recharged Semi-Floating Gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only R Analog 1.0 Volt. The circuit is simulated by using Cadence
Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers.

a) ’Ternary inversion’ [1] is easy, change 1 with 1, and vica versa. If we use the example -23, the result will be 1011 in balanced ternary notation. b) The sign of a number is given by its most significant nonzero ’trit1 ’ c) The operation of rounding to the nearest integer is identical to truncation. d) Addition and subtraction are essentially the same operation: just apply the rules of ’ternary inversion’ to one of the numbers, and afterwards doing an adding operation.

I. I NTRODUCTION

In 1840 Thomas Fowler, a self-taught English mathematician invented a ternary mechanical calculating machine which used balanced ternary notation. All details on the calulating machine was lost, until recently. A research project which began in 1997 have managed to get all the information which is needed to create a historical replica [6]. Fowler used the terms -, 0 and + for a negative, a zero and a positive number. We will use the terms 1, 0 and 1. Arithmetic in balanced ternary notation is almost the same as any other alternative base, except it can handle negative and positive numbers. This means that it can be both negative and positive carry to adjacent digits.

Nowadays almost all multiplication done with computers are binary multiplications. Multiplying two positive numbers in a binary numbering system is trivial, but if we want to deal with negative numbers, it is not that trivial. When doing multiplication with negative numbers you usually need a sign bit and you have to use the 2’ complement. That is why I suggest using balanced ternary numbering system instead, to make a solution to the sign problem. The so-called ’Brousentsov’s Ternary Principle’ of computer design was first realized in the Setun computer [1] and this computer used a ’ternary-symmetrical number system’, which is another name for the balanced ternary notation. There has also been some other attempts to implement arithmetic applications which use the ternary numbering system, but they lack commercial success [2] [3].

B. Balanced Ternary Arithmetic

+ =

1

A. The Balanced Ternary Number Systems ’Ternary numbering systems is the most efficient of all integer bases’ as Brian Hayes claims in his article Third Base [4]. Balanced ternary notation is a number system which use base 3 representation. Balanced ternary notation is ’Perhaps the prettiest number system of all’ as Donald Knuth said in his book, The Art of Computer Programming [5]. In the balanced ternary the digits are also powers of 3, as in ordinary ternary numbers, but they are ’balanced’ since they are symmetrical about zero. A given example of a balanced ternary number is the decimal number 23. It is written in balanced ternary notation as: 1011. This numeral is interpreted as: 1x33 + 0x32 − 1x31 − 1x30 , or 27 + 0 - 3 - 1, in decimal notation. The balanced ternary number system has also some advantage able properties:

1

decimal 1

1

decimal 1

1

decimal 2

Examples of positive carry in balanced teranary addition.

1

1

+

1

1

decimal 2

=

1

1

decimal 4

decimal 2

Examples of negative carry in balanced teranary addition.

1 One trit has 3 values, the values are ( 1, 0, 1), it is analogous to bit in the binary world (0 , 1).

Multiplication in balanced ternary notation is done in the similar manner as with decimal multiplication. The truth table of a balanced ternary multipication is shown in table I. Multiplication is done one digit a time. The choice of each

D. The Recharged Semi-Floating Gate (RSFG) Ternary Inverter Cf

TABLE I

+ Clk

Pe

T HE TRUTH TABLE OF A BALANCED T ERNARY M ULTIPLICATION C IRCUIT

Cf Ci

Vin

-1

0

1

-1

1

0

-1

0

0

0

0

1

-1

0

1

digit is simple, if the digit is 1 then invert, if it is 0 then set it to zero, if it is 1 then multiply by one. For example the multipication og 2 x 8 = 16 (decimal) is 1 1 x 1 0 1 = 1 1 1 1 in balanced ternary notation. The calculation is done as shown in the table II. In the first row the multiplicand is inverted by using ’ternary inversion’. In the second row, shift one time left, then multiply with ’0’. In the third row, shift left, then multiply with ’1’. Then the three numbers are added together using a balanced ternary adder. TABLE II A N EXAMPLE OF AN BALANCED TERNARY MULTIPLICATION . 1 0 1 1

1

0

1 1

1

Invert multiplicand 0 times multiplicand

1

Ci + Clk

Vout

Vin

Vout

Ne

Fig. 1. Schematic diagram of the Recharged Semi-Floating Gate MVL Inverter, which generates the Ternary NOT function. The transistor sizes are Pe (w = 460nm and l = 100nm) and Ne (w = 120nm and l = 100nm)

The Recharge Semi-Floating Gate (RSFG) MVL-Inverter in figure 1 is an important application [10]. This is a key element in Multi-Valued Logic [9]. A MVL inverter, also called an analog inverter, is an inverter with a negative feedback mechanism, Cf . The voltage gain of this circuit is out Av = ∆V ∆Vin = −1. The transfer characteristic of the analog inverter is given by equation1 [11]. Vout = Vdd − Vin

(1)

A MVL inverter can be used to generate the ’ternary inversion’. The truth table of the rule of ’ternary inversion’ is shown in table III.

1 times multiplicand

TABLE III

decimal 16

T HE TRUTH TABLE OF THE RULE OF ’ TERNARY INVERSION ’ Vin

Vout

1

1

C. Recharge Semi-Floating Gate Devices

0

0

The multiple-input floating-gate (FG) transistors can be used to simplify the design of multiple-valued logic [7]. The initial charge on the floating-gates may vary significantly and therefore impose a very severe inaccuracy, unless we do apply some form of initialization. Research on floating-gate reset strategies have been presented by Kotani et.al. [8], and by Berg et.al. [9]. Floating-gate (FG) circuits need to be initialized, either once initially or frequently. The once and for all initialization is synonymous with programming. By recharging the FG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges, and we convert the non-volatile floating gates to Semi Floating Gates (SFG)[9]. The reset or recharged scheme may be used to overcome some problems associated with the floating-gate circuit design. All of the capacitors in the CMOS RSFG design presented in this paper are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

1

1

II. I MPLEMENTATION OF THE BALANCED TERNARY MULTIPLICATION CIRCUIT USING R ECHARGED S EMI -F LOATING G ATE D EVICES A block scheme of the proposed BT-multiplication circuit is shown in figure 2. The input data is set into a shift register, and here the data is shifted and leading zeros are inserted in the input vectors X, Y and Z. From the shift register the 4-trits data are sent to each of the vectors X,Y and Z. X Y and Z are the input signals to the 4-trits BT-Adder. The outputs from the BT-Multiplication (BTM) circuit are S0, S1, S2, S3 and S4. A. A Balanced 3,2 Ternary Counter A balanced 3,2 ternary counter, can also be seen as a 3input ternary full adder, where the carry signal can take all three logic values (1, 0, 1). The balanced 3,2 ternary counter

C10

DATA

C12

SHIFT REGISTER C1

+ Clk

+ Clk

C−HIGH

Z

CARRY DETECT

_ 1

1

C11

C2 C−LOW

0

i4

i3

0

S1

X _____ SUM 1

Y

0

0

0

0

Y C7 Z

X

0

_ 1

0

C9

C3 + Clk

1

+ Clk

C4 C8 i1

C5

Z3

Z2

Z1

Z0

Y3

Y2

Y1

Y0

X3

X2

X1

i2

S0

X0 C6

4 TRITS BALANCED TERNARY ADDER

Fig. 3.

Fig. 2.

S3

S2

S1

S0

1

The Block Scheme of the multiplication circuit

X

S4

A Block Schematic diagram of the Balanced 3,2 Ternary Counter

0.5 0

-3

-2

-1

0

1

2

3

S0

0

1

1

0

1

1

0

S1

1

1

0

0

0

1

1

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

0.5 0

(X + Y + Z)

0.2

x 10

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

x 10 1 Z




0

1 Y

TABLE IV T HE TRUTH TABLE OF A BALANCED 3,2 T ERNARY COUNTER

0.5 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

SUM 0

x 10 1 0.5 0

B. The Balanced Ternary Multiplication Circuit A balanced ternary counter is a key element in a multiplication application. To make a 4-trits BT-Adder (figure 6) we need to use 8 balanced 3,2 ternary counters (BTC) which is shown in figure 3. The output stage (4-trits BTA) of the 4trits balanced ternary multiplication (BTM) circuit shown in figure 2, consists of 8 BTC’s. The SUM output signals is S0, S1, S2, S3 and S4. The input vectors X, Y and Z to the 4trits BTA (the output stage) will either be inverted, be zero or be unchanged. If we take the example 2 x 8 (decimal) 11

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

x 10 SUM 1

(BTC) is shown in figure 3, the truth table of the (3,2) BTC is shown in table IV. The Balanced 3,2 Ternary Counter takes three ternary inputs X, Y and Z, and generates two outputs, S0 and S1. This counter counts from -3 to +3. The full truth table is shown in table V. The simulation results of the (3,2) BTC is shown in figure 4, when the logic input signal X is set to 0. The Carry detect stage will detect when two or three of the inputs are high or low. This will then generate the binary high(C-HIGH) or binary low- (C-LOW) carry signal. The C-HIGH and C-LOW signal are combined to a ternary signal SU M 1. By adding the SU M 1 with the input signals X, Y and Z, by using a 4-input ternary inverter (i1), we get the correct SUM 0 signal. A similar balanced ternary adder were presented in Singapore at the ISMVL2006 conference [12]. It had a two balanced ternary inputs (X and Y) and two outputs, S0 and S1, but the main idea of operation is almost the same.

1 0.5 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2 −8

x 10

Fig. 4. Simulation results for the Balanced 3,2 Ternary Counter shown in figure 3.

x 101 (balanced ternary) shown in table II. The first product is the inverted, of the multiplicand which generates the 4-trits X vector X=[1 1 0 0]. The second product should be set to 0, which gives the Y vector Y=[0 0 0 0]. The third product is first shifted 2 times left and then 1 times multiplicand this gives the Z vector Z=[0 0 1 1]. Figure 5 shows the input to the output stage. X is inverted using a ternary inversion, Y is set to ’0’ and Z propagates to the input of the 4-trits BTA. To make this possible, a multiplexer-switch must be set on the input to the BTA circuit. Figure 6 shows the propagation of the trits in the output stage. Since the BTC are 3,2 counter some of the inputs of the BTCs has to be set to ’zero’ as shown in the figure 6. The signal S0 has less delay. The signal S4 has the longest path and this will determined the maximum operation frequency of this circuit. Figure 7 shows the simulated output plots of the BTMultiplication circuit. The figure shows the output vector

TABLE V T HE FULL TRUTH TABLE OF THE BALANCED 3,2 T ERNARY C OUNTER

X

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

Y

1

1

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

Z

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

1

0

1

SUM

10

11

01

11

01

00

01

00

01

11

01

00

01

00

01

00

01

11

01

00

01

00

01

11

01

11

10

1

1.2

1.4

1.6

1.8

2

__ X

0

0

0

1

__ 1

1

0

0

0

0

0

1

__ 1

0

1

S0

4 TRITS BTA

S3

2.2

2.4

2.6

2.8

3 x 10

S2

Z

0.5 0

S1

Y

−9

1 S1

0

__ 1

S0

X

0.5 0

S4

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3 x 10

−9

S2

1

Fig. 5.

0.5 0

The input vectors to the 4-trits Balanced Ternary Adder

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3 x 10

−9

S3

1

SUM=[S3 S2 S1 S0] = [1 1 1 1], the result of the simulation correspond with the total sum of the multiplication done in table II. S4 is ’zero’ and is not shown.

0.5 0

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3 x 10

−9

Fig. 7. A plot of the outputs from the Balanced Ternary Multiplication circuit Z3

1

Y3

0

X3

0

Z2

(3,2) BTC S4

0

Y2

_ 1

X2

0

Z1

0

Y1

0

1

S3

Z0

_ 1

0

0

(3,2) BTC

(3,2) S3

X1

BTC

S2

_ 1

0

S2

Y0

X0

0

1

R EFERENCES

(3,2) BTC S1

_ 1

0

S1

S0

0

1

’0’ (3,2) BTC S2

0

S1

_ 1

(3,2) BTC S3

0

S2

_ 1

(3,2) BTC ’0’

S4

S3

0

1

(3,2) BTC S4

0 S4

1 S3

_ 1 S2

_ 1 S1

1 S0

Fig. 6. A block diagram of the 4-trits Balanced Ternary Adder showing the propagation of the trits

III. C ONCLUSIONS In this paper a 4-trits Balanced Ternary Multiplication (BTM) circuit has been presented. It has some advantage able properties, it handles multiplication with both negative and positive numbers, which is one of the benefits using balanced ternary notation. This application shows that it is possible to build a fast multiplier circuit if we use balanced ternary notation, and by using a conventional CMOS Process. The proposed BTM operates at a clock frequency at 1 GHz at a load of 10f F .

[1] S. Stakhov, “Brousentsov’s Ternary Principle, Bergman’ Number System and Ternary Mirror-symmetrical Arithmetic,” The Computer Journal, Vol. 45, No.2, pp. 221–236, 2002. [2] A. Herrfeld and S. Hentsche, “Ternary Multiplications Using 4-Input Adder Cells and Carry Look-Ahead,” Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999. [3] K. Diawuo and H. T. Mouftah, “A Three-Valued CMOS Arithmetic Logic Unit Chip,” Proceedings of the 17th IEEE International Symposium on Multiple-Valued Logic, pp. 215–220, 1987. [4] B. Hayes, “Third Base,” American Scientist, Volume 89, Number 6, pp. 490–494, Nov-Dec 2001. [5] D. Knuth, The Art of Computer Programming, Second edition. AddisonWesley Publishing Company, 1981. [6] M. Glusker, D. M. Hogan, and P. Vass, “The Ternary Calcualating Machine of Thomas Fowler,” IEEE Annals of the History of Computing, pp. 4–22, 2005. [7] T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring GateLevel Weighted Sum and Threshold Operations,” IEEE Transactions on Electron devices, vol. 39(6), pp. 1444–1455, 1992. [8] K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked NeuronMOS Logic Circuits Employing Auto Threhold Adjustment,” IEEE International Solid-State Circuits Conference(ISSCC), pp. 320–321,388, 1995. [9] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin, “Novel Recharge Semi-Floating-Gate CMOS Logic For Multiple-Valued Systems,” Proceedings of the 2003 IEEE International Symposium on Circuits And Systems in Bangkok, 2003. [10] H. Gundersen and Y. Berg, “MAX and MIN Functions Using MultipleValued Recharged Semi-Floating Gate Circuits,” Proceedings of the 2004 IEEE International Symposium on Circuits And Systems in Vancouver, 2004. [11] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen, “Ultra-Low-Voltage Floating Gate Transconductance Amplifiers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001. [12] H. Gundersen and Y. Berg, “A Novel Balanced Ternary Adder Using CMOS Recharged Semi-Floating Gate Devices,” Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic in Singapore, p. 18, 2006.

Appendix A

ADDITIONAL INFORMATION

99

100

A.1

Measurement Information

A prototype chip was fabricated by STMicroelectronics using a 90nm CMOS process. It contained some simple RSFG structures, a Ternary-NOT circuit, an AUTO-ZERO circuit), a MAX circuit, a More-Less and Equality circuit, and a simple balanced ternary adder. The measurement equipment set-up is shown in Figure A.1 and A.2.

Figure A.1: Set-up of the measuring instruments used

A.1.1

Instruments

The instrument where controlled using the GPIB interface connected to a Linux PC, with MATLAB 7.5.0.338 installed. All scripts where written in MATLAB. The HP/AGILENT 33250 where used as the reference clock. All input signals to the chip where DC-signals generated by KEITHLEY 213. The output was measured by using 10:1 probes connected to TEKTRONIX TDS 3052. HP/AGILENT E3631A served as the power supply to the chip. The multimeter HP/AGILENT 34401A monitored the input signals. A list of the instruments I used, is given in Table A.1. Table A.1: Measurement instruments HP/AGILIENT

E3631A

Power Supply

HP/AGILIENT

33250A

Function Arbitrary Waweform Generator

HP/AGILIENT

34401A

Multimeter

KEITHLEY

213

Quad Voltage Source

TEKTRONIX

TDS 3052

Digital Oscilloscope

TEKTRONIX

TEK P6139A

Probes (500MHZ, 8.0pF, 10MΩ, 10X)

101

(a) The set-up

(b) A closer look

Figure A.2: A typical set-up of the measurement jig

A.1.2

The Prototype Printed Circuit Board

The prototype printed circuit board (PCB) was made by using FreePCB, after reading a short turtorial on PCB design [41]. FreePCB is a free, open-source PCB editor for Microsoft Windows, released under the GNU General Public License [73]. A picture of the PCB with the prototype chip is shown in figure A.4 and the layout of the PCB is shown in figure A.3.

102

Figure A.3: Layout of the PCB

Figure A.4: Picture of the PCB with the mounted prototype chip

103

104

Appendix B

ABBREVIATIONS Below are some of the abbreviations used in this thesis. ADC ALU BT CMOS CPU DLC FG FGUVMOS MAX MIN MOSFET MVL NMOS PCB PG PMOS RSFG SRAM SUS-LOC

Analog-to-Digital Converter In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations Balanced Ternary Complementary Metal Oxide Semiconductor Central Processing Unit Down Literal Circuit Floating Gate Floating Gate UltraViolet light Metal Oxide Semiconductor The MAXimum function is analogues with the OR function in binary logic The MINimum function is analogues with the AND function in binary logic Metal Oxide Semiconductor Field Effect Transistor Multiple-Valued Logic N-channel MOSFET Printed Circuit Board Pass Gate transistor P-channel MOSFET Recharged Semi-Floating Gate Static Read Only Memory SUpplementary Symmetrical LOgic Circuit

105

106

List of Figures 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13

Floating gate structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . A n-input NMOS FG transistor . . . . . . . . . . . . . . . . . . . . . . . . Capacitive division model, (a) Schematic of the transistor model with the parasictic capacitors included. (b) Equivalent capacitive divider model . . Gate structures used in FG technology . . . . . . . . . . . . . . . . . . . . A typical recharged semi-floating gate binary inverter. . . . . . . . . . . . A simple clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the simple clock generator implemented in 90nm CMOS technology, the reference clock is 1 GHz . . . . . . . . . . . . . . . . . . . Typical auto-zero elements . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocked CMOS gate, used to remove the recharge clock, to create a nonrecharged signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured output characteristics of the auto-zero element in figure 2.8(a) with input signals -1 and +1 . . . . . . . . . . . . . . . . . . . . . . . . . Measured output characteristics of the auto-zero element in figure 2.8(a) with input signal +0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured DC response of the RSFG binary inverter . . . . . . . . . . . . Measured output characteristics of the binary RSFG inverter with input signals −1 and +1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 3.2 3.3 3.4 3.5 3.6 3.7

. .

. 8 . 9 . 11 . 13 . 14 . 15 . 16 . 17 . 17 . 18 . 18

A typical RSFG MVL Inverter . . . . . . . . . . . . . . . . . . . . . . . . . A down literal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A RSFG MAX circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A RSFG MIN circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured DC response of a RSFG MVL inverter in 90nm CMOS technology Measured output charcteristics of the RSFG MAX-circuit . . . . . . . . . . Measured output characteristics of the MAX circuit with input signals (−1,−1) and (−1, +0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Measured output characteristics of the MAX circuit with input signal (−1,+1) 3.9 Measured output characteristics of a RSFG MVL inverter in 90nm CMOS technology with input signal +1 and −1 . . . . . . . . . . . . . . . . . . . . 3.10 Measured output characteristics of a RSFG MVL inverter in 90nm CMOS technology with input signal +0 . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2

6 7

23 25 25 26 26 27 28 28 29 29

A more, less or equal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 A typical output plot of the more, less or equality circuit . . . . . . . . . . . 34 107

4.3 4.4 4.5 4.6

Measured output characteristics of the RSFG MLE circuit in 90nm Technology A Ternary Switching Element . . . . . . . . . . . . . . . . . . . . . . . . . . Vout vs Vin of the ternary switching element, the supply voltage; Vdd = 2V Measured output characteristics of the RSFG MLE circuit in 90nm CMOS Technology with input signals (−1,−1) and (−1,+1) . . . . . . . . . . . . . Measured output characteristics of the RSFG MLE circuit in 90nm CMOS Technology with input signal (+1,−1) . . . . . . . . . . . . . . . . . . . . .

35 36 37

40 43 44 45

5.6 5.7

A RSFG balanced ternary adder . . . . . . . . . . . . . . . . . . . . . . . . . A balanced ternary (4,2) counter . . . . . . . . . . . . . . . . . . . . . . . . An example of a 4 trits parallel balanced ternary adder using (4,2) counters An example of a balanced ternary multiplication . . . . . . . . . . . . . . . . Measured output characteristics of the BTA circuit, with input signal (−1, −1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured output characteristics of the BTA circuit, with input signal (+0,+0) Measured output characteristics of the BTA circuit, with input signal (+1,+1)

A.1 A.2 A.3 A.4

Set-up of the measuring instruments used . . . . . . A typical set-up of the measurement jig . . . . . . . Layout of the PCB . . . . . . . . . . . . . . . . . . . Picture of the PCB with the mounted prototype chip

4.7 5.1 5.2 5.3 5.4 5.5

108

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38 38

45 46 46 101 102 103 103

Bibliography [1] M. Aline, T. Saidi, and E. D. Olson. Design and Characterization of a Low Power Ternary DSP. International Signal Processing Conference, 2003. [2] R. Appleyard. The Direct Measurement of the Napierian Base. Proc. Phys. Soc. London, 26:178–182, 1913. [3] Snorre Aunet. Real-time Reconfigurable Devices Implemented in UV-light Programmable Floating-Gate CMOS. Dr. Scient. thesis, Department of computer and information science, Norwegian University of Science and Technology (NTNU), 2002. ISBN 82-471-5447-1. [4] V. Beiu, J. M. Quintana, and M. J. Avedillo. VLSI Implementation of Threshold Logic-A Comprehensive Survey. IEEE Transactions on Neural Networks, 14(5):1217– 1243, 2003. [5] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin. Novel Recharged Semi-FloatingGate CMOS Logic for Multiple-Valued Systems. Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 5:193–196, 2003. [6] Y. Berg, S. Aunet, Ø. Næss, J. G.Lomsdalen, J. Bush, and M. Høvin. Binary Input Multiple-Valued Recharge CMOS Full-Adders. Euopean Conference on Circuit Theory and Design, Poland, pages 365–368, 2003. [7] Y. Berg, S. Aunet, Ø. Næss, and O. Mirmotahari. Basic Multiple-Valued Functions using Regharge CMOS Logic. Proceedings of the 34th International Symposium on Multiple-Valued Logic, pages 346–351, 2004. [8] Y. Berg, S. Aunet, Ø. Næss, O. Mirmotahari, and M. Høvin. Binary to MultipleValued Recharge Converter for Multiple-Valued CMOS logic. Euopean Conference on Circuit Theory and Design, Poland, pages 349–352, 2003. [9] Y. Berg, R. Jensen, J. G. Lomsadalen, H. Gundersen, and S. Aunet. Fault Tolerant CMOS Logic using Ternary Gates. Proceedings IEEE 37th International Symposium on Multiple-Valued Logic, 2007. [10] Y. Berg and T. S. Lande. Programmable Floating-Gate MOS Logic for Low-Power Operation. IEEE International Symposium on Circuits and Systems, 3:1792–1795, 1997. 109

[11] Y. Berg, T. S. Lande, O. Næss, and H. Gundersen. Ultra Low-Voltage Floating Gate Transconductance Amplifiers. IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, 48(1), Jan. 2001. [12] Y. Berg, O. Mirmotahari, P. A. Norseng, and S. Aunet. Ultra Low Voltage CMOS Gates. Proceedings of the 13th International Conference on Electronics, Circuits and Systems, pages 818–821, 2006. [13] Y. Berg, O. Næss, M. Høvin, and H. Gundersen. Ultra Low-voltage Floating-gate (FGUVMOS) Amplifiers. Analog Integrated Circuits and Signal Processing, 26:63–73, 2001. [14] N. P. Brusentov. The Computer ’Setun’ of Moscow University. Material of the Scientific-technical Conference: New Developments in Computational Mathematics and Computing Techniques, pages 226–234, 1960. [15] J. R. Burns and R. A. Powlus. Threshold Circuit Utilizing Fields Effect Transistors. U.S. Patent 3 260 863, July 12, 1966. [16] R. S. Chau. Intel’s Breakthrough in High-K Gate Dielectric Drives Moore’s Law Well into the Future. Technology@Intel Magazine, pages 1–7, January 2004. [17] M. Davis and Emil L. Post. His Life and Work, in M Davis (ed.), Solvability, Provability, Definability: the Collected Works of Emil L Post. Boston, MA, pages xi–xxviii, 1994. [18] K. Diawuo and H. T. Mouftah. A Three-Valued CMOS Arithmetic Logic Unit Chip. Proceedings of the 17th IEEE International Symposium on Multiple-Valued Logic, pages 215–220, 1987. [19] C. Duffy and P. Hasler. Scaling pFET Hot-Electron Injection. 10th International Workshop in Computational Electronics, pages 140–150, 2004. [20] D. Etiemble. On the Performance of Multiplevalued Integrated Circuits: Past, Present, and Future. Proceedings of the 22th International Symposium on MultipleValued Logic, pages 156–164, 1992. [21] D. Etiemble. Why M-Valued Circuits are Restricted to a Small Niche? Journal of Multiple-Valued Logic and Soft Computing, 10:109–123, 2003. [22] R. Fowler and L. Nordheim. Electron Emission in Intense Electric Fields. Proceedings of the Royal Society of London. Series A, Containing Papers of a Mathematical and Physical Character, 119(781):173–181, May 1928. [23] M. Glusker, D. M. Hogan, and P. Vass. The Ternary Calcualating Machine of Thomas Fowler. IEEE Annals of the History of Computing, pages 4–22, 2005. [24] H. Gundersen. Design of Low-Voltage Analog Amplifiers Using Floating-Gate Transistors. Cand. Scient. thesis, Department of Informatics, University of Oslo, Norway, 2000. 110

[25] H. Gundersen. On the Potential of CMOS Recharged Semi-Floating Gate Devices Used in Balanced Ternary Logic. Proceedings of the 17th International Workshop on Post-Binary ULSI Systems, 2008. [26] H. Gundersen and Y. Berg. MAX and MIN Functions Using Multiple-Valued Recharged Semi-Floating Gate Circuits. Proceedings of the 2004 IEEE International Symposium on Circuits And Systems, Canada, pages 857–860, 2004. [27] H. Gundersen and Y. Berg. A Balanced Ternary Multiplication Circuit using Recharged Semi-Floating Gate Devices. Proceedings IEEE 24th Norchip Conference, pages 205–208, 2006. [28] H. Gundersen and Y. Berg. A Novel Balanced Ternary Adder Using CMOS Recharged Semi-Floating Gate Devices. Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic, Singapore, pages 18–21, 2006. [29] H. Gundersen and Y. Berg. A Novel Ternary More, Less and Equality Circuit Using Semi-Floating Gate Devices. Proceedings IEEE International Symposium on Circuits and Systems, pages 3169–3172, 2006. [30] H. Gundersen and Y. Berg. Fast Addition using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. Proceedings IEEE 37th International Symposium on Multiple-Valued Logic, 2007. [31] H. Gundersen, R. Jensen, and Y. Berg. A Novel Ternary Switching Element Using CMOS Recharged Semi-Floating Gate Devices. Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic, Canada, pages 54 –58, 2005. [32] B. Hayes. Third Base. American Scientist, 89(6):490–494, Nov-Dec 2001. [33] A. Herrfeld and S. Hentsche. Ternary Multiplications Using 4-Input Adder Cells and Carry Look-Ahead. Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999. [34] P. H¨afliger and H. K. O. Berge. Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation. IEEE Transactions on Circuits and Systems-II: Express Briefs, 54(2):127–130, February 2007. [35] M. Inaba. Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007. [36] M. Inaba, K. Tanno, and O. Ishizuka. Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. Proceedings of the 31nd IEEE International Symposium on Multiple-Valued Logic, pages 27–32, 2001. [37] M. Inaba, K. Tanno, and O. Ishizuka. Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. Proceedings of the 32nd IEEE International Symposium on MultipleValued Logic, pages 282–288, 2002. 111

[38] M. Inaba, K. Tanno, and O. Ishizuka. Analog Inverter with Neuron-MOS Transistors and Its Application. IEICE Trans. Fundamentals, E85-A(2):360–365, Feb. 2002. [39] Engineneering Research Associates Inc. High-Speed Computing Devices. McGrawHill, 1950. [40] R. Jensen, H. Gundersen, J. G. Lomsdalen, and Y. Berg. Recharged Comparator and Multiple-Valued N-ary Frequency Divider. Proceedings of the 15th International Workshop on Post-Binary ULSI Systems, pages 51–54, 2006. [41] D. L. Jones. PCB Design Turtorial. www.alternatezone.com - Revision A - June 29th 2004, pages 1–25, 2004. [42] D. Kangh and S. M. Sze. A Floating Gate and Its Application to Memory Devices. The Bell System Technical Journal, 46(4):1288–1295, 1967. [43] E. Kinvi-Boh and E. D. Olson. MVL Circuit Design and Characterization at the Transistor Level Using SUS-LOC. Proceedings of the 33rd International Symposium on Multiple-Valued Logic, pages 105–110, 2003. [44] Donald Knuth. The Art of Computer Programming, Second edition. Addison-Wesley, 1981. Vol 2. Seminumerical Algorithms, pages 190-193. [45] K. Kotani, T. Shibata, M. Imai, and T. Ohmi. Clocked Neuron-MOS Logic Circuits Employing Auto Threhold Adjustment. IEEE International Solid-State Circuits Conference, pages 320–321, 1995. [46] Kotarbinsky. Jan Lukasiewicz’s Works on the History of Logic. Studia Logica 8, pages 57–62, 1958. [47] T. S. Lande, D. T. Wisland, T. Sæther, and Y. Berg. FLOGIC - Floating-Gate Logic for Low-Power Operation. Proceedings of the 3rd IEEE International Conference on Electronics, Circuits and Systems, pages 1041–1044, 1996. [48] D. Lee, D. Blaauw, and D. Sylvester. Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 12(2):155–166, February 2004. [49] Thomas H. Lee. The Design of CMOS Radio-Frequency Intergrated Circuits. Cambrigde University Press, First Edition, 1998. [50] J. E. Lilienfeld. Method and Apparatus for Controlling Electric Currents. U.S. Patent 1,745,175. Application filed October 8, 1926, granted January 18, 1930. [51] Ø. Næss. Non-Volatile and Volatile Floating-Gate Circuits and Programming Techniques. Dr. Scient. thesis, Faculty of Mathematics and Natural Sciences, University of Oslo Unipub, 2005. ISSN 1501-7710, No. 413. [52] Ø. Næss, Y. Berg, and T. S. Lande. Low-Voltage Circuits using Pseudo Floating-Gate Transistors. Proceedings of 20th IEEE Norchip Conference, pages 272–277, 2002. 112

[53] E. D. Olson. Supplementary Symmetrical Logic Circuit Structure. Proceedings of the 29th International Symposium on Multiple-Valued Logic, pages 42–47, 1999. [54] E. D. Olson and K. W. Current. Demonstration of ”Supplementry Symmetrical Logic Circuit Structure” Concepts Using A MOS Test Chip. Multiple Valued Logic Journal, 7:1–23, 2001. [55] E. D. Olson and K. W. Currrent. Hardware Implementation of ’Supplementary Symmetrical Logic Structure’ Concepts. Proceedings of the 30th International Symposium on Multiple-Valued Logic, pages 371–376, 2000. [56] INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE (INRIA) Team R2D2. Reconfigurable and Retargetable Digital Devices. Activity Report 2004, page 11, 2004. http://www.inria.fr/rapportsactivite/RA2004/r2d2/r2d2.pdf. [57] T. N. Rajashekhara and I. E. Chen. A Fast Adder Design Using Signed-Digit Numbers and Ternary Logic. Proceedings of the 1990 IEEE Southern Tier Technical Conference, pages 187–194, 1990. [58] Jaime Ram´ırez-Angulo, Carlos A. Urquidi, Ramon Gonz´alez-Carvajal, Antonio Torralba, and Antonio L´ opez-Mart´ın. A New Family of Very Low-Voltage Analog Circuits Based on Quasi-Floating-Gate Transistors. IEEE Transactions on Circuits and Systems-II: Analog AND Digital Signal Processing, 50(5):214–220, 2003. [59] I. G. Rosenberg. La structure des fonctions de plusieurs variables sur un ensemble fini. C.R. Acad. Sci. Paris, Ser. A.B., 260:3817–3819, 1965. [60] I. G. Rosenberg. Uber die functionale Vollstandigkeit in den mehrwertigen Logiken. Rozpravy Ceskoslovenske Akademie Ved. Ser. Math. Nat. Sci., 80:3–93, 1970. [61] J. Shen, M. Inaba, K. Tanno, and O. Ishizuka. Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. Proceedings of the 30nd IEEE International Symposium on Multiple-Valued Logic, pages 15–20, 2000. [62] J. Shen, K. Tanno, and O. Ishizuka. Down Literal Circuit with Neuron-MOS Transistors and Its Applications. Proceedings of the 29nd IEEE International Symposium on Multiple-Valued Logic, pages 180–185, 1999. [63] T. Shibata and T. Ohmi. An Intelligent MOS Transistor Featuring Gate-level Weighted Sum and Threshold Operations. IEDM Technical Digest, pages 919–922, 1991. [64] T. Shibata and T. Ohmi. A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Transactions on Electron Devices, 39(6):1444–1455, 1992. [65] T. Shibata and T. Ohmi. Neuron MOS Binary-Logic Integrated Circuits-Part I: Designs Fundamentals and Soft-Hardware-Logic Circuit Implementation. IEEE Transactions on Electron Devices, 40(3):570–576, 1993. 113

[66] T. Shibata and T. Ohmi. Neuron MOS Binary-Logic Integrated Circuits-Part II: Simplifying Techniques of Circuit Configuration and Their Practical Applications. IEEE Transactions on Electron Devices, 40(5):974–979, 1993. [67] K. C. Smith. Multiple-Valued logic: A Tutorial and Appreciation. IEEE Computers, 21:17–27, 1988. [68] E. S´anchez-Sinencio and A. G. Andreou. Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits . Wiley, 1998. [69] S. Stakhov. Brousentsov’s Ternary Principle, Bergman’ Number System and Ternary Mirror-symmetrical Arithmetic. The Computer Journal, 45(2):221–236, 2002. [70] M. Syuto, J. Shen, K. Tanno, and O. Ishizuka. Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Funcions. Proceedings of the 30nd IEEE International Symposium on Multiple-Valued Logic, pages 27–32, 2000. [71] C. Urquidi and J. Ram´ırez-Angulo. A New Family of Low Voltage Circuits Based on Quasi Floating Gate Transistors. IEEE Midwest Symposium on Circuits and Systems, pages 93–96, 2002. [72] Z. G. Vranesic and V. C. Hamacher. Threshold Logic in Fast Ternary Multipliers. Proceedings of the 1975 IEEE International Symposium on Multiple-Valued Logic, pages 373–387, 1975. [73] Allan Wright. FreePCB - A free open-source PCB editor for Microsoft Windows. http://www.freepcb.com, 2007. [74] K. Yang and A. G Andreou. A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET. Journal of Analog Integrated Circuits and Signal Processing, 6(3):197–208, 1994.

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