Automatic Layout Generation of RF Embedded Passive Designs Mohit Pathak, Satya Vadlamudi, Josh Beaver, and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology
[email protected] Abstract In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. Physical layout generation of such designs is challenging since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. Our approach is to make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits.
I. INTRODUCTION Embedded passive is an emerging technology that has a potential for increased reliability, improved electrical performance, size shrinkage and reduced cost [1]. Using this technology, surface-mount passive components used in systems are integrated into packaging substrate via multiple layers. However, the design of circuits with embedded passives is non-trivial due to the electromagnetic interactions that cause parasitics, leading to non-ideal frequency behavior. In this paper we target RF embedded passive filter designs using liquid crystalline polymer (LCP) substrate. Layout generation for such designs is not an easy task. The desired response of a given layout is tightly coupled with the response of each of the individual components and the effect of parasitics due to interconnects between them. The manual design cycle for generation of such layouts can be extremely time-consuming. A minor change in the layout may cause a drastic change in the frequency response. A conventional design flow tries to optimize circuit performance at the layout level at the premium cost of time-consuming EM iterations (using a
full-wave EM simulation tool like SONNET) for entire layouts. Our goal is to develop a tool that quickly generates and optimizes RF embedded passive circuits in LCP substrate automatically. An early work [2] targets primarily CMOS technology, not packaging substrate such as LCP or LTCC. They do not describe a way of estimating parasitics for more than 2-pin nets. Such an approach would not work for RF embedded passive circuit since knowing the exact nature of interconnect parasitics is critical. Sommer et al. [3] presented a layout synthesis algorithm for embedded passive components such as capacitor, resistor and inductor. But, they did not discuss how to use them to construct an entire circuit. Mukherjee et al. [1] discuss another technique for automating the design of passive components. They also suggest how to analyze an entire embedded passive circuit, but their approach is limited to optimizing a given layout instead of constructing one. Our contribution is a design methodology that automates the design process of LCP-based embedded passive designs from its circuit model to the layout. We make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages of the methodology to obtain the desired goals. Full-wave EM simulations is completely out of the design loop. Thus, our methodology significantly reduces the design time for RF embedded passive circuits. In addition, we provide the designer with an initial layout solution that closely matches the desired response. Since it is easier to tweak a given good solution to meet the desired goals rather than starting from scratch, our design flow can help reduce design times significantly. II. PRELIMINARIES
A. Problem Formulation We assume that the following are given: (i) a netlist of the given RF circuit consisting of a set of passive components (we restrict ourselves to inductors and capacitors for RF filter designs) and nets, (ii) initial value of the components, (iii) a set of design goals such as center/resonent frequency, bandwidth, insertion loss, etc, (iv) a parameterized library that consists of inductors, capacitors, interconnects, and coupling models. The goal of Embedded Passive Physical Design is to automatically generate a layout of the given circuit (= placement and routing of the components) such that the performance objectives are achieved and the area of the layout is minimized. Our target packaging substrate consists of two metal layers separated by a LCP layer for component placement (= minimum required to place a capacitor) and routing [1]. B. Design Flow Our approach is to optimize the component placement using Simulated Annealing and component routing using parasiticaware maze-routing. We perform non-linear optimization at various steps of the layout generation process to meet the desired performance objectives while minimizing the area of the layout. Our method consists of the following steps:
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. Step 1: component shapes are chosen from the library based on their initial values. . Step 2: these components are resized during our pre-layout optimization step by ADS (Advanced Design System by Agilent), a circuit-level simulator and optimizer. This is necessary to consider the effects of various component parasitics such as vias connecting to ground, wire connection from the core to boundary, etc. The geometric shapes change slightly during this step. . Step 3: we perform placement and routing using the optimized components. Component coupling and wire parasitics are introduced during this step. The objectives during this step include layout area, wirelength, and routability. We save K1-best layouts based on these objectives. * Step 4: for each of the Kl-best layouts, we derive the circuit model and evaluate using ADS. The goal is to select K2-best layouts that achieve the responses that are closest to our goals. The circuit model of the components and their coupling are extracted from the placement, whereas the wire and via parasitics are derived from the routing. . Step 5: for each of the K2-best layouts, we perform non-linear circuit optimization again using ADS on the entire layout. The components and wires are again re-sized during this step so that the overall circuit response best meets our goals. . Step 6: The white space introduced during the post-layout optimization step is removed during our layout compaction step. The goal is to preserve the circuit response while optimizing the layout area. The component placement and routing change slightly during this step. In case the final compacted layout passes our final circuit-level verification, we perform a full-wave EM simulation using SONNET for final verification. If not, we repeat the entire process starting from placement and routing (or even component selection and optimization). Our final solution can be used for further manual touch-up if necessary. III. PRE-LAYOUT OPTIMIZATION The objective of our pre-layout optimization is to find optimized component dimensions which meet the desired circuit objectives while considering intra-component parasitics. The circuit elements in each component are grouped into two categories, namely, dominating elements, and parasitic elements. The dominating element values reflect the main inductance or the capacitance value of a given component. During initial selection, the components were selected based on their dominating element values. Due to the effect of parasitics in each component, the initial selection does not always meet the desired circuit response. The goal of our pre-layout optimization is to find new components (possibly with new dimensions) such that they meet the desired circuit responses while considering both the dominating and parasitic elements. In addition to intra-component parasitics, additional parasitics such as vias connecting to ground, core-to-boundary elongation are also modeled. Due to these
changes in the circuit model, the overall shape of the component after the optimization may change. Note that the optimization is applied not to individual components but to the circuit model of the entire design. Since the optimization is performed before placement and routing, the effect of interconnect parasitic and component coupling are not considered in this case. Note that our post-layout optimization step does consider these layout-based parasitics. To optimize a given unplaced/unrouted circuit, we use Agilent's Advanced Design System (ADS) engine to perform nonlinear optimization. The basic idea is that during the optimization process, the parasitic element values of all components are fixed while the dominating element values are changing. The optimization process finds the optimal values of dominating elements. For every component with new dominating element value, we replace it using our library. Since the new component has different dominating value, the parasitics are also different in this new component. We then repeat the overall process until the response of the overall design meets our goal or the change in the response is minimal. More specifically, we first fix the parasitic element values and makes the dominating element values as variables for the optimization engine. Next we find the maximum and minimum value for dominating elements of each component based on the available values in library. The optimization engine is then called. Next we update the current solution based on the values (both dominating and parasitic elements) obtained from the optimization engine. The above process is repeated while the maximum change in dominating element values is below a threshold or the maximum number of iterations is reached.
IV. PLACEMENT AND ROUTING The main objective of our placement and routing step is to find good candidate layouts which are optimized for area, wirelength, and routability. From a given candidate placement solution, we actually perform routing to accurately decide whether the given placement is routable. Since the routing resource is restricted to two metal layers, and the wires and vias add significant parasitics to the overall design, wirelength and routing completion are very important goals. In addition, the area objective also play an important role in determining the overall wirelength as well as coupling among the components. The ultimate goal in our embedded passive layout is to meet the desired goals in terms of frequency responses, which can be judged by a circuit simulator such as ADS or EM simulator such as SONNET. However, layout optimization using these tools is extremely time-consuming if not impossible. Thus, we sample "good initial layouts" that are optimized in terms of area, wirelength, and routability, and then choose the best one out of these using ADS as the verification engine. As discussed in Section II-B, we save the K1-best layouts based on area, wirelength, and routability objectives. For each of the K1-best layouts, we derive the circuit model and evaluate using ADS. The goal is to select K2-best layouts that achieve the responses 116
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