Backend CAD Flows for "Restrictive Design Rules" Mark Lavin, Fook-Luen Heng, Greg Northrop IBM Research Division Thomas J. Watson Research Center Yorktown Heights NY
[email protected],
[email protected],
[email protected] Section 5 discusses some initial work to implement this approach.
ABSTRACT: To meet challenges of deepsubwavelength technologies (particularly 130nm and following), Lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETs like altPSM. For emerging technologies (65nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the Design->Silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. We have been exploring how Design might take advantage of these restrictions, and will present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPC/RET algorithms and the accuracy of models of manufactured products. We also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to Design For Manufacturability (DFM).
2 THE PROBLEM The problem (actually, one of the problems) of Design-through-Manufacture of advanced technology is the decreasing ability to control the physical properties of fabricated devices and interconnects relative to models used for design closure and optimization. One of the main sources of variability is lithographic patterning. Lithographers relate “degree of difficulty” to the inverse of Rayleigh k1 factor. Figure 1 (from [2]) shows how that factor has been declining and its effect on pattern fidelity. conventional
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1 INTRODUCTION
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Figure 1 Pattern Fidelity vs. Lithographic k1
It’s now widely accepted that manufacturability, along with noise, power, and designer productivity, is one of the major problems for VLSI. This has led to growing interest in Design For Manufacturability (DFM), although there is not complete consensus about what this term means[1]. In this paper, I discuss one possible aspect of DFM, the idea of restrictive design rules (RDRs) and exploiting these restrictions throughout the layout flow. Section 2 and Section 3 motivate this idea by describing the Manufacturability problem and several solution approaches. Section 4 outlines our RDR-based approach and 0-7803-8702-3/04/$20.00 ©2004 IEEE.
introduce RET
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widespread RET
O R = k1 -------NA 0.8
The decreasing ability of lithography to control structure in the XY plane is compounded by problems in other dimensions: difficulty controlling layer thickness in processes like deposition and CMP [3] and material limits like gate oxide thickness. Also, the ability to control properties of composed materials (e.g., doped semiconductors) is reaching material limits. Because the variability of shapes and physical properties is not decreasing proportionally to nominal feature size, the variability in properties
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Other so-called Resolution Enhancement Techniques (RETs) such as sub-resolution assist features and phase-shifting masks use properties of the optical projection process to reduce the minimum resolvable feature size and decrease sensitivity of the printed shapes to process variations (dose, focus, and mask dimensions).
relevant to design like device performance, wire delay, and leakage are increasing, and for design methodologies that depend on worst-case properties, the benefits of new technologies are small, if any.
3 POTENTIAL SOLUTIONS 3.1
Pray for a (process) Miracle
While OPC and RETs try to make the fabricated shapes resemble the designed shapes as closely as possible, other techniques such as shape filling/slotting and the addition of contact “landing pads” deliberately modify the intended wafer shapes to ones that are easier to fabricate (e.g., a uniform areal shape density) or more forgiving of process effects like layer-to-layer misregistration.
If low k1 is one of the main causes of the problem, then why not “simply” increase k1, by reducing stepper wavelength or increasing NA or both? The first leads to proposals for Next Generation Lithography (NGL) tools based on shorter wavelength energy sources like 157nm deep ultraviolet light, soft X-rays (EUV) [4], projection e-beams and ion beams. Trying to increase NA has led to more recent proposals for immersion steppers [5] in which NA is increased by introducing fluid with higher index of refraction than air between the optics and the wafer.
These “data process” (vs. physical process) techniques have several problems: First, the computational cost of implementing them is becoming a significant adder to post-tapeout cost and turn-around time. Runtimes of days on large SMPs for a single mask layer are not unusual, although these can be reduced through the use of massive distributed parallelization. Second, as the complexity of the techniques increase, it becomes far more difficult to ensure their correctness, particularly when the set of design geometries is open-ended. Algorithm errors and incorrect settings of tuning parameters can result in fatal defects; this fact has given rise to the use of extensive post-OPC/RET checking, further increasing computation time and cost. The third problem with post-tapeout data processes is that it may not be possible to insulate the designer from them completely. For example, the introduction of fill shapes on interconnect levels may affect wire parasitics to an extent that could affect design closure. Some of the RETs, notably alternating phase shift masks (altPSM), impose additional constraints on layouts (e.g., no T junctions at critical dimensions) that are hard to check and correct using conventional DRC techniques.
In addition to the cost (and risk) of the equipment to support these NGLs, they raise a host of issues about resist materials and mask costs. Furthermore, even if lithographic k1 could be increased by process improvements, sources of variability in other processes (etch, CMP) may not be controllable, so that we would have to pray for multiple process miracles.
3.2 Post-tapeout Manufacturability Enhancement Another approach to controlling the increasing variability of VLSI fabrication is to compensate for the systematic components of shape variability by transforming as-designed shapes to those that are written on the photomasks used to pattern the silicon. Some of those modifications, like optical proximity correction (OPC) attempt to compensate for systematic shape distortions of fabrication processes by applying inverse distortions when converting design shape to mask shapes; these are generally called Optical Proximity Correction (OPC) even though they compensate other process effects as well as optical projection.
3.3 Design For Manufacturability (DFM) The problem of not being able to hide RETs like altPSM from designers behind the “tapeout
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layouts that designers or tools produce and that fabrication processes must reproduce. These restrictions include requiring that gate-forming polysilicon features all have the same orientation and width, and are placed at a fixed pitch. This is the approach that we have taken in our work, described in the following sections.
wall” has been one of the factors motivating the recent increase of interest in Design for Manufacturability (DFM). In fact, DFM is hardly new: design rules and DRC exemplify DFM by abstractly representing and verifying process capabilities for layout structures. However, standard DRC does not handle process requirements like “phase-shiftability” very well, and DRC decks are growing more complex and design rules more conservative with each successive technology.
4 PROPOSED SOLUTION We are exploring how design restrictions could improve the manufacturability of designs in a project we call L3GO (Layout using Gridded Glyph Geometry Objects). Our approach has been to extend the design restrictions on polysilicon features mentioned above to all layers of a design, and then tailor the layout flow and tools to take advantage of these restrictions.
DFM tries to address these problems by manufacturability details more directly to the design processes. A number of “manufacturing-aware” point tools have been described, including cell generators, placers, routers[6,7], and fill-shape generators [8], all of which augment traditional tools by adding elements to the objective functions they are optimizing that account for yield and process window.
4.1
L3GO layouts have conventional overall structures (cells and layers). Like approaches going back to Mead & Conway [12], shapes are defined by a coarse grid, typically a simple fraction of the minimum manufacturable feature pitch, and three types of glyphs, shown in Figure 2: x Point glyphs: 0-dimensional points lying at grid points, typically used for vertical interconnections (contacts and vias). x Stick glyphs: 1-dimensional line segments drawn between two grid points, typically used for FET gates or for interconnections. x Rectangle glyphs: 2-dimensional, axisaligned rectangles whose vertices are on grid points, typically used for diffusion regions.
Grobman [9] and others have proposed the idea of manufacturability sign-off for hard IP blocks, which would verify various aspects of manufacturability including adherence to mask-making rules, defect-limited yield, variability leading to circuit-limited yield, etc. While these proposals seem desirable, they have the problem of further tying IP to specific a specific fabricator and process, and beg the question of what designers could do when the manufacturability checks fail. It has also been recognized that DFM flows will require additions to the information that current passes between different point tools, including “design intent” information flowing downstream (layout generation to layout verification to mask-making to fabrication) as well as “process capability” information flowing upstream. SI2 has organized a consortium, the Design To Manufacturing Coalition (DTMC), to develop an open software standard to address these requirements [10].
3.4
Restrictive Design Rules
V1 M2 M1
DIFF POLY
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Design Restrictions
Recently, researchers in companies including IBM [2] and Intel [11] have proposed an approach complementary to making design processes more manufacturing aware: restricting the
Figure 2: L3GO Grid and Glyphs
In addition to their grid-based geometry and identity, glyphs can have attributes describing
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interprets a set of rules, where the pattern specifies a local configuration of glyphs and glyph parts connected by geometric relationships and the transformation specifies how the pattern’s geometric elements are transformed into shapes in terms of combinations of primitive actions (expand, move-edge, add-feature, etc.)
circuit identity and other “design intent” information.
4.2
Backend CAD Flow
4.2.1 Layout Creation L3GO layouts can be generated using conventional layout editors and represented in standard representations including GDSII. We have developed a small amount of extension language code (SKILL) for the Cadence Virtuoso™ layout editor that constrains L3GO inputs to lie on the prescribed grids. We have also developed versions of our SKILL-based layout generators that output in L3GO format.
In addition, the elaboration process provides a point of control in which the design intent information carried on the glyphs (e.g., identification of shapes on timing-critical nets) can be converted into geometric intent information that could be carried as attributes of the target shapes.
4.2.2 Layout Verification Unlike convention layouts, which can require hundreds of design rules, L3GO layouts are subject to a few dozen design rules. These rules can be checked using conventional DRC tools (our current implementation uses Cadence’s DIVA™), but we plan to implement checking directly on the L3GO data model to take advantage of the fact that the L3GO rules can be easily specified and checked in terms of allowed and forbidden patterns, illustrated by Figure 3 for contacts or vias, where the circle is a reference via, and the X’s and +’s indicate where other vias are forbidden/allowed.
+ + + + + + + + +
+ + + X + X + + +
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+ X X X X X X X +
+ + + X X + + +
+ X X X X X X X +
+ + + X + X + + +
+ + + X + X + + +
4.2.4 “DataPrep” The target shapes from elaboration are converted into mask shapes using the conventional posttapeout data. Beyond the conventional flow, the geometric intent information could be used automatically by point tools like OPC to set correction targets, specify segmentation, etc. In addition, DataPrep (and all sequences of processes that start with glyphs) can exploit the fact that using grids and glyphs restricts the possible local configurations sufficiently that it becomes feasible to extract those local configurations “on the fly” and use them as keys to a pattern cache that can store the results of computation so that subsequent appearances of a local configuration can be looked-up on the cache rather than recomputed
+ + + + + + + + +
4.2.5 Simulation The L3GO flow extends beyond the generation of mask shapes (which would be sent to a mask fabricator for fracturing and mask writing) in two further steps. The first of these, throughprocess simulation, uses process simulators (e.g., Mentor CalibreOPC™) to transform the mask shapes into predicted wafer shapes. This is done for a number of values of process variables (e.g., dose, focus and mask bias), in order to predict the nominal wafer shapes and also their variability; Figure 4 illustrates this for a
Figure 3: Pattern-based L3GO layout rules
4.2.3 Elaboration One of the key elements of the L3GO flow is the conversion of glyphs into conventional-looking target shapes, which we call elaboration. Elaboration is implemented by a program that
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ability. These, in turn, can be used as the input to statistical timing tools [13].
small area of polysilicon features varying in focus.
4.3
Analysis of Proposed Solution
4.3.1 Benefits The use of restrictive design rules (RDRs) in the L3GO backend flow has several advantages over shape-based layouts: The first formed the initial impetus for RDRs: They enhance manufacturability, both directly (fixed pitch and orientation features are less sensitive to variation of focus, etc.) and they make RETs like altPSM or SRAFs easier to generate and “hide” from designers. A second advantage of L3GO is that it insulates designers from “technology churn”: small changes in design rules can be implemented in the Elaboration step without having to change the L3GO rules or modify existing L3GO layouts. This insulation may also facilitate migration of layouts from one technology node to the next.
Figure 4: Wafer contours simulated through focus
Although this kind of simulation (and the DataPrep preceding it) are computationally expensive, we depend on L3GO’s restriction of designs and the use of pattern caching to make it practical.
A third advantage, already noted above, is that the restriction of designs makes it feasible to do more accurate analysis of circuit properties and their variability, which can result in designs being less subject to “padding” and “safe-siding”. In addition, the restriction of designs allows more exhaustive checking of the increasinglycomplex RET and OPC algorithms, and the more targeted design of test structures.
4.2.6 Quality of Results Computation The nominal values and variations predicted by through-process simulation must be transformed from geometric quantities like edge-placement error (EPE) into properties meaningful to design closure and optimization like timing, leakage and yield (the inverse of the conversion in Elaboration).
The fourth advantage of the L3GO approach is the reduction of computation cost for all downstream data – target shapes, mask shapes, simulation results, even QOR results – through the use of pattern caching.
The quality of results computation uses the predicted contours of one or more layers and layerspecific techniques to compute electrical properties For example, device properties like length, width and leakage are calculated using a layout device extractor, based on polysilicon and diffusion contours. Interconnect properties like contact resistance are computed using shape manipulation and Monte Carlo simulation.
4.3.2 Costs, Disadvantages, Problems Of course there are costs for the cited benefits: The one most often cited is area density of designs; surely, people reason, restricted designs can’t be hand-crafted the way conventional designs can. However, our experiments with early 65nm designs show that L3GO does not impose significantly more restriction than the technology requirements themselves. A second poten-
These quantities can be used as input to simulators for timing, power, noise to give a more accurate estimate of their nominal values and vari-
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tial cost is learning a new set of layout and analysis tools. Our discussions with designers has suggested this cost is minimal and designers actually prefer the L3GO representation as more directly conveying their “layout intent.” A third potential problem of RDRs and L3GO is the argument “what if a miracle does occur?” That is, what if a breakthrough in technology alleviates process variablility to a degree that obviates the advantages? We believe that there are as likely to be significant qualitative changes on the scaling path, like new structures (SOI, FinFets) and material problems as well as miracles, and that the L3GO flow provides a more coherent framework for handling these.
5 STATUS AND RESULTS-TO-DATE
ContactedEnd layer = M1_L3GO, endCap = 140 nm End layer = PC_L3GO, endCap = 80 nm
Multiple elaborations possible Choices made in litho. context With design annotation could reflect design intent as well
To date (August, 2004) we have implemented prototypes of the “forward” part of the L3GO flow: As mentioned above, there are two mechanisms for generating layouts, using a graphical layout editor and an algorithmic layout generator. We have also implemented a library of C++ classes comprising the L3GO data model, including L3GO_Glyphs, L3GO_Grids, L3GO_TargetShapes, etc. Currently those are built on top of conventional data model classes from the IBM Niagara shape processing system, and we intend to migrate the L3GO data model to OpenAccess, using that API’s extension facilities.
ContactedPoint layer = M1_L3GO, endCap = 140 nm End layer = PC_L3GO, right-ext = 20 nm, top-ext = 40
Figure 5: Elaborations using two different rules
As shown in Figure 5, even a simple set of rules allows specifying different types of elaborations to match the capabilities of the process. One of the areas of greatest technical risk was pattern caching, so we have started to experiment with its effectiveness using 65nm technology designs consisting of automatically placed and routed macros with cells created by the algorithmic layout creation tool. The experiments proceed as follows: We use the pattern caching mechanism to fill a cache by processing macros using a left-to-right vertical scan line. Patterns consist of glyphs or glyph parts plus their surroundings out to a radius of 600nm, which realistically reflects the radius of influence for optical effects in this technology (using high-NA 193nm optical projection).
We have implemented a prototype rule-based Elaborator that takes a text file description described above and applies it to L3GO designs represented as GL1 (IBM proprietary stream) or GDSII files. The prototype implementation operates on flat designs, be can be readily adapted to hierarchical processing .).
For a “quilt” of four macros approximately 500um x 500um, the experimental scans finds 4211020 pattern elements, of which approximately 61258 are unique, a “cache hit rate” of more than 98%. Figure 6 shows how the “misses” (indicated by light dots) fall off as the scan proceeds from left to right and the cache
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generation of more general layouts exploiting the restricted range of L3GO layouts.
warms up.
6 CONCLUSION In this paper, we have reviewed how the process of converting layout designs into silicon has become more difficult and prone to variability with current and future semiconductor technologies. We have discussed several approaches for addressing these problems, leading up to the current growth of interest in Design For Manufacturability. We have argued that some of the techniques proposed for DFM, while plausible in principle, would require large amounts of computation or designer effort or both. We believe the Restrictive Design Rules approach provides a more tractable way to realize the goals of DFM including improved yield and quality of results while improving designer productivity by reducing sensitivity of designs to changing details of technology. We have defined and started to implement L3GO, a set of tools and a backend design flow, to test these conjectures about the use of RDRs.
Figure 6: Illustation of Pattern Caching
Another way to view the effect of pattern caching is measuring the local area fraction that would have to be processed to cover all of the cache misses. Figure 7 illustrates how this area fraction falls below 10% as the macro is scanned left to right, which should relate to reduced execution time through pattern caching.
7 ACKNOWLEDGMENTS We want to thank the people in IBM that collaborating on the L3GO project: Rama Singh, Jin-Fuw Lee, Uli Finkler, Pieter Woeltgens, Giovanni Fiorenza, Stas Polonsky and Mary Wisniewski in the Research Division; Nak Seong, Lars Liebmann, Jim Culp, John Cohn, Bill Dewey and Leon Stok in the IBM Microelectronics Division; Nathan Kitchen and Puneet Gupta of the University of California (Berkeley and San Diego). Figure 7: Pattern Caching Miss Area Fraction
In addition to the “forward flow” mechanisms described above, we have started experiments with through-process simulation and quality of results computation.
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For the future, we plan to move this prototype implementation code into a production-ready form and use it in an actual design. Beyond that, we anticipate future work investigating how the QOR results can be used for automatic optimization of the Elaboration rules, and automatic
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[3] T. Tugbawa, T. Park, D. Boning, T. Pan, P. Li, S. Hymes, T. Brown, and L. Camilletti, "Modeling of Pattern Dependencies for MultiLevel Copper Chemical Mechanical Polishing Processes, " CMP Symposium, MRS Spring Meeting, April 2001. [4] C. W. Gwyn, P. J. Silverman, "EUVL: transition from research to commercialization", Proc. SPIE Vol. 5130, p. 990-1004, (2003) [5] J. Mulkens, D. Flagello, B.Streefkerk,
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