Basic Science and Challenges in Process Simulation

Advances in Solid State Physics 38, 565−582 (1999) ()

Basic Science and Challenges in Process Simulation J. Da
browski,a H.-J. Mussig,a M. Duane,b S. T. Dunhamc , R. Goossensd , e and H.-H. Vuong a Institute

for Semiconductor Physics, Walter-Korsing-Strae 2, D-15230 Frankfurt (Oder), Germany b Advanced Micro Devices, Inc., Austin, Texas, USA c Electrical and Computer Engineering Dept., Boston University, Boston, MA 02215, USA

d Semiconductor Research Corporation, National Semiconductor Corporation e Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07944, USA

Summary: We intend to turn the reader's attention towards CMOS

(Complementary Metal-Oxide-Semiconductor), the mainstream semiconductor technology. Within a decade, silicon CMOS devices will be 200 atoms long and 50 atoms deep. Of 50 billion devices on a chip only 64 may fail. This calls for extreme control of atomistic processes. We review research topics in basic materials science which are likely to match the needs of CMOS. It is noted that a hierarchy of models which adopt methods ranging from quantum mechanics through classical and Monte Carlo schemes to easily solvable continuum equations must be constructed.

1 Introduction Atomic-scale studies of solid state systems mark major achievements of materials science. The mainstream microchip technology, Complementary MetalOxide-Semiconductor (CMOS), may also prot from them. Stimulated by CMOS miniaturization (Fig. 1), atomistic research and modeling can enhance competitiveness of production by testing technological ideas on fundamental level. A technologist often nds himself at a crossroad. Physical insight can guide one in the choice of direction to head, helping in early development phases. The same insight positions a scientist to supply ecient simulation models. This can be benecial in failure and sensitivity analysis within the existing technologies. Starting from an overview of CMOS, we discuss the simulation environment, TCAD tools, crystal growth, wafer processing, implantation, diusion, oxides, silicides, back end processes, gettering, and prospective metrologies and theories. This summarizes the 182nd Heraeus-Seminar \International Workshop on Challenges in Predictive Process Simulation", ChiPPS'97 1, 2], which was primarily focused on diusion-related problems viewed from the perspective of the whole fabrication process. These issues are posted for ranking on the Internet 2].

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Figure 1 Miniaturization drives technology into the atomic regime. In this STM

image of the clean Si(001), atomic details as dimer rows, defects, and monatomic steps are clearly visible. The length of the scanned area is 0.1 m. Within one decade, this will be the minimum feature size of state-of-the-art CMOS devices.

2 MOS technology The workhorse of MOS technology is the Field Eect Transistor (MOSFET) (Fig. 2). Basically, it is a switch controlled by the gate potential. MOSFETs are named after the type of carriers which ow between the source (S) and the drain (D): nMOSFETs are built on p-doped material, with n+ -doped source and drain (S/D), while pMOSFETs are built on n-doped substrates, with p+ -doped S/D. Circuits must be faster, cost less per bit, use less power. They are cheaper with interconnects on chip. Hence miniaturization 4]: shorter channels, thinner oxides, shallower junctions. Gate oxide thickness tox, now 8 nm, will be 3 nm by 2001, with roughness approaching the atomic step height 3]. Estimates from 1997 indicated that tox can be scaled down to 2 nm 5] in the same year a 0.06 m MOSFET with tox of only 1.2 nm (12  A) was demonstrated 6]. Such transistors work fast but have high standby power losses due to tunneling through the oxide. Maintaining an increasing performance of sub- m MOSFETs may be expensive 7]. Also costs of production lines escalate: a current generation \fab" (factory) costs around a billion dollars. Only a fraction of the revenue may thus come from cutting-edge technologies (today 0.25 m linewidth, or the gate oxide length, which somewhat exceeds the channel length). Even 95% of the products shipped in 1997 by a prospering microprocessor company may have been made with \old" 0.5 and 0.8 processes. Indeed, though tomorrow has its challenges, innovations which make yesterday's technologies cheaper may be welcome today. A typical integrated circuit needs several hundred fabrication steps which apply deposition, lithography, oxidation, implantation, etching, polishing. The wafer is structured by local doping and isolation. Then gate oxides are grown and covered by gate polysilicon, contacts are made, interconnects are added. It remains to break the wafer into chips and seal them for protection. The steps needed to make the devices are named Front End Of the Line (FEOL) processes, while the steps needed to wire them are dubbed Back End Of the Line (BEOL)

Basic Science and Challenges in Process Simulation source

gate

inversion channel

3 drain

gate oxide

Si substrate

Figure 2 A schematic cross-section of a MOSFET 8]. Black areas on the sides

mark the isolation oxide (\eld oxide" or FOX). Triangular terminations of the FOX symbolize \bird's beaks", side-eects of LOCOS oxidation. Also in black is shown the gate spacer (SiO2 or Si3 N4 ) which encompasses the gate. The gate is a heavily doped polySi strip the other electrodes, source (S) and drain (D), are also highly doped. The substrate between S and D is doped oppositely to S/D. A gate potential greater than the threshold voltage, VT , opens a conducting \channel" between S and D. The electrodes are contacted by silicide (not shown).

Most of the process steps are in BEOL and they are the primary yield-limiters. But the road from physics to technology is shorter in FEOL. Inplanted dopant atoms are activated into substitutional sites by annealing. Standard dopants are B, P, and As new designs may employ In and Sb. Implants are shot through a protective SiO2 layer, sometimes covered by Si3 N4 . This may reduce channeling. To make shallower proles, B is often implanted as BF2 . CMOS combines nMOS and pMOS on the same wafer, usually pre-doped with B. The n-type wells (\tubs") for pMOS are implanted. Low-energy implants are then used for junctions and adjustments of channel proles. Gates can be deposited already doped, but they are usually implanted because device parameters are optimal when the gate and the channel have the same work function. The active areas are isolated by thermal oxidation of the pad oxide in Ocontaining gas. This LOCal Oxidation of Silicon (LOCOS) scheme 7] produces \bird beaks" (Fig. 2), so Shallow Trench Isolation (STI), which adds etch and deposition steps, may be needed in the future 10]. High-quality gate oxides are grown by high-temperature dry oxidation after striping the remaining pad oxide. After gate deposition and etch, contacts are made by self-aligned silicidation (salicidation) with Ti, in the future maybe Co. The metal attacks Si, but not SiO2 . The unreacted lm is removed, leaving well-dened contacts. The circuit is wired with planes of horizontal Al lines (\metallization levels") joined by vertical W \plugs". The future material is Cu 11]. Glasses (BPSG) are used for isolation, but their high dielectric constants delay the propagation of electric signals (parasitic capacitances, RC) and facilitates cross-talk between wires. New dielectrics will be needed and even Cu may have to be replaced.

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Figure 3 Left: Price per bit (circles, right ordinate) and cost per lot of 25 wafers

(squares, left ordinate) for DRAM generations versus the year of introduction 9]. Right: Product realization. Logic design translates the product specications into gates, registers, etc., assuming that parameters as clock speed are within ranges guaranteed by the physical layout. The latter outlines the physical structure (transistor placement, linewidths) which should fulll these requests. The process design casts the physical design targets onto process conditions.

3 Simulation Environment and TCAD tools Modeling of technological processes is increasingly attractive to the industry. First, it can save time. Second, it can reduce processing costs of silicon wafers. New generations are developed by scaling the existing ones problems are solved by matrix experiments. A technology is often tuned during production, by varying the process for some wafer lots (\split lots"). If the change is too drastic, wafers can be lost. By the year 2010, a lot of 50 wafers will cost nearly a million dollars (Fig. 3) and this way may prove too expensive or too slow. A semiconductor fab acts as a computer which may need a few months to run a batch (Fig. 3). Simulation can give results within a few days, so virtual experiments would be optimal. But this may work only if all design tools are predictive. This may be dicult (Tab. 1), but any progress is certainly welcome. Simulation for CMOS includes equipment modeling (crystal growth, CVD, rapid thermal and plasma processing), process modeling (diusion, implantation, oxidation, epitaxy, etching), and device modeling (physics, design, interaction of devices, interconnects, degradation, burn-out). These activities need an extensive database coupled to physically sound models. Process modeling may be assisted by atomistic theoretical tools employing quantum mechanics and molecular dynamics. Diusion or interfacial physics appear particularly suited for them. But in many cases direct measurements or empirical models will dom-

Basic Science and Challenges in Process Simulation Application Accuracy needed predictive TCAD very high advanced process control high process centering high inverse modeling high early exploration medium failure analysis medium learning and insight low

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Comments probably an elusive goal: : : provide macro models optimize for a mature product use to extract coecients less splits in processing of lots test probable causes high return on investment

Table 1 TCAD applications. The top three items get most attention, while much useful work is done in the bottom three classes. See also 3, 12, 13, 15].

inate. As examples, one may quote reaction rates and sticking coecients. The key atomistic issues in modeling for crystal growth and wafer processing are about defects and homogeneity. The main challenges in the front end are related to dopant proles in shallow junctions and short channels, an excellent playground for atomistic physics. It is intriguing that combination of models (e.g., for high-concentration regime and for defect-mediated diusion) remains problematic. Promising for atomic-scale physics in back end are surface processes during deposition and etching. The simulation methods exist, but key parameters are dicult to get and little physics is built into BEOL models. Technology Computer Aided Design (TCAD) can be used on many problems (Tab. 1). It must be ecient physics is just one of the means to achieve this. In early development phases, simulation gives insight into technology directions and elucidates interactions between optional solutions. A high return on investment can be obtained by getting approximate but early answers to the right questions. The earlier a problem is caught, the easier it is to correct. In the late development phase, TCAD is useful for process optimization, sensitivity analysis, and diagnosis 16]. Such quantitative applications are more demanding (Tab. 1). But even insight alone helps. E.g, understanding of existing processes enables predictions of process reliability and of process-induced variations. A great potential for modeling is in new materials. There is a lot of data on existing technologies, so extrapolations usually work. The big questions come with new materials, as Cu instead of Al, or replacements for SiO2 . Another key area where basic physics may help is interfaces. Any insight that physics can provide early in the development of new technologies can have a large impact. Practical TCAD uses computationally cheap, continuum models. This traditional method is reaching limits in defect-mediated prole evolution, chemical and physical reaction modeling, predictive equipment and topography modeling, and practical non-equilibrium transport. It is unclear when it will break down, but technology advances fast and this may happen before we realize it. Discussions between technologists and physicists are needed to smoothen the transition

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Specialization process/device fab equipment electrical tests analytical metrology simulation

Knowledge needed for TCAD calibration must know complete process ow, process/device physics To in implantation aects diusion local To in RTA electrical versus optical oxide thickness SIMS knock-on SRP probe pressure uncertainty in poly length and oxide thickness model limitations grid dependence

Table 2 Knowledge needed for TCAD calibration. The wafer temperature To

during implantation can aect the point defect generation and thereby the diffusion later 17]. To during RTA is dicult to measure 18], but 1 volt variation in a 220 V AC line changed To by 6o 19]. The ion beam energy can aect SIMS proles 20]. SRP depends on probe pressure 21]. Poly linewidth and oxide thickness are dicult to measure a 1% change aects the saturation current by 1%.

to discrete models. Atomistic physics is not easily integrable into the existing tools and will have to be rst translated to continuum models. Consider two examples. First, electrical characteristic of tiny transistors are aected by two- and three-dimensional (2D and 3D) structural details 14]. The 3D narrow-channel eect becomes comparable to the 2D short-channel eect. Since 2D dopant proles cannot be properly measured (section 10), diusion models which would reliably extrapolate 1D data are needed. When adopted to the continuum formalism, they can be used in modern simulators which allow to dene equations. Second, applications beyond 0.1 m will need discrete description of defects and dopants, with stochastic analysis of uctuations 4]. Optimally, TCAD should yield correct electrical characteristics given any process ow. But the models have numerous, often obscure parameters. They must be calibrated by ts to experiments not always doable under conditions close to those in the production. The models may also employ wrong assumptions or contain no physics. The predicivity depends thus on the choice of test structures, interpretation of the experiment, and intuition and experience of the user. Calibration is also dicult because typically a whole process is simulated. If the threshold voltage from the subsequent device analysis does not match the measured value, one must check assumptions in the process and device simulations, the test structure layout, and electrical measurements. Knowledge in many areas is required (Tab. 2). Physics can help by systematizing this knowledge. Models with physically meaningful parameters and with known windows for their variation are thus favored. Calibration strategies are important. A hierarchy of models from atomistic to continuum is needed. Some basic models, e.g., for segregation, must be re-examined in light of advances in metrology, physical understanding, and process conditions over the last 20 years. To avoid confusion, implementation of the models must be backward compatible their physical interpretation would assists users and vendors, adding value to TCAD tools.

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4 Models for crystal growth and wafer processing Crystal growers must produce Si base material with homogeneous distribution of O and dopants. Modeling can be used to predict the transport of the impurities in the melt and their incorporation into the crystal. Given increasing crystal diameters (a 300 mm technology fab is being built in Dresden, Germany), costs of development will increase and simulation will gain importance. But melt convection is turbulent and three dimensional, and thus dicult to handle. Epitaxy modeling should consider heat transfer by convection, conduction, and radiation. 3D gas convection and reaction of a gas mixture (SiHCl3 , H2 ) with the surface must be included. Accuracy of heat transfer and convection models needs improvement 22]. Models for reaction kinetics are in the development phase. Grown-in defects (octahedral voids) in as-grown Si reduce the yield (the percentage of working chips) and must be contained. Their distributions will have to be simulated by taking into account dynamics of point defect (self-interstitials, vacancies, foreign atoms) and the formation of extended defects 23]. Finally, modeling tools for O precipitation during thermal treatments, including inuence of impurities (e.g., boron), gettering of metals (section 9), stress in Si wafers (including thermal stress), defects and homogeneity in epitaxy, and molecular simulation for cleaning and polishing of wafers must be developed.

5 Models for ion implantation A major challenge is the formation of shallow, heavily doped junctions 3]. Junction depths continueously decrease: in the 0.1 m technology (year 2007), they will be 150 to 450  A (15 to 45 nm). The diculty lies in channeling eects and in the diusion out of the implanted region during subsequent processing. For reviews on implantation and its relation to diusion, see 33] and 31]. The modeling provides initial conditions for simulation of dopant diusion. Standard TCAD yields the spatial distribution of dopants by a sophisticated extrapolation of SIMS data. This may run out of steam for near-0.1 m structures. The ions create Si interstitials (SiI ) and vacancies (SiV ). Since dopants diuse by point-defect mediated mechanisms (Tab. 3), the distribution of SiI , SiV , and their clusters (seeds of extended defects) is needed for further modeling of diffusion. Appropriate atomistic simulators have been presented 24, 25, 26], but more data is needed on the intermediate cluster congurations and on thermal eects on defect migration and recombination 25, 27]. Though TCAD models can account for channeling and defect-mediated diusion (section 6.1), they are not good enough for heavily doped junctions shallower than 100 nm. The basic theoretical methods which can help to obtain the missing data are: 1. Quantum mechanics. The most exact but the most CPU-intensive hence only small systems can be examined. Static calculations dominate, dynamic

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species B P As In Sb

type

atomic importance research diusivity diusion mass importance research diusivity vehicle acceptor 5 high mature high SiI donor 15 high advanced high SiI donor 33 high advanced medium SiV , SiI acceptor 49 medium evolving low SiI , SiV donor 51 medium evolving low SiV

Table 3 Shallow dopants. Note the absence of fast-diusing Al it would deteriorate the dopant prole of a submicrometer device. Ga diuses fast in SiO2 28].

simulations are needed. Can validate/calibrate higher-level methods 29]. 2. Classical molecular dynamics (MD). Successful for low-energy impacts 24, 26]. Problems with computational resources and physical intuition. Hits its limits at amorphization and defect evolution for t > 1 ns. 3. Binary collisions (BC). The leading atomistic approach 25, 30, 31, 32]. Monte-Carlo based. Successful for ballistic processes, yields ion range proles. Better coupling to MD and experiment will improve modeling of damage. A hierarchy of models ranging from the lowest (ab initio) to the highest level (which may adopt Monte Carlo for self-annealing, diusion, and clustering of defects 25]), with consistent and transferable parameters, would greatly enhance the predictability. Self-annihilation and thermal eects (dependence of implantation and diusion on temperature 17]) could be then properly included. Mostly simulated are the species of Tab. 3. It would be useful to learn more how species like N and Si aect channeling and diusion. Si can be implanted to amorphize the crystal in order to reduce channeling and speed up silicidation in narrow stripes. N implants help to control diusion. These are important examples where simulation plays a minor role. Simulation tends to be a \step behind" technology the issue is how to get \in-step" with technology. Briey, in order to model shallow junctions, TCAD must include interaction between implantation and diusion. This illustrates the key issue in FEOL: the main challenge is in making modules interact, not in improving each module.

6 Models for dopant diusion Research on diusion in Si has provided many detailed data, including atomistic models and the inuence of various process conditions 34]. But dopant proles for new designs can hardly be predicted without short loop experiments for calibration. \Ramping" (increasing or decreasing of the wafer temperature, at around 100 K/s) is an extra complication. Dopants may diuse during ramping already above 600oC. The local temperature is dicult to measure18, 19]. The traditional approach to diusion is to use coupled dierential equations

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34]. Dynamics of diusion vehicles (SiI , SiV 35, 36, 37], Tab. 3) is limited to equilibrium. Recent tools provide non-equilibrium dynamics of point defects and allow to account for inhomogeneous distribution of extended defects which are sources/sinks of SiI . The key technical details to be worked out are: 1. Diusion parameters for SiI and SiV : formation energies, migration barriers, pre-exponentials, dependence on the Fermi-level, chemical composition, and strain. Experimental 27, 38] and theoretical (ab initio 39], tight-binding 29]) data exist, but are often contradictory. Diusivities of SiI from metal diusion and from the depth dependence of TED (section 6.1) dier by orders of magnitude. Trapping of SiI has been suggested as an explanation 40]. 2. 3D solvers and statistical analysis for standard TCAD. Beyond 0.1 m, statistics of defect and dopant distribution will play a role 4]. 3. Methods to measure 2D and 3D proles with sucient accuracy (section 10). A number of basic problems remain unsolved. The reaction paths of defectmediated diusion are still doubtful. This includes diusion in heavily doped materials. Transient diusion eects need a complete description. Boundary conditions (notably, at SiO2 /Si(001) interfaces) must be properly dened. Diusion in polySi is dicult to handle. These (and other) issues are addressed below.

6.1 Diusion in Si bulk

Dopant diusion is commonly described by pair models: dopants and point defects are assumed to form mobile pairs. They can explain why dopants diuse with a lower activation energy than native point defects (SiI , SiV ). But the errors resulting from the simplication of interactions have not been estimated. It is dicult to develop a consistent analysis of experimental data without a consistent knowledge about the paths by which point defects mediate the diusion. Not only the form of diusion equations but also such parameters as cross sections for defect-dopant reactions depend on the reaction path. Advanced atomistic theories for the interstitial 36, 41] and vacancy mediated 36, 42, 43] mechanisms have been attempted they must be veried and expanded. Dopant diusion is enhanced at concentrations above 2
1020 cm;3 . To sort out the right explanation, quantum-mechanically veried potentials for defectdopant interactions 42] are needed. Models including rigorously the kinetics of extended defects or SiI injection at SiO2 /Si are missing for such concentrations. In practice, only atoms in isolated substitutional sites act as shallow dopants. One must thus consider their activation, deactivation (formation of atomic-size clusters or/and precipitation of a silicide), and diusion. Useful TCAD models exist, but they have many limitations and a lot of room for research remains. Essential to the fabrication of shallow junctions is that diusion is aected by excess intrinsic point defects. Depending on the migration mechanism (Tab. 3), such transient eects may enhance or retard diusion. For example, Si interstitials enhance diusion of B and P and retard diusion of Sb.

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The classic Transient Enhanced Diusion (TED) is caused by SiI produced in implantation, stored in End Of Range (EOR) defects after amorphizing and in f113g defects after non-amorphizing implants, and re-emitted. Its main features are described by the theory of cluster evaporation 27], but the initial conditions are unclear (section 5). Description of vertical and lateral TED extensions is not reliable, particularily due to uncertainties in parameters for SiI dynamics. TED at low concentrations (near to steady-state conditions) is well understood, but its modeling at high concentrations (far from steady-state) is problematic. Models built on the basis of a few easy to measure parameters are needed. TED is suppressed by substitutional C 27] rst predictive models are available. The pressing question is the alleged enhancement of junction leakage by C. Some other impurities, notably F, have also been reported to aect TED 44]. An oxidizing interface ejects SiI . The oxidation enhanced diusion (OED 34]) is under control. Cl in the oxidizing ambient signicantly reduces the number of ejected SiI , probably due to creation of SiV when the silicon is etched. Another source of SiI is deactivation of As 45]. Activation is eciently done by Rapid Thermal Annealing (RTA) 46]: infrared lamps briey heat the wafer to a high temperature. The concentration of the activated As exceeds solubility limits at temperatures at which As is mobile. In consequence, As atoms tend to cluster and precipitate. Even 50% of dopants can be clustered. Small As clusters contain SiV , and their formation leads to emission of SiI . This recent discovery 45] calls for more studies. The mechanism of the SiI emission is not clear. SiI may be ejected from the clusters, or the clusters may consume SiV while SiI are produced in the volume in Frenkel pairs. Other dopants, notably B, cluster as well. B clusters with SiI and is deactivated the complexes act as SiI storage bins. Modeling of TED, activation, and deactivation needs data on the structure (ratios of point defects to clustered impurities) and energetics (cluster sizes, emission/capture rates) of stable and intermediate clusters. Even groups of two dopant atoms 41] are important. On the other extreme, dopant interactions with extended defects must be studied. The case of polySi is addressed in 6.3. Also silicidation injects point defects (SiV in the case of Ti and Co). There are indications that this is not a major issue. When SIMS artifacts are absent, both Ti and Co silicidation are measured 47] to inject SiV between 0.5 and 1 times the equilibrium SiV concentration at temperatures between 800 and 890oC. Silicidation should thus reduce diusivities of B and P by a factor of two or less. Finally, the concentration of SiV is enhanced by nitridation 48]. The mechanism is unclear: it may be a direct insertion at the interface, or enhanced SiV formation in Si volume due to the strain induced by the Si3 N4 lm.

6.2 Boundary conditions

A dopant prole is determined by the initial distribution of dopants and point defects (section 5) and by the physical borders (the bulk and an interface).

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The bulk is a reservoir of point defects. Transient processes usually dump point defects into it, but the bulk can be a source of vacancies for As deactivation. Shallower junctions imply ne proling of dopants closer and closer to the SiO2 /Si(001) interface, e.g., as close as 50 nm 49]. Three classes of boundary processes aect the dopant prole under the oxide. Dopant atoms either segregate to the oxide (B) or are ejected from it (P, As). Dopant atoms segregate to the SiO2 /Si(001) interface. Interstitials and vacancies are annihilated at nonoxidizing interfaces and interstitials are ejected from oxidizing interfaces. Take P as an example. As the oxide grows into the silicon, it \shovels" P atoms, and P segregates to the interface at temperatures high enough to enable diusion (around 600oC). This P pile-up impacts the dependence of the threshold voltage VT on the gate length, adding to Reverse Short Channel eect 50]. The prole can change so much that VT obtained by standard TCAD can be o by 0.5 eV. Models for dopant proles close to SiO2 /Si(001) exist and work for present CMOS devices (e.g.,49]). But further detailed measurements and more comprehensive modeling are needed to give predictions for new designs. A simple but physically correct description of the interfacial processes and a reliable estimate of the physically allowed range of the model parameters would be of signicant help to designers. This includes segregation coecients and their dependence on temperature, ambient, dopant concentration, and oxide trap density. The electronic structure of segregated dopants aects the activation, the noise gure, and the gate leakage current. The segregated atoms are deactivated, which causes a dose loss. Even 50% of the implants may \disappear" 51]. The interface can collect more than 2
1014 dopant atoms per cm2 , nearly as many as there are interfacial lattice sites (7
1014 /cm2). The loss is enhanced when the annealing ambient contains O, needed to heal defects in SiO2 . An inert ambient may be critical at very high temperatures (above 1000oC), as during activation. Similarly large amounts of dopants may be lost to the pad oxide after implantation. The resulting increase of series resistance becomes a problem for channel lengths below 0.25 m. One might try to avoid this by implanting more dopants, but the atoms migrate in all directions and a higher dose means more diuse proles. Special capping layers and annealing schemes should thus be studied. The problem of dose loss in the context of silicidation is addressed in section 7. Ultrathin oxides are prone to B penetration from heavily doped gates (section 6.3). Oxides which contain N are much more resistant, and nitridized oxides are a promising technological candidate. Since N tends to accumulate at the SiO2 /Si interface, the inuence of N on the interfacial dopant atoms should be claried.

6.3 Other problems

Below, we address diusion of dopants in gate oxides and in polySi, precipitation of oxygen, stress eects on diusion in silicon, and diusion in SiGe. Stress may arise from eld oxidation, dierent thermal expansion coecients

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of layers (SiO2 , Si3 N4 ), lattice mist in SiGe heterostructures, and extended defects. The stress can be on the limit of dislocation formation, particularly during oxidation. While the inuence of stress on oxidant diusion and reaction in SiO2 are well assessed, its eect on diusion in Si is less studied 48]. Band-gap engineering by SiGe may become important in upcoming technologies. Quantitative models for the diusion of Si, Ge, and dopants in SiGe structures, and for the segregation to bulk Si, are scarce.52] There is a need to pinpoint the role of the composition and strain in the diusion mechanisms. Doping of polySi gates invokes important problems. First, gate oxides will be soon as thin as 3 nm (30  A) 3]. B can diuse through such a thin SiO2 . Atomistic models exist 53], but diusion of B in gate oxides is not well understood. Quantitative data on the dependence of the diusion on the B concentration and on the presence of F and other impurities is insucient and inconsistent. Modeling of F diusion in polySi gates and in gate oxides is in its infancy. Second, the doping must reach 1020 cm;3 , with uniformity better than 3% 3]. It is dicult to activate even 5
1019 cm;3 dopants. E.g., dielectric reow deactivates As and can increase the contact resistance by a factor of three 54]. Third, diusion models for polySi build on local homogenization. Poly thickness and grain sizes compare to gate lengths, so diusion via single boundaries must be included. This is needed to estimate the eect of dopant distribution on the oxide penetration. Reliable models for diusion and activation in polySi and for diusion in SiO2 should help to nd a trade-o between high thermal budgets for doping homogeneity and low thermal budgets to prevent B penetration. An area of potential interest is the interaction between impurities (such as C and dopants) and precipitation of O. O precipitates act as getters keeping the active regions clean from such \killer" impurities like Fe (sections 4 and 9).

7 Silicide and oxide lms The key silicide in CMOS is TiSi2 . Silicidation is done in an inert ambient (N2 ) at low temperatures, such as 600oC. This produces a defected, high-resistivity phase of TiSi2 , labeled C49. Annealing transforms it into the low resistivity phase, C54. The transformation is nucleation-controlled and slows down when the silicide strip is scaled. Alternative silicides, notably CoSi2 , are thus studied, mostly experimentally. Standard TCAD tools lack the database for Co processes. Silicidation is well studied 55], but its complexity hinders development of physically-based modules 56]. E.g., it is aected by dopant distribution, which must be computed in changing volumes of coexisting phases. Silicides are polycrystalline, with fast diusion paths along boundaries 57]. Diusion in the grains is usually anisotropic and may depend on stress. Segregation of dopants into the silicide depletes the silicon at the interface, increasing the contact resistance. Modeling should estimate VT changes due to the dose loss and to a possible

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counterdoping, obtain the eect of silicidation on S/D resistance, and suggest a process window for the lm thickness and the energy and dose of implantation. Silicidation impedes scaling. The interface roughness facilitates electrical punch-through and limits junction depths. Since S/D junctions are made before silicidation, also Si consumption in the Ti process limits their depths. A junction must be at least 100 nm deep to assure low leakage after silicidation. Continued use of silicidation will soon require raised S/D structures 58]. Atomistic studies might help to solve the problems related to the dose loss and to the interfacial roughness. But to be successfull, atomistic theories must decouple the involved physical eects from the complex silicide formation. Oxidation is troubled by oxide thickness (tox) variations and B penetration (section 6.3). Methods to simulate tox variations, susceptibility to B penetration, and concentrations and generation kinetics of defects in the oxide (including micropores) and at SiO2 /Si (including SiO2 /polySi) are needed. Dependence on temperature and chemistry of the oxidant (O2 , O2 +N2 , NO2 , NO) and of the annealing ambient (O2 +N2 , O2 +Ar, Ar) is of interest. Physical models for device reliability would be welcome. New dielectrics, as Si3 N4 , are a prospective eld. Models for gate oxidation are largely empirical the underlying physics is unclear. Corrections to the Deal-Grove model 59] work well for tox > 10 nm, but gate oxides are now thinner. As tox approaches the few-monolayer regime, atomistic schemes should be considered (section 10). Mechanism of inhomogeneous oxide growth (as for isolation) is controversial. Parameters governing elastic, viscous, viscoelastic or plastic deformation of the oxide, and describing the eects of stress on oxidant diusion and reaction await identication. Innovations like Rapid Thermal Oxidation 46] are not addressed in standard models.

8 Models for BEOL Complex physics and chemistry are typical in BEOL. Practical simulations often use nearly geometrical models with much calibration. Commonly simulated are deposition by sputtering, CVD, PECVD, plasma etching. The materials are SiO2 , TiN (diusion barrier, wetting layer, and etch stop), Al, Ti, and W 60]. The goal is mainly to test the viability of increasing the aspect ratio of interconnect features, e.g., lling of trenches and vias 61], and to explore the scaling limits of present processes 62]. As these limits are reached, new materials and processes are being introduced rapidly. This includes low dielectric constant (\low-k") dielectrics to reduce delay and cross-talk 63]. Another emerging material is Cu. IBM has just announced 11] the rst Cu technology (0.2 m). Plasma etching and deposition is treated with a limited set of chemical equations. Incoming uxes are well simulated by equipment models. Advancements include Monte Carlo simulation for angle and energy distributions. Beyond 100 nm, molecular dynamics will be needed for the surface/plasma interaction.

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The list of wishes for BEOL simulation includes 64]: 1. Decomposition paths, deposition rates: Cu, Ti, W, Al, polySi, WSi2 , TiSi2 . 2. Surface mechanisms (including surface diusion) in deposition and etching. 3. Plasma processing: radical/ion interaction in plasma and with surfaces. Cross sections for excitation, total and partial ionization, dissociation, attachment, dissociative attachment. CFx (x=1-3) interacting with Si and SiO2 , Cl etch of Al (including BCl2 cross section, Cl2 data exists), F interaction with Si. 4. Viscosity, thermal conductivity, diusivity: SiClx (x=2,3), SiHx Cl2 (x=1,2), SiHCl3 , SiH3 Cl, Cl+ , BCl+2 , CF+x (x=1-3), SF+x (x=1-6), WF+x (x=1-6). 5. Ar+ sputtering of Al, Cu(111), Ti. Energy, angle of sputtered atoms, and yield as a function of incoming ion energy and angle. Another challenge is Chemical Mechanical Polishing (CMP). CMP is widely used in BEOL (dielectric planarization, metal etch back) and FEOL (STI) 63].

9 Models for gettering of impurities The ultimate goal is here to improve the yield (the percentage of working chips). Simulation should pinpoint the steps most sensitive to contamination and suggest changes to reduce this sensitivity and widen the process window. This requires quantitative understanding of surface chemistry and gettering. Basic mechanisms are established, but there are many gaps in the details, such as surface and bulk segregation coecients under various process conditions. Good surface chemistry data exist for some contaminants, especially for Fe. The critical impurities are transition metals, mostly Fe, Cu, and Ni. Iron 65] is well-studied, ubiquitous, relatively fast diusing. It remains electrically active (interstitial) after fast cooling. FeB pairs 67] usually determine the carrier diusion length and lifetime, especially after processing. A single Fe atom segregated to the gate oxide can kill a 0.1 m-channel transistor! Another frequently studied metal, Au, is not troublesome and will not become so the foreseeable future. Progressively restrictive contamination thresholds call for new gettering methods 66]. Well-understood gettering driven by supersaturation (relaxation-type internal gettering by SiO2 precipitates) will loose importance as supersaturation is ever more dicult to achieve. Proximity gettering (segregation gettering close to the device by p=p+ epi or implanted layers) is very promising. Most processor structures use it (Intel: 100%). Quantitative calculations of proximity gettering require segregation coecients their values are often not well established.

10 Prospective metrologies and atomistic theories Diusion simulations are veried mostly by comparison of electrical measurements with device simulations. This assumes at least that the latter are adequate.

Basic Science and Challenges in Process Simulation

15

Below we benchmark methods which might supply direct two-dimensional (2D) data: location of the junction with accuracy better than 10 nm, and dopant and carrier proles with vertical and lateral spatial resolution of 10 nm or better. Metrology requirements have been recently re-examined in Ref. 77]. 2D proling is too tough for traditional methods. Though the conventional Spreading Resistance Probe (SRP) yields one-dimensional (1D) vertical proles for junction depths below 50 nm, the required lateral resolution cannot be even approached. SRP with a conducting Atomic Force Microscopy (AFM) probe and an ohmic back contact oers some improvements. Secondary Ion Mass Spectroscopy (SIMS) can yield excellent 1D proles, but also fails for 2D. New methods build on electron and scanning probe microscopies. Samples are cleaved and scanned. Since a unique relation between the electronic structure of the surface and the dopant prole in the substrate is needed, the common problem is that the sensitivity is hampered by diculties with surface preparation. Selective etching 68] uses the dependence of the etch rate on the doping level. The topography is measured by AFM 69], Transmission Electron Microscopy (TEM 70]), or Scanning Electron Microscopy (SEM 70]). Stereo SEM improves sensitivity and resolution. The main problems are reproducibility, calibration, and a strong rise of the etch rate at concentrations above 5
1019 cm;3 . Chemical staining 71] detects metal layers electroplated on silicon. The main problem is low sensitivity of electroplating to the substrate Fermi level. Scanning Tunneling Microscopy (STM 72]) detects the doping level through the dependence of the current on the depleted region in Si. The resolution is limited by the surface roughness and incomplete surface passivation. Scanning Capacitance Microscopy (SCM) detects tip-sample capacitance changes 73]. Tip preparation methods limit its resolution to around 20 nm. Scanning Kelvin Probe Microscopy (SKPM) measures changes in surface potential 74]. Spatial resolution, limited by the tip, is comparable to that in SCM. Surface preparation limits resolution in measurement of the potential. TCAD must know geometrical factors such as oxide thickness, tox , and gate length, l. Essential electrical parameters, like the saturation current Idsat , depend in the rst-order on tox and l. For 0.25 m gate lengths with 5 nm gate oxides, 1% accuracy for Idsat implies a measurement error of only 2.5 nm (25  A) for the poly length. Even more impressive is the condition for tox : 0.05 nm (0.5  A), much less than a monolayer. The desired control on Idsat is below 10% (3). Errors add up, so 1% from a single input data is a conservative requirement. STM can measure currents through ultrathin oxides 75]. This might be used to access local oxide thickness variations, interfacial states, defect states in the oxide, and to study hot-electron damage. A conducting AFM 76] may decouple the information about the oxide thickness and the interface roughness. The ultimate goal of atomistic simulations for TCAD is to yield data needed to write down simple time-dependent equations. Parameters in these equations

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should have a well-dened physical meaning, so that they can be measured with a minimum of interpretation bias. Another value comes from the paradox of simulation: in order to simulate something, one must understand it well, but in the process of understanding it, one may reduce the need for simulation 13]. Ab initio schemes 78] are nearly arbitrarily accurate. Their assumptions can be strictly controlled. But they are CPU-intensive, working best for systems with less than thousand atoms. Even assisted by high performance computing and new algorithms, they will be most helpful in sorting out the right physics or validating and calibrating higher-level methods. Computation for TCAD seems practical only in such cases as for atomic congurations or binding energies. Similar limitations apply to quantum-mechanical methods which use model potentials derived ab initio or from experiment. But much larger systems can be treated and molecular dynamics becomes much cheaper 79]. Disorder, complex interfaces, or dislocations become accessible with less eort, though with less condence. These techniques are an indispensable extension of ab initio tools. Classical methods are even faster. They introduce approximate interatomic interactions: Stillinger-Weber 80] or Terso 81] potentials, or \valence forces" 82]. But direct links to the electronic structure are lost. Unphysical eects can dominate the outcome. Examples of failures are known particularily for structures in which dangling bonds or unusually coordinated atoms play a role 29, 83]. Critical congurations must be cross-checked against lower-level methods. Strictly atomistic methods are limited by the period of atomic vibrations, 10;13 s: there are 13 decades from the atomic to the \technological" time scale! Monte Carlo schemes get around this by describing atomic dynamics through energy barriers and hopping frequencies. The time scale is thus increased to the hopping time, by two to six decades, and the density of mobile species drops from the atom density (1023/cm3 ) to the point defect density (1010 -1020/cm3 ). Quantum-mechanical methods may have an impact through calculations for (1) dopant diusion, notably transient eects, (2) dopants near interfaces, in particular pileup and dose loss, (3) surface chemistry during metalization, (4) chemical reactions during etching. They must be linked to higher-level methods (classical potentials, Monte Carlo, continuum equations) in virtually all cases.

11 Conclusions and Acknowledgements We conclude noting that as microchip technologies enter the ultrasubmicron era, physical understanding gains importance. This calls for improved process simulation supported by atomistic studies. To secure this support, as physical insight and as input data, links between technologists and scientists must grow stronger. We are indebted to A. Agarwal, S. Biesemans, A. Bourenkov, L. Colombo, E. Dornberger, M. Duane, R. W. Dutton, H.-J. Gossmann, E. Kaxiras, E. Langer, J. Lorenz, T. Ma, H. Marquardt, M. Meyyappan, A. Ourmazd, S. T. Pantelides,

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P. Pichler, J. M. Poate, M. Posselt, H. Rucker, H.-H. Vuong, E. R. Weber, and E. T. Yu for their help in organizing the work, sorting out and ranking the essential issues, and for reviewing subsequent versions of the manuscript.

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