Bebop to the Boolean Boogie Third Edition

Bebop t o t h e Boolean Boogie A n Unconventional Guide t o Electronics

Third Edition

Clive "Max" Maxfield

AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO ELSEVIER

Newnes is an imprint of Elsevier

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Contents

ABOUT THE AUTHOR

xvii

FOREWORD

xix

ABOUT THIS BOOK

xxi

ACKNOWLEDGMENTS

xxv

SECTION 1 •

Fundamentals

CHAPTER 1

A n a l o g V e r s u s Digital

3

It Was a Dark and Stormy Night

3

Analog Versus Digital Views of the World

4

Multi-Value Digital Systems

5

Experiments with Bricks

6

CHAPTER 2

CHAPTER 3

CHAPTER 4

A t o m s , Molecules, a n d Crystals

11

Protons, Neutrons, and Electrons

11

Quantum Levels and Electron Shells

13

Making Molecules

13

Crystals and Other Structures

15

Conductors, Insulators, a n d O t h e r Stuff

17

Conductors and Insulators

17

Voltage, Current, and Resistance

18

Resistance and Resistors

19

Capacitance and Capacitors

21

Inductance and Inductors

23

Memristance and Memristors

28

Impedance and Reactance

28

Admittance, Conductance, and Susceptance

29

Unit Qualifiers

30

Semiconductors ( D i o d e s a n d Transistors)

33

Herding Wild Electrons

33

The Electromechanical Relay

33

The First Vacuum Tubes

35

Semiconductors

36

Semiconductor Diodes

37

Bipolar Junction Transistors (BJTs)

39

Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs)

CHAPTER 5

CHAPTER 6

41

The Transistor as a Switch

43

Gallium Arsenide Semiconductors

44

Light-Emitting Diodes [LEDs]

45

Organic LEDs (OLEDs)

46

Active Versus Passive and Electric Versus Electronic

47

P r i m i t i v e Logic Functions

49

Switch Representations of AND and OR Functions

49

FALSE and TRUE Versus OPEN and CLOSED

50

BUF and NOT Functions

51

"Connect the NOTs"

52

AND, OR, and XOR Functions

52

NAND, NOR, and XNOR Functions

53

Not a Lot

55

Functions Versus Gates

56

Using Transistors t o Build Logic G a t e s

57

NMOS, PMOS, and CMOS

57

Using Os and Is Instead of Fs and Ts

57

NOT and BUF Gates

58

NAND and AND Gates

60

NOR and OR Gates

61

XNOR and XOR Gates

62

XNOR and XOR Gates: Pass-Transistor

CHAPTER 7

Implementations

63

Pass-Transistor Logic

65

Alternative Number Systems

67

Fingers, Toes, and Pebbles

67

Bones with Notches

67

Tally Sticks: The Hidden Dangers

68

The Abacus

69

Roman Numerals

69

Decimal (Base-10)

70

Duo-Decimal (Base-12)

71

Sexagesimal (Base-60)

73

The Concepts of Zero and Negative Numbers

74

Vigesimal (Base-20)

76

Contents

Jobs Abound for Time-Travelers

CHAPTER 8

CHAPTER 9

76

Quinary (Base Five)

77

Binary (Base-2)

78

Octal (Base-8) and Hexadecimal (Base-16)

80

Way Back in the Mists of Time

82

Representing Numbers Using Powers

82

Lucky and Unlucky Numbers

84

Tertiary Logic

85

Binary Arithmetic

87

Before We Start

87

Unsigned Binary Numbers

87

Adding Unsigned Binary Numbers

88

Nines' and Ten's Complements

89

Subtracting Unsigned Binary Numbers

91

Sign-Magnitude Binary Numbers

93

Signed Binary Numbers

94

Adding Signed Binary Numbers

95

Subtracting Signed Binary Numbers

96

Binary Multiplication

97

Binary Division

98

Boolean Algebra

99

Cabbages, Parrots, and Buckets of Burning Oil

99

Primitive Logic Functions

100

Combining a Single Variable with Logic О or Logic 1

102

The Idempotent Rules

102

The Complementary Rules

102

The Involution Rule

103

The Commutative Rules

104

The Associative Rules

104

Precedence of Operators

105

The First Distributive Rule

105

The Second Distributive Rule

105

The Simplification Rules

106

DeMorgan Transformations

106

Minterms and Maxterms

112

Sum-of-Products and Product-of-Sums

112

Canonical Forms

114

An Interesting Conundrum

114

Contents

CHAPTER l O

C H A P T E R 11

C H A P T E R 12

Karnaugh Maps

117

The Tree of Porphyry

117

John Venn and his Venn Diagrams

117

Allan Marquand and Lewis Carroll

117

Maurice Karnaugh and Karnaugh Maps

118

Minimization Using Karnaugh Maps

119

Grouping Minterms

120

Incompletely Specified Functions

122

Populating Maps Using Os Versus Is

123

Slightly M o r e Complex Functions

125

First Gather a Bucket of Logic Gates

125

Scalar Versus Vector Notation

125

Equality Comparators

126

Multiplexers

127

Decoders

129

Tri-State Functions

130

Combinational Versus Sequential Functions

132

RS Latch (NOR Implementation)

132

RS Latch (NAND Implementation)

137

D-Туре Latches

138

D-Туре Flip-flops

139

Implementing a D-Туре Flip-flop

142

JK and T Flip-flops

143

Shift Registers

144

Counters

146

Setup and Hold Times

148

Brick by Brick

149

S t a t e Machines

151

"Is That a Gizmo in Your Pocket, O r . . . "

151

State Diagrams

152

State Tables

153

State Machines

154

State Assignment

155

Don't Care States, Unused States, and Latch-Up Conditions.... 158 C H A P T E R 13

Analog-to-Digital and Vice Versa

161

Setting the Scene

161

Analog-to-Digital

162

Digital-to-Analog

164

DSP Versus DSP

165

Analog Signal Processing [ASP]

165

Digital Signal Processing [DSP]

166

DSP Examples

167

What Implements the Digital Signal Processing?

167

SECTION 2 • Components and Processes CHAPTER 14

C H A P T E R 15

I n t e g r a t e d Circuits (ICs)

173

The First Integrated Circuits

173

An Overview of the Fabrication Process

175

A Slightly More Detailed Look at the Fabrication Process

176

An Introduction to the Packaging Process

181

Integrated Circuits Versus Discrete Components

185

Different Types of ICs

186

TTL, ECL, and CMOS

187

Core Supply Voltages

187

Equivalent Gates

188

Device Geometries

188

What Comes After Optical Lithography?

190

How Many Transistors?

192

Moore's Law

192

M e m o r y ICs

193

RAMs and ROMs

193

Cells, Words, and Arrays

195

Addressing a Word in Memory

196

Kilo, Mega, Giga, Tera, Etc

196

Bits and Bytes

197

ROM Control Decoding

197

RAM with Separate Data In and Data Out Busses

199

RAM with Single Bidirectional Bus

200

Increasing Width and Depth

201

Mask-Programmed ROMs

202

PROMs

203

EPROMs

205

EEPROMs/E E PROMs

207

FLASH

207

SRAMs and DRAMs SDRAMs

208 208

DDR, DDR2, DDR3, QDR, RAMBUS, Etc

210

SIMMs, DIMMs, and RIMMs

210

CHAPTER 16

C H A P T E R 17

CHAPTER 18

ECC Memory

211

MRAMs

211

nvRAMs, FRAMs, PRAMs, RRAMs, CBRAMs, SONOS, Etc

211

P r o g r a m m a b l e ICs

213

A Simple Programmable Function

213

Fusible-Link Technologies

214

Antifuse Technologies

215

EPROM, E 2 PROM, FLASH, and SRAM Technologies

217

The First Programmable Logic Devices (PLDs)

217

PROMs

218

PLAs

221

PALsandGALs

223

Additional Programmable Options

224

Introducing CPLDs

224

Introducing FPGAs

227

Alternative FPGA Architectures

229

Alternative FPGA Configuration Technologies

232

Mixed-Signal FPGAs, CSSPs, and

233

Summary

233

Application-Specific I n t e g r a t e d Circuits (ASICs)

235

Introducing ASICs

235

Full Custom Devices

236

Gate Arrays

236

High-Level View of the Gate Array Design Flow

238

Standard Cell Devices

240

High-Level View of the Standard Cell Design Flow

241

I T Versus 6 T SRAM

241

Structured ASICs

242

Input/Output (I/O) Cells and Pads

245

ASICs Versus ASSPs

246

Who Are All the Players?

246

Summary

248

P r i n t e d Circuit Boards (PCBs)

251

Not Much Fun

251

The First Circuit Boards

251

PCBs and PWBs

252

RoHS and Lead-Free Solder

252

Subtractive Processes

253

Additive Processes

255

Single-Sided Boards

257

Lead Through-Hole (LTH)

259

Wave Soldering

259

Surface Mount Technology (SMT)

260

Double-Sided Boards

262

Holes Versus Vias

264

Multilayer Boards

265

Through-Hole, Blind, and Buried Vias

266

Power and Ground Planes

267

High Density Interconnect (HDI) and Microvia Technologies... 2 7 0

CHAPTER 19

CHAPTER 2 0

Backplanesand Motherboards

271

Conductive Ink Technology

272

Chip-on-Board (COB)

273

Flexible Printed Circuits (FPCs)

274

Hybrids

277

The Offspring Resulting from Crossbreeding

277

Hybrid Substrates

277

The Thick-Film Process

278

Creating Tracks

279

Creating Resistors

280

Laser Trimming

281

Creating Capacitors and Inductors

282

Double-sided Thick-Film Hybrids

283

Subtractive Thick-Film Technology

283

The Thin-Film Process

283

Laser Trimming

285

The Assembly Process

286

Attaching the Die

286

Wire Bonds

287

Tape-Automated Bonding

288

Flipped-Chip Techniques

289

Advantages of Using Bare Die

290

The Packaging Process

290

A d v a n c e d P a c k a g i n g Techniques

293

Sliding Down the Rabbit Hole

293

Wire Bonds Versus Flip-Chip

293

Wire Bonding and Flip-Chip

294

Contents

Chip-Scale Package [CSP) Technology

294

3-D Die Stacking

295

System-in-Package [SiP], PiP, and PoP

296

A Positive Plethora of Substrates

297

An Example SiP Based on Cofired Ceramics

298

Low-Fired Cofired Ceramics

CHAPTER 21

301

Assembly and Packaging

301

Pin Grid Arrays

302

Pad, Ball, and Column Grid Arrays

302

Fuzz-Buttons

304

Populating the Die

304

The Mind Boggles

305

A l t e r n a t i v e a n d F u t u r e Technologies

307

A Smorgasbord of Technologies

307

Reconfigurable Computing

307

Elemental Computing Arrays (ECAs)

310

Optical Interconnect

314

Fiber-Optic Interconnect

314

It Pays to Keep Your Eyes Open

317

Free-Space Interconnect

317

Guided-Wave Interconnect

318

Optical Memories

320

Protein Switches and Memories

321

Electromagnetic Transistor Fabrication

324

Heterojunction Transistors

325

Виску balls and Nanotubes

328

Diamond Substrates

331

Chemical Vapor Deposition

331

Chemical Vapor Infiltration

332

Ubiquitous Laser Beams

332

The Maverick Inventor

333

The Requirement for Single-Crystal Diamond

333

Conductive Adhesives

334

Superconductors

335

Nanotechnology

337

Back to the Water Molecule

337

Imagine a Soup

339

Once Again, the Mind Boggles

341

Summary

342

Contents

SECTION 3 • Design Tools and Stuff CHAPTER 2 2

General Concepts

345

Stuff, More Stuff, and Yet More Stuff

345

The Origins of EDA

345

Computer-Aided Design (CAD)

346

Computer-Aided Engineering (CAE)

346

Designers Versus Engineers

347

Electronic Design Automation (EDA)

347

Automation

347

Embedded Systems

348

Programming Versus Hardware Design Languages

349

Netlists

350

Transistor-Level

350

Gate-Level

351

Component-Level

351

Different Levels of Abstraction Transistor-Level

352

Switch-Level

352

Gate-Level

353

Structural

353

Functional (Boolean, RTL)

353

Behavioral

354

Algorithmic

354

Different Languages

CHAPTER 2 3

351

354

Programming Languages

354

Scripting Languages

355

Hardware Description Languages (Digital)

355

Hardware Description Languages (Analog)

358

Verification Languages (General)

358

Verification Languages (Formal)

358

Electronic System Level (ESL)

359

Design a n d V e r i f i c a t i o n Tools

361

Weasel Words

361

Design Capture

361

Transistor-Level and Gate-Level Netlists

361

Schematic Capture

362

Higher Levels of Abstraction

363

Graphical Design Entry Lives On

363

Functional Verification (Simulation)

364

Formal Verification

365

Logic Synthesis

366

Layout (Place-and-Route)

367

Parasitic Extraction

367

Timing Analysis

368

Static Timing Analysis (STA)

368

Statistical Static Timing Analysis (SSTA)

369

Design for Manufacturability (DFT)

370

And So Much More

371

Schematic Synthesis

371

Analog Synthesis

371

RF/Microwave Design Tools

372

Hardware Simulation Acceleration and Emulation

372

Mixed-Signal Simulation

373

Physical Verification (DRC, ERC, LVS)

373

Signal Integrity (SI) Analysis

374

Thermal Analysis

374

Power Analysis

374

Electromagnetic Interference and Compliance

APPENDIX A

(EMI and EMC)

374

SCAN, BIST, JTAG, etc

375

Automatic Test Pattern Generation (ATPG)

376

Fault Simulation

376

Turn That Frown Upside Down

376

A s s e r t i o n - L e v e l Logic

377

APPENDIX В

P o s i t i v e V e r s u s N e g a t i v e Logic

383

APPENDIX С

R e e d - M ü l l e r Logic

389

APPENDIX D

G r a y Codes

393

APPENDIX E

Linear F e e d b a c k Shift Registers (LFSRs)

407

APPENDIX F

Pass-Transistor Logic

423

APPENDIX G

M o r e on Semiconductors

427

APPENDIX H

Rounding A l g o r i t h m s l O l

435

APPENDIX I

A n I n t e r e s t i n g Conundrum

455

APPENDIX J

A No-Holds B a r r e d S e a f o o d G u m b o

459

Glossary

465

Index

525