behavioral modeling of rf filters in vhdl-ams for automated architectural ...

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➡ BEHAVIORAL MODELING OF RF FILTERS IN VHDL-AMS FOR AUTOMATED ARCHITECTURAL AND PARAMETRIC OPTIMIZATION T. J. Kazmierski and F. A. Hamid School of Electronics and Computer Science, University of Southampton, UK ABSTRACT This contribution presents a methodology, based on VHDL-AMS modeling, for architectural and parametric optimization of high-frequency analogue filters, used in the process of automated synthesis. The synthesis methodology has been designed around the usage of VHDL-AMS parse trees as an intermediate system representation. Behavioral description of filters combines the familiar mathematical/numerical expressions which contain the vital design parameters of an analogue filter such as the quality factor and frequency range. The user specification is processed by the Filter Synthesis Tool named FIST which produces a selection of analogue filter circuits that are suitable for integrated high-frequency applications. 1.

INTRODUCTION

The need for a mixed-signal synthesis environment is increasing along with the advancement in technology and the demand from commerce, especially the telecommunication industry that is promoting integrated wireless communication. It is now very common to find systems with a mixture of analogue and digital circuits, especially in ASIC (Application Specific Integrated Circuit) designs. Although often comprising a small part of a mixed analogue-digital system, the analogue part of an ASIC often causes the bottleneck in design time and effort. This is because the development of CAD (Computer Aided Design) tools in recent years has concentrated mainly on automatic design of digital circuits while the automation of analogue designs remains largely a heuristic and a labor-intensive task. There are two main reasons for the significant popularity high-level digital synthesis has gained during the last decade. Firstly, high-level digital design specifications are now very well supported by suitable hardware description languages, for example, VHDL and Verilog, which allow design constraints and functional descriptions to be clearly stated. Secondly, methods and algorithms for digital synthesis and design optimization have been well established and are supported

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by a large number of software tools used on an industrial scale throughout the integrated circuit design community. The development of appropriate synthesis methodologies to support mixed-signal ASIC designs is still lagging. While digital designs are now fully automated and can be delivered extremely quickly, the analogue part of a typical ASIC still needs to be designed manually. One of the obvious difficulties has been the absence of a mixed-signal high-level hardware description language commonly accepted as a standard throughout the CAD industry. However, the official emergence of VHDL-AMS (VHDL with analogue and mixed-signal extensions) [1] by IEEE in 1999 is likely to change this. VHDL-AMS extends the modeling power of VHDL to systems that exhibit continuous behavior both in time and amplitude. Recently there has been a steady gain of research interest in the field of analogue circuit synthesis [2]. While the earlier analogue synthesis tools are mainly knowledgebased [3-5], in which synthesis mainly relies on a database of information regarding circuit structure and behavior, the more recent analogue synthesis tools are optimizationbased [6-8], where the synthesis problem is viewed as an optimization task. 2. ANALOG ARCHITECTURAL SYNTHESIS Architectural circuit synthesis is the physical realization of a circuit from the concept of its desired functionality. This contribution concentrates on the first two aspects, which are topology generation and device sizing, and our specific application is targeted towards the synthesis of continuous-time RF filter circuits. An automated synthesis tool, named FIST, has been developed for this purpose. The input of FIST is a high-level VHDL-AMS behavioral description and the output is a HSPICE netlist of the best filter topology that realizes the input specifications. FIST recognizes and hence, can synthesize, certain types of filter elements either in the time domain using differentialalgebraic equations (DAEs) or in the frequency domain using s-domain transfer functions.

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➡ 3. OUTLINE OF SYNTHESIS ALGORITHM Figure 1 shows the implementation of the synthesis algorithm implemented in FIST [9]. FIST scans the parse tree for synthesizable syntax to finally produce a filter netlist that will be parametrically optimized using a threetier optimization. The optimization algorithm comprises the use of stochastic search, non-linear simplex and builtin HSPICE curve-fitting optimizer. VHDL-AMS analogue filter description

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Calculate filter coefficient values

types used by FIST are OTA-C (Operational Transconductance Amplifier-Capacitor) and active LC circuits incorporating on-chip spiral inductors. Each filter cell in the library serves as a template where the critical parameters that influence and affect the filter performance and specification are selected for optimization. The main performance measure for each filter cell is the accuracy of the match between the simulated frequency response and the ideal curve obtained from the VHDL-AMS specification. Other performance criteria are power consumption and area. This technique has proved particularly useful for high-frequency filters in which parasitic effects and high-order MOS effects such as subthreshold and very short channel behavior cannot be ignored. One important point regarding the effect of parasitic capacitances is that the effective MOS transconductance itself becomes frequency-dependent, and it can drop significantly with the increase in frequency. This is particularly important in the optimization of OTA filter cells which depends largely on the optimization of the specific OTA cell alone.

Map to filter cells & produce netlist Three-tier parametric optimisation

4. CASE STUDY: SYNTHESIS OF A 1GHZ 4TH ORDER BANDPASS FILTER The following VHDL-AMS model was used to specify the desired behavior of the 1GHz 4th order band pass filter:

NO Accuracy accepted?

constant a: real:= 0.2e18; constant b: real:= 1.551e39; constant c: real:= 1.114e28; constant d: real:= 7.880e19; constant e: real:= 0.2828e9; constant num: real_vector:= (0,0,a); constant den: real_vector:= (b,c,d,e,1.0); ... Vout == Vin'LTF(num,den);

YES HSPICE netlist Yes

Figure 1: Flow chart of FIST, the VHDL-AMS architectural synthesis system for high-frequency analogue filters. When a synthesizable construct is found, the synthesizer employs a static calculator to scan the parse tree in a recursive manner, to evaluate the required filter coefficients from the user defined VHDL-AMS code. After the filter specification is obtained, high order filters (i.e. of order more than 2) are mapped into configurations of first and/or second order cells. The resulting configurations are then parametrically optimized and the best configuration is selected. The parametric optimization relies on the error figure calculated as the difference between the desired and actual AC characteristics. AC analysis is performed by full HSPICE simulation around a DC operating point which is included around the optimization. The FIST filter cell library is a collection of HSPICE filter netlists with topologies suitable for highfrequency integrated-circuit implementation. The main

Most high frequency band pass filters for integrated implementations are designed either around OTA-C configurations, or Q-enhanced LC circuits with silicon inductors. The latter are typically implemented using onchip spiral structures, where the Q of the inductors are typically small due to the losses in the spiral. The small Q can be enhanced by using negative resistance circuits that cancel the effect of the losses [10-12]. The 2nd order LC filter cell designed for FIST is based on a very effective, Colpitts-type LC oscillator whose positive feedback provides a mechanism for Q-enhancement. Another FIST cell that produces both a band pass and low pass response is a vertically stacked current-mode biquadratic filter implemented around the regulated cascode configuration. This circuit also includes Q-tuning circuitry and is realized by vertically stacking two fully-differential biquad circuits. The FIST library also has a cell that produces a fourth-

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➡ order band pass response; which is the coupled resonator, build with two sections of resonant circuits [12]. In the OTA-C topology, two basic second-order band pass filter are cascaded two produce a fourth-order response. Three different OTA from [13] are evaluated in this cascaded OTA-C structure. Many other available OTA circuits [14] that can also be used for the OTA-C filter.

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(c) Figure 2: Sample fourth-order bandpass configurations analysed by FIST (a) cascade of bandpass biquads: Colpitts and OTA-C (b) Chebyshev vertical cascode in a bandpass configuration, (c) coupled resonator filter. Table 1 presents a summary of the results. The main variables for parametric optimization in all cases are the transistor widths, bias currents and capacitances. The three-tier optimization selected a cascade of two 2nd order wide-swing OTA cells as the best topology in terms of the matching error. This error is calculated as the difference between the AC simulation result in each optimization loop with 6 points on the ideal curve located in the critical frequency range between 0.13 GHz to 4.3 GHz. The AC

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transfer function of the best topology simulated by HSPICE is shown in Figure 3. FIST rejected the LC cascade for which an acceptable matching figure could not be found. It is worth noting that the power consumption of the single-transistor LC structures for this frequency range also turns out to be excessive. The LC-OTA-C topology is the cascade of the LC Collpits circuit and an OTA-C biquad section using a folded-cascode OTA.

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➠ Topology

Matching Size (number Power error of MOSFETs) (mW) Cascade 1 0.0611 48 137 3. Cascade 2 0.0658 48 266 Cascade 3 2.274 74 475 Vertical 0.0688 10 484 LC 2.999 80 5456 LC-OTA-C 0.0833 25 32 Table 1: Optimization results for five different topologies analyzed by FIST to synthesise a fourth-order 1GHz band pass filter with a Q factor of 50. (Cascade 1 uses wideswing OTA cells, cascade 2 - folded-cascode OTA, and Cascade 3 -wide-swing folded-cascode OTA ones).

Figure 3: AC simulation results of the best topology for the 4th order band pass filter. 5. CONCLUSION This contribution presents an efficient methodology for synthesis of integrated high-frequency analog filters from behavioral VHDL-AMS specifications. The synthesis algorithm used by FIST that is based on the parse tree of the behavioral VHDL-AMS has been explained. Also inclusive and vital in FIST’s synthesis methodology is the optimization step that is based on HSPICE’s built in optimizer that works on a selection of filter cells from a library to give the best filter circuit in terms of accuracy. As the main application for FIST is targeted for integrated high-frequency use, the filter cells as well as the optimization formulation were geared for this. The feasibility of the method has been demonstrated by the automated design of a 4th order 1GHz band-pass filter. 11. REFERENCES 1. IEEE standard VHDL analog and mixed-signal extensions. 23 Dec. 1999, Design Automation Standards Committee of the IEEE Computer Society.

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2. Gielen, G. and R.Rutenbar, Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits. Proceedings of the IEEE, 2000. 88(12): p. 1825-1852. Degrauwe, M.G.R., et al., IDAC: An Interactive Design Tool for Analog Circuits. IEEE Journal of Solid-State Circuits, 1987. 22(6): p. 1106-1115. 4. Harjani, R., R.Rutenbar, and L. Carley, OASYS: a framework for analog circuit synthesis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1989. 8(12): p. 1247-1266. 5. El-Turky, F. and E.E. Perry, BLADES: An Artificial Intelligence Approach to Analog Circuit Design. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 1989. 8(6): p. 680-692. 6. Krasnicki, M., et al. MAELSTROM: Efficient Simulation-based synthesis for custom analog cells. in ACM/IEEE 36th D. A.C. 1999. 7. Phelps, R., et al., Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2000. 19(6): p. 703 717. 8. Plas, G.V.d., AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2001. 20(9): p. 1037 -1058. 9. Hamid, F. and T.J. Kazmierski. FIST - a VHDL-AMS based architectural synthesis strategy for integrated high-frequency analogue filters. in FDL. 2003. Frankfurt, Germany. 10. Lee, T.H., The Design of CMOS Radio-Frequency Integrated Circuit. 1998: Cambridge University Press. 11. Li, D. and Y. Tsividis, Active LC filters on silicon. IEE Proceedings of Circuits, Devices and Systems, 2000. 147(1): p. 49-56. 12. Kuhn, W.B., F.W. Stephenson, and A. Elshabini-Riad, A 200 MHz CMOS Q-Enhanced LC Bandpass Filter. IEEE Journal Solid-State Circuits, 1996. 31(8): p. 1112-1121. 13. Baker, R., H. Li, and D.E. Boyce, CMOS circuit design, layout, and simulation. IEEE Press series on Microelectronic systems. 1998. 14. Al-Hashimi, B.M., et al., Integrated universal biquad based on triple-output OTAs and using digitally programmable zero. IEE Proceedings of Circuits, Devices and Systems, 1998. 145(3): p. 192-196.