Bilayer Pseudospin Field-Effect Transistor: Applications ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

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Bilayer Pseudospin Field-Effect Transistor: Applications to Boolean Logic Dharmendar Reddy, Leonard Franklin Register, Senior Member, IEEE, Emanuel Tutuc, Member, IEEE, and Sanjay K. Banerjee, Fellow, IEEE

Abstract—We have recently proposed a new type of bilayer graphene-based transistor for ultralow-power (perhaps 1000 times less compared with CMOS) room-temperature operation, namely, the bilayer pseudospin field-effect transistor (BiSFET). BiSFET operation is based on gated exciton-condensate-enhanced tunneling. Here, we discuss implementation, operation, and predicted power consumption of BiSFET-based Boolean logic gates, including an inverter, an inverter-based NOR gate, and a programmable NAND / OR , as well as a BiSFET-based memory element. The advantages over CMOS in terms of lower voltage and power are discussed. Index Terms—Beyond complementary metal–oxide– semiconductor (CMOS) graphene, bilayer, graphene, nanoelectronics, pseudospin, tunneling.

I. I NTRODUCTION

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E HAVE recently proposed a new type of graphenebased transistor to enable lower voltage and power operation than possible with CMOS logic [1]. The device, which we call a bilayer pseudospin field-effect transistor (BiSFET), is based on the expected novel electrical properties of two layers of graphene in close proximity. While its operation can be quite sensitive to small voltage changes, the output characteristics are also different than those of a MOSFET. In this paper, therefore, we explore ways of implementing a variety of Boolean logic gates and a memory element using BiSFETs. Of course, the BiSFET is currently only a concept based on predicted physics in a novel material system. We recognize the limitations of theory, particularly initial efforts, and the technological challenges to the realization of BiSFETs. There are certainly no guarantees that such a device can ever be realized. Therefore, it could be argued that by now starting to explore BiSFET logic and memory circuits, we are “putting the cart before the horse.” However, we believe that such circuitlevel work—of which this paper represents only a start—is necessary to help measure the potential payoff of continuing device work (and circuit work) and to inform that work through

Manuscript received November 24, 2009. First published February 25, 2010; current version published April 2, 2010. This work was supported in part by the Semiconductor Research Corporation Nanoelectronics Research Initiative (SRC NRI) South West Academy of Nanoelectronics (SWAN) Center and in part by the Texas Emerging Technology Fund. The review of this paper was arranged by Editor M. Reed. The authors are with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78705 USA (e-mail: dharmareddy84@ gmail.com; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2041280

identification of critical device physics and technological challenges. The BiSFET and its essential operating physics were discussed in [1]. We provide a brief review of that physics and describe the associated SPICE model of the BiSFET used for the circuit simulations of this paper in Section II. Implementation of various Boolean logic gates and their operating principles are discussed in Section III. A BiSFET-based memory cell and associated preliminary SPICE simulations are presented in Section IV. II. P HYSICS AND O PERATION Under certain conditions, electrons in one semiconductor layer can pair with holes in an adjacent layer (both fermions), resulting in electron–hole pairs/excitons (bosons) that can then condense. The pairing of electrons and holes in closely spaced 2-D electron–hole bilayer systems has been a topic of continued research interest. The phenomenon was theoretically first predicted by Lozovik and Yudson [2], whereas experimental investigations have focused on closely spaced electron–hole bilayers in GaSb–InAs [3], Si [4], and GaAs [5], [6]. The electron–hole pairing, namely, exciton formation, and the ensuing Bose condensation qualitatively alter the quantum wavefunctions in the bilayer, converting states that were isolated in one of the two layers into states that are a coherent linear combination of top-layer (pseudospin up) and bottom-layer (pseudospin down) components. This qualitative change effectively shorts the two layers through coherent many-body tunneling, reducing the interlayer resistance from a large value associated with the limited single-particle tunneling rates, to a value primarily limited by the contacts. This dramatic reduction in tunnel resistance only applies for small interlayer biases, however. Once the interlayer current reaches a critical value, which, in turn, depends on single-particle tunneling rate and carrier density [7], [8], the tunnel resistance significantly increases. So far, this Bose condensate has been observed only at very low temperatures and under high magnetic fields in GaAs/AlGaAs double-quantum-well systems [7]–[10]. However, as a consequence of a synergy of multiple properties of graphene—a single atomic layer thick with nearly perfect electron–hole symmetry in the band structure, a low density of states, and a zero bandgap—it has recently been predicted that this condensate could occur at much higher temperatures, possibly above room temperature, in otherwise weakly coupled and oppositely charged graphene double/bilayer systems [11], [12]. The predicted maximum temperature for coherence

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be induced in the graphene layers by use of differing work functions for the gates, or ferroelectric oxides as dielectrics, and/or backgating. Applied gate voltage signals are intended only to balance or slightly unbalance the charge concentrations between layers to improve or degrade the electron–hole pairing and the ensuing interlayer tunneling current. Furthermore, in most cases considered here, a switchable input signal to only one gate is required, leaving a good deal of flexibility in what constitutes the other “gate.” In addition, a fixed input voltage signal to these other gates could effectively be achieved via small changes to gate work function, etc. Qualitatively, it is expected that the interlayer tunneling current Ipn increases with the interlayer voltage difference Vpn = Vp − Vn until it reaches a maximum current Imax at an associated interlayer voltage Vpn = Vmax . It then decreases back toward zero while exhibiting a negative differential resistance (NDR) with a further increase of interlayer voltage as the condensate becomes unstable [14]. Any charge imbalance between the layers induced by unbalanced gate voltage signals VG,p and VG,n to p- and n-type graphene layers, respectively—with fixed input signals effectively obtainable as noted above—will reduce the initial quality of condensate and, thus, Imax . This qualitative behavior is illustrated in Fig. 1(d). For specificity only, as required for SPICE simulations, for most of this work, this behavior is approximated via the smoothed interlayer current versus interlayer voltage relation, i.e., Ipn = Go Vpn 1 +

Vpn /Vmax exp (1 − |Vpn |/Vmax )

4 −1/4

with gate-voltage-dependent Vmax , i.e., −10|Δp − Δn| Vmax = Vmax,o exp (no + po )

Fig. 1. (a) Device schematic of a BiSFET. (b) Flowchart of BiSFET operation. (c) Equivalent circuit model. (d) I–V characteristics of a BiSFET for three different gate voltages VG,n with VG,p = −25 mV.

is slightly above 0.1EF /kB , where EF is the magnitude of the Fermi energy relative to the band edge [11], [12], which translates to no ≈ po ≈ 5 × 1012 /cm2 for condensates above 300 K [1]. Single-layer graphene sheets have been gated up to density values in excess of 1013 /cm2 [13]. The BiSFET represents one attempt to explore the applicability of this novel predicted behavior for graphene bilayers to achieve device functionality, in this case, low-power switching. A functional schematic of a BiSFET intended to represent only the essential device elements, not a specific fabrication scheme, is shown in Fig. 1(a). A p-type and an n-type layer of graphene are separated by a dielectric tunnel barrier to limit the bare charge carrier transport/tunneling between layers. As illustrated, each graphene layer has a metallic contact and is electrostatically coupled to a gate electrode through a gate dielectric. In the absence of applied gate biases, carriers could potentially

(1)

(2)

where Δn and Δp are the variations in charge density values with all four terminal voltages consistent with the model of Fig. 1(c). There remains much work to be done on the device side to better quantify this behavior. In this paper, the focus is on how this qualitative behavior might be applied to logic circuits. For example, we note here and demonstrate at the end of Section III-A that the actual form of the decay in the NDR, i.e., Ipn ≈ Go Vmax exp(1 − |Vpn |/Vmax ) for (1), is not critical for at least the logic gates. Again, only for specificity, for all the simulations presented below, the following model parameter values have been used in accordance with the calculations in [1]. All gate lengths have been chosen to be L = 10 nm, slightly larger than the estimated Josephson length. Unless otherwise specified, the gate/channel width for BiSFETs shown in the circuits is W = 20 nm for a W/L ratio of 2; larger specified values of W/L indicate wider gates. Effective oxide thicknesses of 1 nm are assumed for gates, and interlayer dielectrics correspond to respective capacitances CG,p , CG,n , and Cil , all of 3.5 × 10−6 F/cm2 . This choice does not imply that the same oxides should be used. For example, low-k dielectrics, particularly for the interlayer dielectric, are advantageous to forming the condensate, allowing a physically thinner tunnel barrier while limiting the

REDDY et al.: BISFET: APPLICATIONS TO BOOLEAN LOGIC

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signal Vin to the gates will not switch the output signal under these conditions. As shall be seen, this insensitivity to the input voltage can be useful. However, this insensitivity is also clearly incompatible with use of BiSFETs as simple dropin replacements for MOSFETs in conventional CMOS logic elements.

III. B OOLEAN L OGIC G ATES In this section, we illustrate how Boolean logic gates, nevertheless, could be implemented using BiSFETs. To this end, we rely on SPICE simulations implemented with the previously described device model.

A. Inverter

Fig. 2. (a) BiSFET-based inverter. (b) I–V characteristics of (solid) B1 and (dash) B2 for a fixed supply voltage Vs of 25 mV and three different input voltages Vin (in millivolts) shown along the curves. The magnitude of current |Ipn | across the devices B1 and B2 is plotted on the Y -axis. The voltages across the terminals for B1 and B2 are shown on the bottom X-axis and the top Xaxis, respectively. The intersection points of the curves for B1 and B2 indicate possible stable operating points.

interlayer capacitance. The nominal carrier density values in graphene layers were taken to be po ≈ no ≈ 5 × 1012 cm−2 to allow room-temperature operation, as discussed in Section II. These density values could be provided by, e.g., opposing gate work functions of approximately ±1 eV, respectively, or by one ±1 eV gate work function and an opposing fixed “back-gate” bias. Because of the substantial qualitative differences between BiSFET behavior and that of MOSFETs—e.g., current decay rather than saturation with an increased interlayer (effective source-to-drain) voltage—entirely different ways of implementing Boolean logic are required using BiSFETs. Consider, for example, two BiSFETs, B1 and B2, in a CMOSinverter-like layout with a fixed power supply voltage Vs of 25 mV, as shown in Fig. 2(a). The solid curves in Fig. 2(b) are the current–voltage (I–V ) behavior of B1 for three different input voltages Vin = 0, 12.5, and 25 mV, as obtained from (1) and (2). The dotted curves, which represent the load line for B1, are the I–V behavior of B2 at the same input and supply. The voltage axis for the I–V characteristics of BiSFETs B1 and B2 is indicated by the arrows in Fig. 2(b). The three points of intersection for each input voltage indicate stable points of operation, with associated output voltages of Vout ≈ 0, 12.5, or 25 mV. However, as can be seen, these output voltages show little dependence on the input voltage. That is, the input

Despite the above discussion, a BiSFET-based inverter can be realized within the CMOS-like complementary layout of Fig. 2(a). However, as suggested by the preceding discussion, the supply voltage Vs cannot be held fixed. Rather, it must be ramped up and down as a function of time t. Consider first, for simplicity, a low-frequency operation with a clocked power supply voltage Vs (t) varying between 0 and 25 mV, as illustrated in Fig. 3. Fig. 3(a) shows the quasi-static I–V characteristics for BiSFETs B1 and B2 of Fig. 2(a) for values of the now clocked supply voltage Vs (t) increasing from 0 to 25 mV, for a fixed (“high” or “one”) 25-mV gate input voltage Vin . The voltage axis for the I–V characteristics of BiSFETs B1 and B2 is shown by the solid and dotted arrows in Fig. 3(a). The numbered (nonuniformly) time-ordered intersection points of the I–V characteristics of B2 with the lower edge of the figure indicate the supply voltage; the intersection points of the I–V characteristics of the two BiSFETs with each other indicate the corresponding output voltage. Fig. 3(b) shows the same for a fixed (“low” or “zero”) 0-mV Vin . Fig. 3(c) shows the clocked supply voltage Vs (t), an input signal Vin (t) shaped to illustrate that only the input signal during the upward clock ramp matters, and the corresponding output voltage Vout (t) as a function of time. In the case of a high gate input voltage (logic 1), as per Fig. 3(a) and Vs (t) = 0 mV, the interlayer voltage drop across both BiSFETs is zero, along with the output voltage. As Vs (t) begins to increase with both BiSFETs in their low-resistance states, Vs (t) is split approximately equally across the two BiSFETs, and Vout (t) begins to increase, as the intersection point of the two BiSFET I–V characteristics begins to move up and to the right. However, at Vs (t) ≈ 8 mV, the current in the BiSFET with the (more) unbalanced bilayer charge density values, i.e., B2, reaches its maximum allowed value. Beyond this value of Vs (t), B2 enters into its NDR regime, and the current through both serially connected BiSFETs must decrease, and the intersection point of the two I–V curves now begins to move back down and to the left. By the time Vs (t) reaches 25 mV, B2 is in a high-resistance state well into its NDR regime while B1 remains in a low-resistance state, Vs (t) is predominately dropped across B2, and Vout (t) approaches 0 mV (logic 0).

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Fig. 3. Quasi-static I–V characteristics of BisFETs (solid line) B1 and (dashed lined) B2 of the inverter shown in Fig. 2(a) with adiabatically varying clocked supply voltage Vs (t) and fixed Vin of (a) 25 mV and (b) 0 mV. (c) Results of SPICE-based simulations of the BiSFET inverter showing the lowfrequency clocked supply voltage Vs , deliberately aperiodic input signal—to illustrate that only the input signal during the upward clock ramp matters—and the corresponding output voltage Vout . The small squares in (c) correspond to the similarly marked time-ordered numbered intersection points in (a) and (b).

The operation of the inverter with Vin = 0 (logic 0) [Fig. 3(b)] can be understood in a similar way. This time, however, B1 has the unbalanced charge density values and reaches its maximum current value and enters into its NDR regime with increasing Vs (t). Accordingly, by the time Vs (t) reaches 25 mV, Vs (t) is predominately dropped across B2, and Vout (t) also approaches 25 mV (logic 1).


In either case, as illustrated in Fig. 3(c), the input is required to set the output signal, but not to maintain it. In addition, in terms of timing, the output signal follows the clock signal and not the input signal. In other words, each gate shows a self-latching behavior such that, once the output of a gate is determined, the prior gate can be released for processing subsequent information. In a sequence of BiSFET-based gates, there is no need to hold the input to the first gate until the output of the final gate is determined such as in CMOS. The cost is having to clock each gate. Note that Fig. 2(a) merely represents one possible inverter configuration. For example, which gate of which BiSFET has a fixed signal and which gate is switched is of secondary importance. Of primary importance is only that the charge distribution in one BiSFET is initially (more) balanced, and the other is (more) unbalanced as the clock signal is ramped on. At higher frequencies, the displacement currents that are required to quickly charge the various capacitances must also be considered, and the current flows and output voltages will no longer precisely follow the intersection points of the quasistatic curves of Fig. 3(a) and (b). In addition, at sufficiently high combinations of frequencies and capacitive loads, these displacement currents will (as for conventional CMOS) cause the logic to fail, hereby, e.g., pushing B2 into its NDR region during the ramp-up of Vs (t) via load currents running through it, but not B1, even when it has the larger of the two gatecontrolled values of Imax . Still, we have been able to run this BiSFET inverter gate at 100-GHz in SPICE simulations with a seven-inverter fanout load representing some combination of subsequent gates and interconnect capacitances. Results for, e.g., one and four inverter loads are shown in Fig. 4 (and will be further discussed below). In these simulations, the clocked power supply Vs (t) signal was taken as trapezoidal in time and delayed relative to the input signal Vin (t)—supplied by a preceding inverter with the same load—by the 2.5-ps rise time of the clock, allowing the latter to be set before the inverter is clocked. In contrast, the timing of the output signal Vout (t) simply follows Vs (t). We have confirmed that further fan-out is possible by reducing the clock rate and/or by optimizing the fixed gate voltages. It should also be possible by optimizing the shape of Vs (t) and/or the relative peak/charge-balanced values Imax for the two BiSFETs, as will be discussed in future work. To calculate the consumed energy by the BiSFETs themselves per switching in such an inverter, ignoring parasitics, we integrated the instantaneous power supplied by Vs (t), i.e., Ps (t) = Vs (t)Is (t), over one clock cycle in SPICE simulations, where Is (t) is the current flowing out of the clocked supply to one BiSFET inverter with its output Vout (t) serving as the logical input signal Vin (t) to a following inverter, as shown in Fig. 4(a). This way, both resistive energy losses across the BiSFETs, which occur during switching and under quasi-static conditions, and capacitive charging energies for the BiSFET gates, which occur only during switching, were considered. The energy used per inverter was then averaged over the two logical states and divided by 2 to obtain the average switching energy per BiSFET, of approximately 7 zJ (1 zJ = 10−3 aJ) per clock period, for these 100-GHz SPICE simulations. For


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depending on whether those negative instantaneous power contributions are included in the energy integral. Comparing the time-dependent power Ps (t) consumed during the clock cycle for high- and low-output states, significantly more energy is consumed during the Vs (t) ramp-up for a high output, as required to charge the gates of the subsequent inverters. However, particularly during the Vs (t) ramp-down as the subsequent gates are discharged, the current flows back into the supply, and some of that energy could be returned. The degree will depend on how the clocked power supply Vs (t) is generated and how it is shared among gates—where gates in a low-output state are still net consumers of power during the ramp-down of Vs (t)—which are issues not addressed here. However, the difference is not critical in this paper, where the purpose of such power calculations is only to provide very rough estimates, and in either case, the total consumed energy is quite small. Of course, power consumption in CMOS critically depends on the static source-to-drain leakage current for an OFF-state MOSFET. The analogous current here is perhaps the interlayer tunneling current Ipn within the NDR region at the peak value of Vs (t). In addition, this value is, as previously acknowledged, not well known. Therefore, we have also considered the consumed power—and verified the logical operation of inverters—with a much weaker-than-expected model of decay in the NDR region of the BiSFET characteristic, replacing (1) with 4 −1/4 Vpn /Vmax Ipn = Go Vpn 1 + (3) Vmax /|Vpn |

Fig. 4. Supply voltage, illustrated input voltage signal string (from a preceding inverter), and inverted output signal obtained using SPICE; current supplied by the supply voltage, i.e., Is ; and instantaneous power supplied by the supply voltage source, i.e., Ps = Vs ∗ Is , for an inverter with (a) one-inverter load and (b) four-inverter load.

comparison, according to the International Technology Roadmap for Semiconductors [15], current CMOS logic consumes 100 aJ per switching, and the “end of the roadmap” CMOS in 2020 will consume about 5 aJ. However, we have ignored the power dissipation required to deliver the clocked supply voltage. In addition, because whether the logical input state changes between clock cycles has little, if any, effect on power consumption, the gate activity factor is effectively unity as long as there is a clocked Vs (t) provided. The switching energy quoted above, however, does contain some small negative instantaneous power Ps (t) contributions to the energy integral, as shown in Fig. 4(a). While of little consequence in that case, as the number of subsequent gates and/or interconnect capacitances increases, along with an expected increase in the total consumed energy, the importance of the negative power contributions increases as well. For example, if we increase the load to four inverters, as shown in Fig. 4(b), the calculated average power per BiSFET to the original inverter increases to either approximately 8 or 12 zJ,

which decays in the NDR region as only I ≈ ±Go Vmax [Vmax /|Vpn |]. The consumed energy per clock cycle per BiSFET was 24 zJ due to increased resistive losses. While not insignificant, the large on/off ratio change is far less important here than it would be for CMOS because little time is spent under quasi-steady-state conditions; the input is set, the clocked supply signal is ramped on setting the output in the process, the output is held only long enough to set the output of the next gate, then the supply signal is ramped back off. In addition, a 25-mV signal level used through most of this work was chosen as a rounded-off approximation to kB T at room temperature. With the assumed device characteristics and parameters of Section II, the basic logic operation still works for lower voltages, as illustrated in Fig. 5(a), which shows the inverter characteristics with a peak clock voltage of only 15 mV, although with the clock pulsed at only 50 GHz. However, the consumed energy per BiSFET per clock cycle with a one BiSFET inverter actually increased to 38 zJ due to increased steady-state leakage power over a longer period of time. Of course, at a lower voltage, the gate and interconnect charging energies would decrease. Accordingly, the optimal supply voltage level would undoubtedly depend on application, as for CMOS, and, of course, actual BiSFET characteristics. Thus, we emphasize that the energy numbers provided here are intended only to ballpark the potential of BiSFET-based logic. The inverter (and BiSFET gates in general) also shows gain and signal restoration. Indeed, there is a transition input voltage determined by the fixed gate voltages, below which all values

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Fig. 6. Supply voltage, illustrated input voltage signal string (from a preceding inverter), and output signal of a follower with four followers as load.

−13.5 mV, the full 25-mV output signal can be driven only by an 8-mV input signal, as shown in Fig. 5(b), for a four-inverter load. This simulation was intended to mimic a case where the input signal from a previous stage is degraded, possibly due to voltage drops across long interconnects. B. Signal Follower The inverter of Fig. 2(a) can readily be converted to a signal follower by, e.g., setting the p-gate voltage of B1 to 0 mV and that of B2 to −25 mV (or even 0 mV as it turns out), as shown via the result of Fig. 6. Such a gate would be useful in BiSFET circuits for adding delays along a signal line to synchronize signals, as well as for increasing the fan-in or fan-out for a gate. C. Inverter Based OR, AND, NOR, and NAND Gates

Fig. 5. Supply voltage, input voltage signal, and inverted output signal obtained using SPICE for an inverter (a) with a 25-mV 100-GHz clock using the BiSFET I–V model of (3), (b) with a 15-mV 50-GHz clock, and (c) with a 25-mV 100-GHz clock but degraded input voltage, with full output signal restoration.

of input voltage Vin (t) will be processed as logic 0, and above which all voltages above are processed as logic 1, without appreciably affecting the output signal Vout (t) voltage swing. For example, with the p-gate fixed voltage of B1 adjusted to

A conceptually simple way to create a NOR gate is to use the output of one inverter with Input A to power/clock the second with Input B, as illustrated in Fig. 7(a). When Input A is low, the first/upper inverter’s output signal clocks the second inverter in phase with the original clock signal, as shown in Fig. 4. If Input B is also low, the second/lower inverter’s output then follows its clock signal and, thus, the original clock signal, providing a high output from the gate. In contrast, if Input B is high, the output of the second/lower inverter and, thus, the gate will remain low, independent of the output of the first/upper inverter determined by Input A. If Input A is high, there will be no clock signal to the second/lower inverter, and the gate output will again remain low, independent of Input B. We have verified the logical outputs for all four inputs for such a NOR gate via SPICE simulations with the same clock signal and the four-inverter load considered above, as shown in Fig. 7(b). However, the W/L ratio for the first inverter had to be doubled to 4 to provide sufficient drive current to power the second inverter and subsequent loads, increasing the capacitive load for the preceding gate that supplies Input A to the NOR gate. To again consider just the power requirement of the NOR gate,


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Fig. 7. (a) Schematic representation of a NOR gate using two BiSFET-based inverters. (b) Clock signal (100 GHz), input voltage signals A and B, and output signal C.

ignoring parasitics, the consumed energy was calculated via the integration of Ps (t) = Vs (t)Is (t) in SPICE simulations while supplying Input A and Input B to the following NOR gate. The average calculated consumed energy per clock cycle per NOR gate (not BiSFET) was 40 or 48 zJ, depending on whether the negative instantaneous power contributions were considered, respectively. Inverting the outputs of the above NOR gate, of course, creates an OR gate. Inverting the inputs creates an AND gate, as well as eliminating the problem for reduced fan-in for Input A. Inverting both inputs and outputs produces a NAND gate. D. Programmable NAND/OR Gate It may also be possible to take a more direct and flexible route to creating such logic gates. Fig. 8(a) shows a potentially programmable BiSFET-based NAND/OR gate. In this realization, Input A and Input B are applied to the n-gates of BiSFETs B1 and B2, which have a W/L ratio of 2; thus, there is no increase in capacitive load for the preceding gates. Meanwhile, the Boolean functionality of this gate, i.e., NAND or OR, depends on the voltage VNAND/OR applied to the p-gates of both B1 and B2, potentially allowing one to program the functionality of this gate if these “other” gates are indeed contactable. There are no input signals to the larger BiSFET B3; however, its n-layer gate does become part of the “output” signal load. The operating principle of this circuit is similar to that of the inverter discussed in the previous section, in that there will be two I–V curves whose intersection point is the output voltage. However, with no input signals, the I–V curve for B3 will be

Fig. 8. (a) Programmable NAND / OR gate and SPICE simulation results of switchable (b) NAND and (c) OR gate operation at 100 GHz.

fixed when the ramp-up of Vs (t) begins. The other I–V curve represents the parallel combination of B1 and B2, and its shape changes with Input A, Input B, and VNAND/OR . A VNAND/OR

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of −25 mV produces a NAND gate functionality, whereas a VNAND/OR of 0 mV produces an OR gate functionality. In this implementation, the W/L ratio of B3 was chosen to be 8. If the W/L ratio was smaller than 6, the maximum current that B3 could supply was insufficient to drive both B1 and B2 and the load when the input conditions are such that both B1 and B2 have the largest possible Imax . This condition always leads to a low output, irrespective of input conditions. On the other hand, if the W/L ratio of B3 was very large, the output was always high. SPICE simulations for this gate are shown in Fig. 8(b) and (c) for NAND and NOR implementations, respectively, again with a 100-GHz 25-mV Vpeak clock signal with an intergate delay of 2.5 ps and a fan-out of four inverters. To once again just calculate the power requirement of the gate, ignoring parasitics, the consumed energy was calculated via the integration of Ps (t) = Vs (t)Is (t) in SPICE simulations for one NAND/NOR , supplying Input A and Input B to subsequent NAND / NOR gates. The average calculated consumed energy per clock cycle per gate (not BiSFET) was 16 or 34 zJ, depending on whether the negative instantaneous power contributions were considered, respectively, for the NAND gate, and was 38 or 50 zJ, respectively, for the OR gate. IV. B I SFET M EMORY C ELL As discussed at the end of Section II, when a BiSFET is used in a CMOS-like inverter configuration with a fixed supply voltage, the output is locked at one of the three possible operating points, at least for limited output loads. The output can, however, be pulled high or low, even with the fixed supply voltage, by effectively “grounding” it—as though adding too much fan-out—to the desired value. With the “ground” removed, the output signal will again be locked. This behavior can be exploited to implement a 2-BiSFET static memory cell, as shown in Fig. 9(a), along with a peripheral circuit to the right used in SPICE simulations to test the functionality of the memory element. Note that all of the BiSFET gates are grounded—that is, no contact to the “gates” is actually required—while the only “input” to the BisFETs is the output/ memory (“mem”) signal. When on, the transmission gate Tx couples the data signal to the bit line. The access gate Ac, in turn, couples the bit signal to the memory element. Writing consists of turning on Tx to charge the bit-line capacitance and turning on Ac to write the data onto the particular memory element from a low-impedance source. That is, effectively grounding the Mem output node of that element, high or low, to exceed the Imax of B2 or B1, respectively, to place it in its NDR region. Reading consists of turning on Ac to write the signal stored in the memory’s bit line and turning on Tx to read the signal from the bit line via, e.g., a high-input-impedance sense amplifier, not to exceed the Imax of the currently on/lowresistance BiSFET. Memory operation can be seen in the transient simulation result shown in Fig. 9(b), which is demarcated into six rows (R1–R6) and four columns (C1–C4) for ease of understanding. For these simulations, a precharge circuit has been added. In the Write cycle for a “one,” the transmission gate is turned on with the Tx pulse (see R1 and C1). When the data signal

Fig. 9. (a) BiSFET-based 1-bit static memory cell, along with the peripheral circuit used for testing (b) SPICE-simulated read and write cycles for the memory cell. Tx, Ac, and Pc are the gate voltages for the MOSFETs, as shown in the circuit schematic. The peak value of gate pulses to MOSFETs is 550 mV. Mem, Data, and Bline are the voltages (in millivolts) at the nodes Mem, Data, and Bline, respectively, as shown in the circuit schematic. The supply voltage is fixed.

arrives (R2 and C1), the bit line goes high (R5 and C1). Then the access gate is turned on (R3 and C1), causing the voltage at the memory node Mem to go high (R4 and C1). When the access is turned off, the BiSFET Mem node is still high, i.e., a “one” is stored in the memory. The data stored in the memory can be read as follows: First the precharge gate Pc is turned on to charge the bit line to a known voltage level. Then, when the access gate is turned on (R3 and C2), the voltage on the bit line goes high (R5 and C2), implying that a “one” is stored in the memory. Similarly, columns C3 and C4 demonstrate the write and read cycles for a “zero.” Note that, during the read cycle for the data bit “one” or “zero” stored in the memory, the bit line goes high or low, respectively. Again, this variation of the bit-line voltage can be sensed using a sense amplifier to read out the stored bits from the memory. For a proof of concept, we have used conventional MOSFETs for the peripheral circuits to perform SPICE simulations, as well as BiSFETs only to implement the memory cell itself. The gate pulses used for the MOSFETs are 550 mV high. The pulsewidth for the access gates is 4 ns, which by no means represents the upper limit on the basic 2-BISFET memory element as evidenced by the prior simulations of logic gates. The results of this simulation should only be read as qualitative verification of functionality. Quantitative aspects such as times for read–write cycles, sensitivity, stability, etc., have not yet been tested.


However, we note that the consumed power by BiSFET memory elements will be much more sensitive than BiSFETbased logic gates to the rate of current decay in the NDR tail of the BiSFET I–V characteristic. However, as the voltage scale is defined by Vmax , which can be less than kB T in principle, low voltage and low static power storage may be possible. V. C ONCLUSION Not only is the operational physics of the BiSFET fundamentally different from that of a MOSFET, but also the expected I–V characteristics. Therefore, BiSFETs cannot be used as mere drop-in replacements for MOSFETs. Rather, their potential usefulness depends on finding different ways of implementing digital logic. In this paper, using SPICE simulations, we have provided limited illustrative examples of how BiSFET characteristics might be used to implement a variety of logic gates with the aid of a clocked power supply, as well as of memory with a fixed power supply. This paper demonstrates the possibility of low-voltage (25 mV in simulation), low-power (a few to a few tens of zeptojoules), and fast (∼100-GHz clock/power signals) logic, as well as a possible memory implementation if BiSFETs can be realized. Of course, as discussed in Section I, such realization is far from guaranteed. However, such circuit-level work should help inform of the experimental effort of practical device requirements and provide motivation for that experimental effort, and perhaps motivation and guidance for consideration of other alternative devices that cannot also be used as drop-in replacements for MOSFETs. ACKNOWLEDGMENT The authors would like to thank G. Carpenter for his useful comments and discussions with regard to the circuit design and A. H. MacDonald for his insights into the physics of interacting bilayers. R EFERENCES [1] S. K. Banerjee, L. F. Register, E. Tutuc, D. Reddy, and A. H. MacDonald, “Bilayer pseudospin field-effect transistor (BiSFET): A proposed new logic device,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 158–160, Feb. 2009. [2] Y. E. Lozovik and V. I. Yudson, “Feasibility of superfluidity of paired spatially separated electrons and holes; a new superconductivity mechanism,” JETP Lett., vol. 22, no. 11, pp. 274–276, Dec. 1975. [3] E. E. Mendez, L. Esaki, and L. L. Chang, “Quantum hall effect in a two-dimensional electron–hole gas,” Phys. Rev. Lett., vol. 55, no. 20, pp. 2216–2219, Nov. 1985. [4] U. Sivan, P. M. Solomon, and H. Shtrikman, “Coupled electron–hole transport,” Phys. Rev. Lett., vol. 68, no. 8, pp. 1196–1199, Feb. 1992. [5] M. Pohlt, M. Lynass, J. G. S. Lok, W. Dietsche, K. V. Klitzing, K. Eberl, and R. Mühle, “Closely spaced and separately contacted two-dimensional electron and hole gases by in situ focused-ion implantation,” Appl. Phys. Lett., vol. 80, no. 12, pp. 2105–2106, Mar. 2002. [6] J. A. Seamons, D. R. Tibbetts, J. L. Reno, and M. P. Lilly, “Undoped electron–hole bilayers in a GaAs/AlGaAs double quantum well,” Appl. Phys. Lett., vol. 90, no. 5, p. 052 103, Jan. 2007. [7] I. B. Spielman, J. P. Eisenstein, L. N. Pfeiffer, and K. W. West, “Resonantly enhanced tunneling in a double layer quantum Hall ferromagnet,” Phys. Rev. Lett., vol. 84, no. 25, pp. 5808–5811, Jun. 2000. [8] L. Tiemann, W. Dietsche, M. Hauser, and K. von Klitzing, “Critical tunneling currents in the regime of bilayer excitons,” New J. Phys., vol. 10, no. 4, p. 045 018, 2008.

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[9] E. Tutuc, M. Shayegan, and D. A. Huse, “Counterflow measurements in strongly correlated GaAs hole bilayers: Evidence for electron–hole pairing,” Phys. Rev. Lett., vol. 93, no. 3, p. 036 802, Jul. 2004. [10] M. Kellogg, J. P. Eisenstein, L. N. Pfeiffer, and K. W. West, “Vanishing Hall resistance at high magnetic field in a double layer two-dimensional electron system,” Phys. Rev. Lett., vol. 93, no. 3, p. 036 801, Jul. 2004. [11] H. Min, R. Bistritzer, J.-J. Su, and A. H. MacDonald, “Room temperature superfluidity in graphene bilayers,” Phys. Rev. B, Condens. Matter, vol. 78, no. 12, p. 121 401, Sep. 2008. [12] C.-H. Zhang and Y. N. Joglekar, “Excitonic condensation of massless fermions in graphene bilayers,” Phys. Rev. B, Condens. Matter, vol. 77, no. 23, p. 233 405, Jun. 2008. [13] P. Avouris, Z. Chen, and V. Perebeinos, “Carbon based electronics,” Nat. Nanotechnol., vol. 2, no. 10, pp. 605–615, Oct. 2007. [14] J.-J. Su and A. H. MacDonald, “How to make a bilayer exciton condensate flow,” Nat. Phys., vol. 4, no. 10, pp. 799–802, Oct. 2008. [15] [Online]. Available: www.itrs.net

Dharmendar Reddy received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology, Kanpur, India, in 2006 and the M.S.E. degree in Electrical and Computer Engineering from The University of Texas at Austin in 2008. He is currently working towards the Ph.D. degree in Electrical and Computer Engineering with The University of Texas at Austin, under the guidance of Dr. L. F. Register. His current research interests include alternative switching methods and/or state variables (beyond CMOS), and quantum transport with scattering.

Leonard Franklin Register (SM’95) received the B.S. degree in electrical engineering, the B.S. degree in physics, and the Ph.D. degree in Electrical and Computer Engineering from North Carolina State University, Raleigh. He is currently an Associate Professor of Electrical and Computer Engineering and Temple Foundation Endowed Faculty Fellow with The University of Texas at Austin, where he is a member of the Microelectronics Research Center. He was a Postdoctoral Student and Research Scientist with the Computational Electronics Group, Beckman Institute, University of Illinois at UrbanaChampaign, before joining the faculty of The University of Texas at Austin in 2000. He is a device theorist whose research is focused on understanding and modeling the essential physics underlying the operation of nanoelectronic and optoelectronic devices. His current research interests include alternative materials and device geometries for CMOS (nonclassical CMOS), alternative switching methods and/or state variables (beyond CMOS), quantum-corrected semiclassical transport, and quantum transport with scattering. He has also published in areas including CMOS reliability, compact modeling, lasers, scattering theory, and single-electron devices.

Emanuel Tutuc (M’07) received the B.S. and M.S. degrees in physics from Ecole Normale Superieure, University of Paris, Paris, France, in 1997 and 1998, respectively, and the Ph.D. degree in physics from Princeton University, Princeton, NJ, in 2004. His Ph.D. research was focused on the MBE growth of ultrahigh-mobility electron systems and the physics of interacting electron systems in two dimensions. Between 2004 and 2006, he was a Postdoctoral Researcher with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where his research centered on the growth and electronic properties of Si and Ge nanowires and heterostructures. He is currently an Assistant Professor of Electrical and Computer Engineering with The University of Texas at Austin. His research interests are the growth and electronic properties of semiconductor nanowires and graphene, and their application to high-speed/low-power transistors. Dr. Tutuc was a recipient of the 2009 NSF CAREER Award, a 2008 DARPA Young Faculty Award, and the Charlotte Elizabeth Procter Fellowship (Princeton).

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Sanjay K. Banerjee (S’80–M’83–SM’89–F’96) received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology (IIT), Kharagpur, India, in 1979 and the M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign in 1981 and 1983, respectively. From 1983 to 1987, he was a Member of Technical Staff with the Corporate Research, Development and Engineering, Texas Instruments Incorporated, Dallas, where he worked on polysilicon transistors and dynamic random access trench memory cells used by Texas Instruments in the world’s first 4-Mb DRAM. He was an Assistant Professor from 1987 to 1990, an Associate Professor from 1990 to 1993, and has been a Professor since 1993 with The University of Texas at Austin, where he is currently the Cockrell Family Regents Chair Professor of Electrical and Computer Engineering and the Director of the Microelectronics Research Center. He is also the Director of the South West Academy of Nanoelectronics, one of the three centers in the U.S. to develop a replacement for MOSFETs. He has more than 740 archival


refereed publications/talks and seven books/chapters. He is the holder of 26 U.S. patents. He has supervised more than 50 Ph.D. and 60 M.S. students. He is currently active in the areas of ultrahigh-vacuum chemical vapor deposition for silicon–germanium–carbon heterostructure MOSFETs, nanoparticle Flash memories, and nanostructures. He is also interested in the areas of ultrashallow junction technology and semiconductor device modeling. Dr. Banerjee is a Fellow of the American Association for the Advancement of Science and the American Physical Society. He was a Distinguished Lecturer for the IEEE Electron Devices Society and the General Chair of the IEEE Device Research Conference in 2002. He was a corecipient of the Best Paper Award at the IEEE International Solid State Circuits Conference in 1986. He was the recipient of the Engineering Foundation Advisory Council Halliburton Award in 1991, the Texas Atomic Energy Fellowship in 1990–1997, the Cullen Professorship in 1997–2001, the NSF Presidential Young Investigator Award in 1988, the SRC Inventor Recognition Award in 2000, the IEEE Millennium Medal in 2000, the ECS Callinan Award in 2003, the Industrial R&D 100 Award (with N. Singh) in 2004, the Distinguished Alumnus Award from IIT in 2005, and the Hocott Research Award from The University of Texas at Austin in 2007.