Bluetooth Low Energy (BLE) Direct Down Conversion ...

2017 First New Generation of CAS

Bluetooth Low Energy (BLE) Direct Down Conversion Receiver Front End in 65nm CMOS Technology M. Nasrollahpour, R. Sreekumar, F. Hajilou, M. Aldacher, IEEE, Graduate Student Member, and S. Hamedi-Hagh, IEEE, Senior Member Electrical Engineering Department San Jose State University CA, USA Abstract-This paper presents a Bluetooth Low Energy (BLE) based receiver that features a low power LNA and a novel passive AND function mixer. The entire receiver is designed and simulated in the TSMC 65nm planar CMOS technology. The receiver benefits from a direct down conversion technique where the baseband signals are separated into I/Q paths based on the phase of the signal. The overall input sensitivity of the receiver is around -65 dBm, whilst the system has an overall noise figure (NF) of 8dB. The overall conversion gain of the system is 17.5 dB and the entire receiver consumes 2.85 mW. Keywords— low energy BLE, Direct down conversion, AND function, reception sensitivity, Noise Figure

Fig. 1. System Level schematic of proposed DCR Rx

of image rejection and IIP3 higher than -30 dBm [8]. Such relaxed specifications make BLE-based transceivers ideal for reducing the cost and power in short-range communication devices. The major challenge in designing BLE-based systems is the attempt to develop minimal power consumption since the power dissipation cannot be simply scaled with the nonlinearities associated with the system.

I. INTRODUCTION Bluetooth Low Energy (BLE) systems is at present the most favourable wireless standard for Internet of Things (IoT) based applications [1-6]. Circuits in BLE systems are always striving to achieve a minimal power consumption, while satisfying the standard requirements. Direct down Conversion Rx (DCR) or zero IF systems are most viable for this standard, because of their low power architecture. Another major advantage of employing the DCR architecture is the absence of image issues, since the signal band lies exactly on the tone of the local oscillator (LO) frequency and eliminates the notion of an image. Furthermore, because the demodulated signal is at the baseband frequency of the system, an LPF filter is employed to filter out harmonics. The LPF can have a more relaxed design when compared to high quality band pass filters that would be needed in heterodyne receivers. This would enable to integrate the LPF on chip, leading to a more compact design.

The mixer circuits in a receiver system often possess a bottleneck, when it comes to attaining a sub-mW based operation for each module. Most active mixer topologies saturate around the 0.5-1.2 mW range and consumes the major part of the power budget. Passive mixers are an alternate solution to lower power consumption, since there is no rail supply in the circuit [9]. However, they have issues such as signal loss in the mixer path, less isolation between the LO-RF and LO-IF path. The critical element which determines the overall NF and robustness of the system is the LNA. It must have a really high sensitivity and work with minimal power to satisfy the requirements of BLE standards.

However, the major issues in a DCR system are I-Q mismatches, LO leakages and dc offset which often appears at the base band signal. This can be rectified by a robust circuit design. Fig 1. depicts the system level block diagram of the proposed Rx system followed by the data conversion and DSP blocks [7]. Current BLE standards propose a target sensitivity of -70 dBm, thereby allowing a more relaxed noise figure (NF) close to 30 dB for the overall architecture of the receiver, 21 dB

978-1-5090-6447-2/17 $31.00 © 2017 IEEE DOI 10.1109/NGCAS.2017.44

In this paper, the design and simulation of a BLE receiver with a direct down conversion topology is discussed. The paper is organized as follows; Section II, III and IV discuss the working and design of the passive AND mixer, LNA and crosscoupled VCO used for the architecture. Section V covers the simulation results of the system.

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II. QUADRATURE PASSIVE MIXER

III. CASCODE STAGE LNA

Passive mixers are primarily voltage switching devices, rather than switching the RF current, as in active mixers. Due to the limited budget of BLE topologies, passive mixers are considered as a promising alternative. However, their lack of gain, and non-linear switching limit the overall performance of the system. Another major issue regarding quadrature passive mixers is the increased noise figure (NF), due to the overlapping between the I (in phase) and Q (out of phase) switches. There are several approaches to tackle this issue, one of them is to develop a 25% duty cycle pulse in the local oscillator. This requires a complex and stringent process for the LO synthesis. One innovative approach is to provide a non- overlapping path with two series switches, driven by different phases of the oscillator. This leads to an AND function mixer [10].

The design of the LNA must be robust and linear to compensate for the non-linearity of the mixer. The gain of the LNA must be substantially high to limit the input referred noise of the system [11], and to ensure that the signal strength at the mixer input is high enough for a distortion-less operation. The cascode topology provides a noticeably high gain and also provides a better isolation than common source topology for LNA applications. A proper isolation is ensured through the common gate stage of the cascode amplifier. Fig. 3. depicts the circuit topology of the implemented cascode stage amplifier along with the inductive source degeneration. The inductive source degeneration allows for a more stable circuit, for BLE frequency bands. The drop in gain due to degeneration is overcompensated through a much higher biasing current. This increase in the current budget is plausible, as the passive mixer allows for a much relaxed budget consideration for other modules.

The major drawback of using the AND function mixer is the increased series resistance in the signal path, thereby, further degrading the noise performance of the system. In this paper, this issue is solved by using optimally designed pass gate transistors for the 2nd stage of the AND function, as shown in Fig. 2. To tackle asymmetrical switching of the mixer, it has been divided into two halves with the opposite firing sequence. This ensures that there is always a path connecting the RF input to the Base Band (BB) port.

Vdd Ld

Vbias1

Cout M2

Lg

C2 RFIN

M1 Cex Ls

Fig. 3. Schematic diagram of implemented cascode LNA.

To ensure a 50 Ω matching to the antenna, the magnitude of the input impedance is critical. The value of the input impedance is approximately expressed as: Z

jω L

L

2

where L , L , C and g are the input gate inductor, source degeneration inductor, parasitic gate-source capacitance and transconductance of the input transistor, respectively. The first two term must cancel each other in order to create a zero imaginary part, while the 3rd term can be designed to match to a 50Ω network. The implementation of the external parasitic capacitor between the gate and source of M1 is to achieve a reasonable value for the inductor Ls.

Fig. 2. Schematic diagram of implemented passive AND mixer.

The addition of capacitor Cp , as shown in Fig. 2 , ensures a better conduction to the output, by providing two paths at a phase difference of 90° from each other. However, there must be a minimal parasitic capacitance to prevent dc leakage from output node to the input. The transmission gates cancel LO-RF and LO-IF leakges at the 2nd stage, thus enabling a much better isolation performance.

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III. QUADRATURE LO GENERATION

V. SIMULATION RESULTS AND COMPARISON

Due to the fact that we require a quadrature LO output, we design a Local Oscillator that runs at twice the operating frequency of the system which is then injected into a frequency divider. The design of a 5 GHz based LC tank VCO, with a coarse and fine tuning mechanism is presented in [12]. A single varactor may not be able to cover the entire frequency range because of a limited tuning voltage. To overcome this bottleneck, we propose to use a coarse capacitor bank, and fine tune the frequency using varactors. The double cross-coupled oscillator naturally provides an output common mode level close to VDD/2 and as a result provides wide tuning range. This circuit can be viewed as two back-to-back CMOS inverters. This architecture is also referred as a current reuse circuit as both NMOS and PMOS pairs share the same current. This feature makes this oscillator a good candidate for low power applications. This architecture provides twice the voltage swing for a given bias current and inductor design. In order to improve the phase noise performance and to save the voltage headroom, the tail current source is eliminated at the expense of more sensitivity to the supply voltage. Fig. 4 depicts the schematic of the implemented 5GHz VCO.

The entire system is designed in the TSMC 65nm CMOS technology and results are simulated using the Cadence Spectre RF. From a system point of view, the crucial parameters that are of significance, are the overall conversion gain (CG) of the system, noise and non-linearity performances. The overall maximum conversion gain of the system is measured to be 17.59 dB, and is mainly provided by the LNA. The CG vs input frequency plot is shown in Fig.6.

Fig. 6. Conversion Gain (in dB) Vs frequency.

To measure the overall noise performance of the system, the NF of the system is simulated and the most optimistic value is around 8 dB. The noise figure shows a steady performance over the bandwidth of 100 kHz - 10 MHz and then steadily rises as the frequency increases. The lower frequency noise is attributed due to the quadrature LO generation scheme. The simulated noise figure is shown in Fig. 7. The frequency axis is normalized to the carrier frequency to illustrate the changes across the BLE bandwidth.

Fig. 4. Implemented CMOS LC VCO circuit.

To provide quadrature LO signals (90º phase-shifted from each other) to the mixer, a frequency divide-by-2 circuit, consisting of both positive-edge-triggered and negative-edgetriggered flip-flops, is used between the VCO and the mixer. Both flip-flops employ the true single-phase clock (TSPC) structure which is of higher speed and lower power dissipation than that in static flip-flops [13]. Fig. 5 shows the system level block diagram of the divide by two circuit.

Fig. 7. Simulated Noise Figure (in dB) vs frequency.

From the noise perspective, although the phase noise of the VCO does not affect the NF of the Rx system, it is at the liberty that the phase noise is kept much lower than a respectable value. Simulations of the phase noise have been carried out at an offset of 10 kHz and 1 MHz, and the respective values are -84dBc and -127 dBc, respectively.

Fig. 5. The frequency divide-by 2 circuit diagram.

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VI.CONCLUSION A BLE front end receiver with a zero IF based down conversion topolgy is presented in this work. The system adheres to the BLE standards and is designed in 65nm CMOS technology. It shows an efficient mixer topology, with promising LO-RF & LO-IF leakage reduction. The overall system shows a promising performance suitable for IoT applications due it’s low power consumption and robustness. REFERENCES [1]

Fig. 8. Phase noise simulations of VCO @ 10kHz & 1MHz offset. [2]

The non-linearity performance of the system is evaluated through the 3rd intercept point (IP3 ) and LO-IF leakage in the mixer. The latter affects the overall linearity at the output of the system. Periodic steady state (PSS) simulations are carried out to depict the same and exhibited isolation performance of -43.67 dB at baseband spectrum of the output, as shown in Fig. 9.

[3] [4]

[5]

[6]

[7]

Fig. 9. PSS Simulations of LO-IF feedthrough.

The 3rd order intercept is measured by applying two blocker signals at the input in order to appears at the frequency of interest after the modulation. By maintaing a constant IF of 1 MHz, the IP3 are listed out, and is simulated to be -22.5 dBm in the channel. The simulated results are summarized in Table I.

[8]

[9]

TABLE I. RESULTS SUMMARY OF PROPOSED WORK. Performance Parameters Supply Technology Conversion Gain NF Phase Noise of VCO IP3 Power Consumption (including LO generation)

Value

[10]

1V 65nm 17.59 dB 8 dB @ 10kHz , -84 dBc @ 1MHz, -127 dBc -22.520 dBm

[11]

[12]

2.85 mW

[13]

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