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POWER CONTROL AND OPTIMIZATION


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POWER CONTROL AND OPTIMIZATION Proceedings of the 3rd Global Conference on Power Control and Optimization Gold Coast, Australia 2 – 4 February 20 10

EDITORS

Nader Barsoum

Curtin University, Malaysia

Gerhard-Wilhelm Weber

Middle East Technical University, Turkey

Pandian Vasant

University of Technology Petronas, Malaysia

All papers have been peer-reviewed . SPONSORING ORGANIZATIONS

Middle East Technical University Curtin University of Technology, Malaysia LINDO Systems Inc. EUROPT HINDAWI

Melville, New York, 2010 AIP CONFERENCE PROCEEDINGS

VOLUME 1239


Editors:c Nader Barsoum Department of Electrical and Computer Engineering School of Engineering Curtin University of Technology 250 CDT Miri 9800, Sarawak Malaysia E-mail: [email protected] Gerhard-Wilhelm Weber Institute of Applied Mathematics Middle East Technical University Ankara, Turkey E-mail: [email protected] Pandian Vasant Electrical and Electronic Engineering Department University of Technology Petronas Bandar Seri Iskandar 31750 Tronoh, Perak Malaysia E-mail: [email protected]

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CONTENTS Preface and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Committees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

KEYNOTE SPEAKERS Computational Electronics and 21st Century Education . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 D. Vasileska

Will Renewable Energy Save Our Planet? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M. Bojić

PLENARY SESSION PAPERS

POWER Power Systems ETAP Software Based Transient, Ground Grid and Short Circuit Analyses of 132 kV Grid . . . . . . . . . . . 25 A. Bashir, R. A. J. Khan, M. Junaid, and M. M. Asghar

Optimization of Long Rural Feeders Using a Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 M. Wishart, G. Ledwich, G. Ivanovich, and A. Ghosh

End-User’s Tools towards an Efficient Electricity Consumption: The Dynamic Smart Grid . . . . . . . . . . . 39 F. Kamel and A. A. Kist

Environment Friendly Coal Based Power Generation in Pakistan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 S. A. Qureshi and M. A. Javed

Transmission and Distribution Genetic Algorithm Based Approach for the Optimal Allocation of FACTS Devices . . . . . . . . . . . . . . . . . . . 53 B. Bhattacharyya and S. K. Goswami

Optimal Allocation and Sizing of Capacitors to Minimize the Transmission Line Loss and to Improve the Voltage Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I. Ziari, G. Ledwich, M. Wishart, A. Ghosh, and D. Cornforth

Practical Genetic Algorithm Based Optimal Capacitor Placement for Loss Reduction and Voltage Regulation in Distribution Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 A. E. Milani, S. Baharestani, and S. Soleymani

Reliability and Protection Hydrophobic Characteristics of Composite Insulators in Simulated Inland Arid Desert Environment . . . 75 Y. Khan, A. A. Al-Arainy, N. H. Malik, and M. I. Qureshi

A Distance Protection Strategic Spare Relay for 132/66kV Overhead Lines . . . . . . . . . . . . . . . . . . . . . . . . . 81 R. T. Harris, A. G. Roberts, A. Marks, and W. Phipps

Effective Implementation of Reliability Centered Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 M. B. Nabhan

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Power System Reliability Assessment by Analyzing Voltage Dips on the Blue Horizon Bay 22kV Overhead Line in the Nelson Mandela Bay Municipality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 B. G. Lamour, R. T. Harris, and A. G. Roberts

A Circuit Model of Quantum Cascade Lasers Applicable to Both Small and Large Current Drives . . . 105 M. K. Haldar and J. F. Webb

Power Electronics and Drives Control of DC Motor Using Different Control Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 H. Alasooly and M. Redha

Simulation of Some of the Power Electronics Case Studies in MATLAB Simpowsystem Toolbox . . . . . . 120 H. Alasooly and M. Redha

Centrally Coordinated Control of Multiple HVDC Links for Power Oscillation Damping . . . . . . . . . . . . 134 R. Eriksson and L. Söder

Hybrid PWM Switching Strategy for a Three-level Inverter Fed Induction Motor Drive with Open-end Windings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 S. Srinivas and K. Ramachandrasekhar

Renewable Energy Design of a Traditional Solar Tracking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 N. Barsoum and P. Vasant

Combined Natural Gas and Solar Technologies for Heating and Cooling in the City of Nis in Serbia . . 159 V. P. Stefanović and M. Lj. Bojić

Implementation of Energy Saving Controller for Electromagnetic Ballast Fluorescent Lamps . . . . . . . . 164 Z. Xiong, Cheong, and N. N. Barsoum

Feasibility Analysis of Wind Power System in Pakistan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 M. M. A. Jawad and S. A. Qureshi

CONTROL Controllers Temperature and Light Control of Three Phase Induction Motor Speed Drive by PIC . . . . . . . . . . . . . . 185 N. Barsoum

Hardware Design and Implementation of Fixed-Width Standard and Truncated 4ⴛ4, 6ⴛ6, 8ⴛ8 and 12ⴛ12-Bit Multipliers Using FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 M. H. Rais

Development of Thermostatic Valve for the House Heating System Using SMA and Remote Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 J. J. Choi, S. T. Kim, and Y. C. Park

Virtex-5 FPGA Implementation of Advanced Encryption Standard Algorithm . . . . . . . . . . . . . . . . . . . . . 201 M. H. Rais and S. M. Qasim

Healthcare Visualization of Heart Sounds and Motion Using Multichannel Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 F. Nogata, Y. Yokota, and Y. Kawamura

Design a Wearable Device for Blood Oxygen Concentration and Temporal Heart Beat Rate . . . . . . . . . 213 C. Z. Myint, N. Barsoum, and W. K. Ing

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Kalman Filter TDOA/FDOA Based Aircraft Localization Using Adaptive Fading Extended Kalman Filter Algorithm . . 223 S. C. Lee, W. R. Lee, and K. H. You

Improved Measurement Accuracy Based on Adaptive Kalman Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 W. R. Lee, S. C. Lee, and K. H. You

Kalman Filter and Fuzzy Logic Estimation of Short Circuit Current Machine Parameters . . . . . . . . . . 234 H. M. Al-Hamadi and K. M. EL-Naggar

Wireless Network Wavelength Requirements for a Scalable Multicast Single-Hop WDM Network . . . . . . . . . . . . . . . . . . . . 247 R. W. Yousif, B. M. Ali, M. K. Abdullah, K. B. Seman, and M. D. Baba

Carbon Nanotube Band Structure Effect on Carbon Nanotube Field Effect Transistor . . . . . . . . . . . . . . 254 M. T. Ahamdi, Z. Johari, R. Ismail, and J. F. Webb

A Shortest Path Algorithm for a Network with Various Fuzzy Arc Lengths . . . . . . . . . . . . . . . . . . . . . . . . 260 A. Tajdin, I. Mahdavi1, N. Mahdavi-Amiri, B. Sadeghpour-Gildeh, and R. Hadighi

OPTIMIZATION Hybrid Optimization Hybrid General Pattern Search and Simulated Annealing for Industrial Production Planning Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 P. Vasant and N. Barsoum

Fuzzy Multiobjective Vendor Selection Problem with Modified S-Curve Membership Function . . . . . . . 278 M. Díaz-Madroñero, D. Peidro, and P. Vasant

Continuous Optimization Execution Time Optimization Analysis on Multiple Algorithms Performance of Moving Object Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 S. Z. Islam, S. Z. Islam, R. Jidin, and M. A. M. Ali

On Foundations of Parameter Estimation for Generalized Partial Linear Models with B-Splines and Continuous Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 P. Taylan, G. W. Weber, and L. Liu

Optimization of Desirability Functions as a DNLP Model by GAMS/BARON . . . . . . . . . . . . . . . . . . . . . . 305 B. A. Ozturk, G. Koksal, and G. W. Weber

A Multi Objective Model for Optimization of a Green Supply Chain Network . . . . . . . . . . . . . . . . . . . . . 311 T. Paksoy, E. Özceylan, and G. W. Weber

A System Dynamics Model to Study the Importance of Infrastructure Facilities on Quality of Primary Education System in Developing Countries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 C. S. Pedamallu, L. Ozdamar, G. W. Weber, and E. Kropat

Flexibility and Project Value: Interactions and Multiple Real Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 M. Čulík

Modeling and System Optimization Optimization of Flow Coefficient for Pan Check Valve by Fluid Dynamic Analysis . . . . . . . . . . . . . . . . . 337 J. H. Lee, X. G. Song, S. M. Kang, and Y. C. Park

Advanced Targeting Cost Function Design for Evolutionary Optimization of Control of Logistic Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 R. Senkerik, I. Zelinka, D. Davendra, and Z. Oplatkova

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Adopting Problem-based Learning Model for an Electrical Engineering Curriculum . . . . . . . . . . . . . . . . 347 M. K. A. A. Khan, R. Sinnadurai, M. Amudha, I. Elamvazuthi, and P. Vasant

Evaluating the CMARS Performance for Modeling Nonlinearties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 İ. Batmaz, F. Yerlikaya-Özkurt, E. Kartal-Koç, G. Köksal, and G. W. Weber

Cluster and Scheduling On an Adjacency Cluster Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Z. V. Volkovich, G. W. Weber, and R. Avros

On the MicroCHP Scheduling Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 M. G. C. Bosman, V. Bakker, A. Molderink, J. L. Hurink, and G. J. M. Smit

Market Optimization Multi-Objective Bidding Strategy for GENCO Using Nondominated Sorting Particle Swarm Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 A. Saksinchai, C. Boonchuay, and W. Ongsakul

Optimal Congestion Management in Electricity Market Using Particle Swarm Optimization with Time Varying Acceleration Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 P. Boonyaritdachochai, C. Boonchuay, and W. Ongsakul

Introduction of SAP ERP System into a Heterogeneous Academic Community . . . . . . . . . . . . . . . . . . . . . 388 V. Mornar, K. Fertalj, and D. Kalpić

Photo Gallery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

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Preface After the successful event of the second global conference in Bali Indonesia of June 2009, the third global conference on power control and optimization PCO 2010 being held in a stunning, spectacular and dramatic city of Gold Coast, Australia. It is organized by the Middle East Technical University, the Institute of Applied Mathematics and Curtin University of Technology. PCO Global is a leading global player in the area of Power, Control and Optimization for innovative scientific and engineering activities such as organizing international conferences, journal publications and global education. It’s an official registered organization with IP0285080 in Malaysia (2008). This organization consists of highly qualified professional from all over the world in the area of Science, Engineering, Economics and others research field. PCO global strongly believe and very confident in creating a new global education to all the researchers and students from all over the world. This global organization as it belongs to a civilian society uses a public email address and common website. Global is unconditional, unconstraint, flexible, considers all nation systems, acts for a high degree of satisfaction with immediate response, and has unique registration system using a union currency. We trust that the theme of the conference “Innovation in Optimum Technology” provides emulation between the researchers in their analytical and practical results as it relates to the industrial, health, commercial, marketing and business need. We also believe that the program will provide the speaker, presenters and participants the opportunities to exchange ideas, share experience and foster solid relationship within the conference topics. The primary goal of this conference is on creating a unique opportunity for all participants across the globe to become "connected" and share knowledge, ideas and practices in global grounds. This global link will bring a significant contribution to the global body of the knowledge for human kind. The platform is the aim for all researchers, engineers, practitioners, academicians, students and industrial professionals sharing to present their research results and development activities in the area of power control and its optimization techniques. Presenters will give the optimum materials in these areas, and over the next three days we are certain to find all delegates will have stimulating discussions in both formal sessions and booths exhibition during breaks.

Scope Many engineering systems, science, financial, business and economics suffer from a problem of developing a system that can cope with variations of system or control parameters, measurements uncertainty and complex multi-objective optimization criterion. The need for a priori knowledge and the inability to learn from past experience make the design of robust, adaptive and stable systems a difficult task. Currently, researches on energy resources are found to be a great importance for future alternative replacement of oil. Computational Intelligence has been proven to have successful solution of complex optimization problems by fuzzy logic, neural Network, Evolutionary Algorithms, Genetic with line or pattern search, Particle Swam Optimization, Ant Colony Optimization and Hybrid System Optimization in variety of engineering, science, business, finance, economics, management and hybrid energy resources applications. They include system identification, parameter estimation, multi-objective optimization, robust solution, adaptive system, self organization and failure analysis. The goal of this conference is to bring together researchers working on the development of techniques and methodologies to improve the performance of power systems, energy planning and environments, controllers and robotics, operation research, and modern artificial computational intelligent techniques.

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ORGANIZING COMMITTEE

CHAIRMAN & TECHNICAL PROGRAM

CO-CHAIRMAN & INTERNATIONAL PUBLICITY

SECRETARY & GLOBAL PUBLICITY

LOGISTICS & REGISTRATION

PUBLICATIONS & TREASURER

NADER BARSOUM Department of Electrical and Computer Engineering School of Engineering, Curtin University of Technology Miri, Sarawak, Malaysia Tel: +60-8544-3821 Fax: +60-8544-3837 Email: [email protected]

GERHARD-WILHELM WEBER Institute of Applied Mathematics Middle East Technical University Ankara, Turkey Tel: +90 312 210 5652 Fax: +90 312 210 2985 Email: [email protected]

PANDIAN VASANT Department of Electrical and Electronic Engineering Institute of Technology, University Technology Petronas Bandar Seri Iskandar, Tronoh, Perak, Malaysia Tel: +60-5368-7865 Fax: +60-5365-7443 Email: [email protected]

JEFFREY FRANK WEBB Department of Mechatronics School of Engineering, Swinburne University of Technology Kuching, Sarawak, Malaysia Tel: +60-82-260636 Fax: +60-82-260777 E-mail: [email protected]

RABI W. YOUSIF Faculty of Information & Communications Technology Limkokwing University of Creative Technology Cyberjaya, Malaysia Tel: +603-8317-8408 Fax: +603-8317-8988 Email: [email protected]

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CONFERENCE COMMITTEES Steering and Publicity Committee

Cesare Planese Zari Dzalilov Musa Mammadov Adil Bagirov Sermsak Uatrongjit Cevetco Andreeski

University of Salerno, Italy University of Ballarat, Victoria, Australia University of Ballarat, Victoria, Australia University of Ballarat, Victoria, Australia Chiangmai University, Thailand University of Bitola, Macedonia

International Program Committee David A. Pelta, Ireland Janos Sebstyen, Hungary Sankar Pal, India Didier Dubois, France Xiao-Zhi, Finland John Mellor, UK Tiong Teck Chai, Malaysia Jeng-Shyang, Taiwan Praveen Jain, Canada Frede Blaabjerg, Denmark Elise del Rosario, Philippines Gianfranco Rizzo, Italy Ivan Zelinka, Czech Republic Masao Fukushima, Japan Moti Henig, Israel Christoph Meyer, Germany Christian Rehtanz, Germany Linen Gopal, Malaysia

Lianfei Zhai, Singapore Kwon Hee Lee, Korea Edisanter Lo, USA M. G. C. Bosman, Holland

Nicola Femia, Italy Nikhil Ranjan Pal, Taiwan Henry Nuttle, USA Fernando Gomide, Brazil Sergey Kryzhevich, Russia Pandian Vasant, Malaysia Liron Yedidsion, Israel Wei Xu, U.K Nikolai I. Voropai, Russia Rami Hikmat Fouad, Jordan Felix L. Chernousko, Russia Nadia Nedjah, Brazil Crina Grosan, Romania Raymond Perrault, USA Ibrahim Eksim, Turkey Kaisa Miettinen, Finland Alexander Gorin, Malaysia Celso Ribeiro, Brazil

Zakarias Situmorang, Australia Abdeen Omer, UK Irraivan Elamvazuthi, Malaysia Musa Mammadov, Australia

Igor Tyukhov, Russia Nader Barsoum, Malaysia Aleksey Nenarokomov, Russia James Hsu, Taiwan Erik Kropat, Germany Peerapol Jirapong, Thailand Oleg Repetskiy, Russia Monica Chis, Romania Weerakorn Ongsakul, Thailand Gerardo Mendez, Mexico John Patrick, UK Vincenzo Castelli, Italy A. Gunasekaran, USA Max Yen, USA A. F. Zobaa, UK Shane Xie, New Zealand Quan Min Zhu, UK Madjid Tavana, USA Gerhard-W. Weber, Turkey

Abdulrahman AlOthman, UK Vadim Strijov, Russia Mohammed Alrashidi, UK

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ACKNOWLEDGMENTS The PCO organizing committee wishes to acknowledge the financial support provided by LINDO SYSTEMS INC., IOS Press of Netherlands, HINDAWI and EUROPT. The support of American Institute of Physics AIP in publishing the PCO proceeding online is also gratefully acknowledged. The unlimited appreciation goes to the following publishers, organizations, societies, journals and companies for providing a great support in advertising PCO’2010 in their website as well as news letter, Enews and bulletin: Springer Link, InderScience, EUROPT, IAENG, Hindawi, International Society on Multiple Criteria Decision Making, IFAC Automotive Control, Neural Networks (Science Direct), EWG-MCDA, KES International, EURO, IFORS , World Scientific and INFORMS. Many thanks to the following conference organizers for advertising PCO’2010 on their websites: G-Conference NET, South African Electro Technical Council, OPTEC, German Scientific Computing Initiative, IAHE, ETH, ERDC, Electric Power Engineering related to CET, University of Kwazulu-Natal, Universitas Ma Chung, ECONFERENCE, Universiteit Gent, Power System & Power Electronics conferences, Conference Alerts, All conferences.com and Conference Service Madl. The organizing committee of PCO’2010 would like to convey their utmost sincerest thanks to the following keynote speakers for their fantastic contribution to PCO’2010 global conference. Dragica Vasileska (USA), Milorad Bojic (Serbia), Shuzhi Sam Ge (Singapore), Rainer E. Burkard (Austria), Dobrica Milovanovic (Serbia), Davor Skrlec (Croatia), and Dan Geiger (Israel). Very special thanks to the following special issues journal publications for the best selected papers: Electrical Engineering (Springer), Computers & Mathematics with Applications, International Journal of Operational Research (IJOR), International Journal of Modeling, Identification and Control (IJMIC), International Journal of Society Systems Science (IJSSS), International Journal of Renewable Energy Technology (IJRET), International Journal of Biomechatronics and Biomedical Robotics (IJBBR), International Journal of Applied Decision Sciences (IJADS), International Journal of Data Mining, Modeling and Management (IJDMMM), Journal of Process Mechanical Engineering, Proceedings of the Institution of Mechanical Engineers, Part N: Journal of Nanoengineering and Nanosystems, Int. J. of Information Systems & Social Change (IJISSC), American Journal of Engineering and Applied Sciences, International Journal of Mechanics and Materials in Design, International Journal of Theoretical and Applied Mechanics AIMETA and Fuel. The organizing committee sincerely thanks the special session chairs and stream organizers: Raymond Trever Harris, Kwon Hee Lee, Roman Senkerik, Sergey Kryzhevich, Manu P. Singh, Weerakorn Ongsakul, Gerhardwilhelm Weber, Erik Kropat, Zeev Volkovich, vadim Strijov, Inci Batmaz, Adil Baghirov, Musa Mammadov, and Zari Dzalilov Many thanks to the organizing committee and steering committee of PCO’2010 for their valuable contribution in organizing PCO’2010 at Gold Coast, Queensland, Australia The members of IPC of PCO’2010 have provided their valuable support, encouragement and helping in the process of reviewing the papers. The family of PCO’2010 conference organizers sincerely congratulates the keynote speakers, special session chairs, stream organizers and the paper presenters as well as conference delegates for their strong support and active participation in the conference activities.

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VIRTEX5 FPGA IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD ALGORITHM Muhammad H. Rais and Syed M. Qasim Citation: AIP Conference Proceedings 1239, 201 (2010); doi: 10.1063/1.3459750 View online: http://dx.doi.org/10.1063/1.3459750 View Table of Contents: http://scitation.aip.org/content/aip/proceeding/aipcp/1239?ver=pdfcov Published by the AIP Publishing

VIRTEX-5 FPGA IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD ALGORITHM Muhammad H. Rais and Syed M. Qasim King Saud University, College of Engineering, Department of Electrical Engineering, Riyadh, Saudi Arabia [email protected], [email protected] The 128 bits are organized into state matrix which is Abstract of the size of 4×4. This algorithm starts with initial In this paper, we present an implementation of transformation of state matrix followed by nine Advanced Encryption Standard (AES) cryptographic iteration of rounds. A round consists of following algorithm using state-of-the-art Virtex-5 Field four transformations: Byte Substitution (SubBytes), Programmable Gate Array (FPGA). The design is Row Shifting (ShiftRows), Mixing of columns coded in Very High Speed Integrated Circuit (MixColumns) and followed by addition of Round Hardware Description Language (VHDL). Timing Key called (AddRoundKey). From each round, a simulation is performed to verify the functionality of round key is generated from the original key through the designed circuit. Performance evaluation is also key scheduling process. The last round consists of done in terms of throughput and area. The design SubBytes, ShiftRows and AddRoundKey implemented on Virtex-5 (XC5VLX50FFG676-3) transformation. FPGA achieves a maximum throughput of 4.34 Gbps SubBytes transformation is implemented using Sutilizing a total of 399 slices. Box, which is highly computation intensive and consumes more than 75% of FPGA resources [1]. Keywords: Advanced Encryption Standard (AES), The S-Box is based on the Galois Field GF (28), and Cryptography, FPGA, Hardware Implementation, it is the only non-linear component of the AES VHDL, Virtex-5. algorithm which provides confusion capability [5]. 1. Introduction S-Box based on Galois Field GF (28) is constructed Transmission of sensitive electronic financial by performing two transformations; first taking a transactions and digital signature applications have multiplicative inverse in the Galois Field GF (28) and emphasized the need for fast and secure digital then applying a standard affine transformation over communication networks to achieve the Galois Field GF (28). requirements for secrecy, integrity, and non The S-Box is one of the most time consuming reproduction of exchanged information. process because it is required in every round [6]. Cryptography provides a method for securing and There are other fast and memory efficient algorithms authenticating the transmission of information over that have been reported for the generation of S-Box insecure channels. [1, 3, 7-9]. Dedicated embedded memory blocks To achieve high performance, it is highly available in modern FPGAs are suitable for recommended to implement the cryptographic implementing S-Boxes [1]. algorithm in hardware. Since modern security The objective of this paper is to present an efficient protocols are increasingly defined to be algorithm hardware realization of AES algorithm using stateindependent, a high degree of flexibility with respect of-the-art reconfigurable hardware (Virtex-5 FPGA). to the cryptographic algorithms is desirable. The contributions of this paper are: (1) It uses A promising solution that combines high flexibility VHDL based modular approach for the design of with the speed and physical security of application AES. (2) A more recent state-of-the-art Virtex-5 specific integrated circuits (ASICs) is the FPGA is used for implementation and this result in implementation of cryptographic algorithms on stateachieving a high throughput with zero utilization of of-the-art reconfigurable devices such as field block RAMs (BRAMs). programmable gate array (FPGA). This paper is organized into seven sections. Section Research efforts are underway to implement secure, 2 presents an overview of FPGA technology. Section fast and efficient cryptographic algorithms in 3 discusses the AES algorithm. Section 4 highlights hardware [1-3]. Vincent Rijmen and Joan Daeman on the past and current progress in the area of FPGA [4] proposed and developed a new algorithm for implementation of AES. Section 5 presents the target Advanced Encryption Standard (AES). AES consists FPGA technology. The design and FPGA of 128 block length of bits andLINE supports 128, 192 ON THE CREDIT (BELOW) TO BE INSERTED FIRST PAGE OF EACH PAPER implementation results of AES are presented in and 256 key length bits. section 6. Finally, section 7 provides conclusion. CP1239, Power Control and Optimization, 3rd Global Conference edited by N. Barsoum, G. W. Weber, and P. Vasant © 2010 American Institute of Physics 978-0-7354-0785-5/10/$30.00

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Table 1: S-Box based on Galois Field GF (28) 0 1 2 3 4 5 6 7 8 9 a b c d e f

0 63 ca b7 04 09 53 d0 51 cd 60 e0 e7 ba 70 e1 8c

1 7c 82 fd c7 83 d1 ef a3 0c 81 32 c8 78 3e f8 a1

2 77 c9 93 23 2c 00 aa 40 13 4f 3a 37 25 b5 98 89

3 7b 7d 26 c3 1a ed fb 8f ec dc 0a 6d 2e 66 11 0d

4 f2 fa 36 18 1b 20 43 92 5f 22 49 8d 1c 48 69 bf

5 6b 59 3f 96 6e fc 4d 9d 97 2a 06 d5 a6 03 d9 e6

6 6f 47 f7 05 5a b1 33 38 44 90 24 4e b4 f6 8e 42

7 c5 f0 cc 9a a0 5b 85 f5 17 88 5c a9 c6 0e 94 68

8 30 ad 34 07 52 6a 45 bc c4 46 c2 6c e8 61 9b 41

9 01 d4 a5 12 3b cb f9 b6 a7 ee d3 56 dd 35 1e 99

a 67 a2 e5 80 d6 be 02 da 7e b8 ac f4 74 57 87 2d

b 2b af f1 e2 b3 39 7f 21 3d 14 62 ea 1f b9 e9 0f

c fe 9c 71 eb 29 4a 50 10 64 de 91 65 4b 86 ce b0

d d7 a4 d8 27 e3 4c 3c ff 5d 5e 95 7a bd c1 55 54

e ab 72 31 b2 2f 58 9f f3 19 0b e4 ae 8b 1d 28 bb

f 76 c0 15 75 84 cf a8 d2 73 db 79 08 8a 9e df 16

SubBytes can be implemented either by computing the substitution or using look-up-table (LUT). ShiftRows is a cyclic left shift of the second, third and fourth row of State by one, two, and three bytes, respectively. MixColumns performs a modular polynomial multiplication on each column. During each round, AddRoundKey performs XOR with State and the round key. Round key generation (key expansion) includes S-box substitutions, word rotations, and XOR operations performed on the encryption key. Depending on the security level required for the application, AES uses different key lengths.

2. Field Programmable Gate Array (FPGA) An FPGA is a digital integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. Latest FPGAs offer math functions, embedded memories and storage elements, which makes the design of cryptography easier and provides reasonably cheap solution for designing and implementing various algorithms. Implementation of security protocols on FPGA leads to the various advantages such as low cost, availability of sophisticated design and debugging tools, ability of in-circuit reprogramability and short time to market which leads to the lower financial risk in comparison to the fully customized ASICs and potentially much higher performance than software implementations. 3. Advanced Encryption Standard AES is based on Rijndael algorithm which is a symmetric block cipher that processes fixed data of 128-bit blocks. It supports key sizes of 128, 192 and 256 bits and consists of 10, 12 or 14 iteration rounds, respectively. In this paper, we will present the 128bit version of AES with 10 rounds. Each round mixes the data with a round key, which is generated from the encryption key. The AES encryption structure is shown in Figure 1. The cipher maintains an internal, 4×4 matrix of bytes referred to as State, on which the operations are performed. Initially, State is filled with the input data block and XOR-ed with the encryption key. Regular rounds consist of operations called SubBytes, ShiftRows, MixColumns and AddRoundKey. The last round bypasses MixColumns transformation. SubBytes transformation uses 16 identical 256-byte substitution table called S-box as shown in Table 1.

Fig. 1: AES Encryption Structure 202

4. Related Work Since 2001, many implementations have been presented showing different possible design to achieve highest throughput as well as compact area [10]. For embedded applications, the focus is on the reduction of area rather than the throughput. Therefore, several implementations with small logic requirements have also been published [9]. Research efforts to achieve further acceleration in throughput along with efficient utilization of memory and other FPGA resources are also underway [1, 11-12]. Numerous efforts to implement AES using ASICs are also presented [13-14]. Gielata et al. [15] presented hardware implementation of AES-128 cipher standard on FPGA technology. Since in many network applications software implementations of cryptographic algorithms are slow and inefficient, so to solve those problems, custom architecture in reconfigurable hardware was proposed to speed up the performance and flexibility of Rijndael algorithm implementation. They have reported to achieve the maximum speed and efficiency of cipher process, and have rather proposed pipeline architecture of AES modules using simulations and synthesis of VHDL code utilizing Virtex-4 series of Xilinx FPGA. McLoone et al. [16] discussed high performance single chip FPGA implementations of the Rijndael. These designs were implemented on the Virtex-E FPGA family of devices. Gaj et al. [17] presented and analyzed the results of implementations of all five AES finalists using Xilinx FPGAs. Rady et al. [18] presented hardware implementation of optimized area for the block cipher AES-128 using FPGA. The proposed architecture was implemented in Spartan-3 XC3S400-5 chip with area utilization of 2699 slices and achieving a throughput of 10 Mbps. Pramstaller et al. [19] presented a compact implementation of AES encryption and decryption with all key lengths using a novel State representation, which solves the problem of accessing both rows and columns of the State. Saleh et al. [20] proposed new hardware architecture for AES algorithm over GF (256) and has compared it against two AES hardware structures which were iterative looping and ten rounds pipeline approach respectively. Standaert et al. [21] addressed various approaches for efficient Virtex-E FPGA implementations of the AES Algorithm. From the studies presented above, FPGAs are considered one of the important hardware platforms and integral part for the cryptographic algorithms implementation. FPGAs offer much easier and reasonably cheap solution for the implementation of cryptographic algorithm [10].

5. Target Technology The Virtex-5 device built on a 65 nm state-of-the-art copper process technology is used as the target technology for implementing AES. The Virtex-5 comprises: hard-IP system-level blocks, including Block RAM/first in first out (FIFO), second generation 25×18 DSP slices, SelectIO technology with built-in digitally-controlled impedance, ChipSync source-synchronous interface blocks, enhanced clock management tiles with integrated DCM and phase locked loop (PLL) clock generators, and advanced configuration options. In addition to the regular programmable functional elements, Virtex-5 family provides power-optimized high speed serial transceiver blocks for enhanced serial connectivity, tri-mode Ethernet MACs and high-performance PPC 440 microprocessor embedded blocks. Virtex-5 devices also use tripleoxide technology for reducing the static power consumption. Their 1.0 V core voltage and 65 nm implementation process leads also to dynamic power consumption reduction as compared to Virtex-4 devices. Virtex-5 family uses a new diagonally symmetric interconnects to minimize the number of interconnects [22]. 6. Design and Implementation Results The design of AES is done using VHDL and implemented in a Xilinx Virtex-5 XC5VLX50 (package: ffg676, speed grade: -3) FPGA using the ISE 9.2i design tool. At the start of encryption the array of input bytes is mapped to the State array as shown in Figure 2. The 128-bit block can be expressed as 16 bytes: in0, in1, in2, …, in15. Encryption process is performed on the State, and then state values are mapped to the output bytes array out0, out1, out2, …, out15.

Fig. 2: Mapping of input bytes, State array and output bytes Figure 3 shows the block diagram of AES. Figure 4 shows the FPGA layout of the AES. The part of RTL schematic of AES is shown in Figure 5. Table 2 summarizes the FPGA implementation results of AES using modular approach. It describes the selected target Xilinx FPGA device, encryption throughput achieved, timing reports and the overall device utilization. Figure 6 illustrates the timing simulation of AES. 203

presented design is evaluated based on the throughput and area. The presented design of AES uses maximum clock frequency of 339.087 MHz, which translates to throughput of 4.34 Gbps using an area of 399 slices of a Virtex-5 FPGA for block size and key size of 128 bits with zero utilization of BRAMs. Table 2: Implementation Results Encryption throughput

4.34 Gbps

Timing Report

Fig. 3: Block diagram of AES

Max. clock frequency Min. period

339.087 MHz 2.949 ns

Device Utilization Number of Slice LUTs Number of occupied Slices Number of fully used LUT-FF pairs Total equiv. gate count for design Block RAMS

1338 / 28800 4% 399 / 7200 5% 260 / 1338

19%

11926 Zero

8. Acknowledgement The authors acknowledge the assistance and the financial support provided by the Research Center in the college of Engineering, King Saud University vide their Research Grant No. 39/429. Fig. 4: FPGA layout of AES

9. References [1] A. Aziz and N. Ikram, “Memory efficient implementation of AES S-boxes on FPGA”, Journal of Circuits, Systems, and Computers, 2007, Vol. 16, No. 4, pp. 603-611,. [2] E.L-. Trejo, F.R-. Henriquez and A.D-. Perez, “An efficient FPGA implementation of CCM using AES”, in Proc. of the 8th International Conference on Information Security and Cryptology, Lecture Notes in Computer Science, Springer-Verlag, 2005, pp. 208215. [3] F.R-. Henriquez, N.A. Saqib and A.D-. Perez, “4.2 Gbits/s single chip FPGA implementation of AES algorithm”, Electronics Letters, 2003, Vol. 39, No. 15, pp. 1115-1116. [4] J. Daemen and V. Rijmen, The design of AES-The Advance Encryption Standard Springer-Verlag, 2002. [5] M.T. Tran, D.K. Bui and A.D. Duong, “Gray S-Box for Advanced Encryption Standard”, in Proc. of International Conference on Computational Intelligence and Security, 2008, Vol. 1, pp. 253-258. [6] I. Harvey, The effects of multiple algorithms in the Advanced Encryption Standard, nCipher Corporation Ltd., 2000. [7] I.A-. Badillo, C.F-. Uribe and R.C-. Para, “Design and implementation of an FPGA-based 1.452 Gbps non pipelined AES architecture”, in Proc. of the International Conference on Computational Science and its applications, Lecture Notes in Computer Science, Springer-Verlag, 2006, Vol. 3982, pp. 446455.

Fig. 5: RTL schematic of AES 7. Conclusions In this paper, a high performance and highly optimized hardware implementation of AES Algorithm has been designed and implemented on state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA device using ISE 9.2i tool. The design has been coded using modular approach by using VHDL Language. The design operates correctly as shown in the simulation result. The performance of the 204

[15] A. Gielata, P. Russek and K. Wiatr, “AES hardware implementation in FPGA for algorithm acceleration purpose”, in Proc. of International Conference on Signals and Electronic Systems, 2008, pp. 137-140. [16] M. McLoone and J.V. McCanny, “Rijndael FPGA implementations utilizing look-up tables”, Journal of VLSI Signal Processing Systems, 2003, Vol. 34, pp. 261-275. [17] K. Gaj and P. Chodowiec, “Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware”, in Proc. of Third Advanced Encryption Standard Candidate Conference, 2000. [18] A. Rady, E. ElSehely, and A.M. ElHennawy, “Design and implementation of area optimized AES algorithm on reconfigurable FPGA”, in Proc. of International conference on Microelectronics, 2007, pp. 35-38. [19] N. Pramstaller and J. Wolkerstorfer, “A universal and efficient AES co-processor for field programmable logic arrays”, in Proc. of 14th International Conference on Field-Programmable Logic and its Applications, 2004, pp. 565-574. [20] A.H. Saleh and S.S. B Ahmed, “High performance AES design using pipelining structure over GF ((24)2)”, in Proc. of IEEE International Conference on Signal Processing and Communications, 2007, pp. 716-719. [21] F.-X. Standaert, G. Rouvroy, J.-J.Quisquater and J.-D. Legat, “Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs”, in Proc. of Cryptographic hardware and embedded systems workshop, Lecture Notes in Computer Science, 2003, Vol. 2779, pp. 334-350. [22] Xilinx, Virtex-5 FPGA family overview, 2009

[8] J. Zambreno, D. Nguyen and A. Choudhary, “Exploring area/delay tradeoffs in an AES FPGA implementation”, in Proc. of International Conference on Field Programmable Logic and its Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004, Vol. 3203, pp. 575-585. [9] D.S. Kundi, S. Zaka, Q. Ain and A. Aziz, “A compact AES encryption core on Xilinx FPGA”, in Proc. of 2nd International Conference on Computer, Control and Communication, 2009, pp.1-4. [10] K. Järvinen, M. Tommiska, and J. Skyttä, “Comparative survey of high-performance cryptographic algorithm implementations on FPGAs”, in Proc. of IEE on Information Security, 2005, Vol. 152, pp. 3-12. [11] P. Chodowiec and K. Gaj, “Very compact FPGA implementation of the AES algorithm”, in Proc. of Cryptographic hardware and embedded systems workshop, 2003, pp. 319-333. [12] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, and J.D. Legat, “Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications”, in Proc. of International Conference on Information Technology: Coding and Computing, 2004, Vol. 2, pp. 583-587. [13] S. Mangard, M. Aigner and S. Dominikus, “A Highly Regular and Scalable AES Hardware Architecture”, IEEE Transaction on Computers, 2003, Vol. 52, No. 4, pp. 483-491. [14] H. Kuo and I. Verbauwhede, “Architectural Optimization for a 1.82 Gbits/sec VLSI Implementation of the AES Rijndael Algorithm”, in Proc. of Cryptographic hardware and embedded systems workshop, 2001, Vol. 2162, pp. 51-64.

Fig. 6: Timing simulation of AES

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