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[email protected] Recent Patents on Signal Processing, 2013, 3, 12-21
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Capacitive Sensor Estimation Based on Self-Configurable Reference Capacitance N. Petrellis*,1,2, C. Spathis2, K. Georgakopoulou2 and A. Birbas2 1
Computer Science and Telecommunications Dept., Technological Educational Institute of Larisa, Larisa, Greece
2
Electrical and Computer Engineering Dept., University of Patras, Patras, Greece
Received: 29 July, 2012; Revised: 30 September, 2012; Accepted: 06 November, 2012
Abstract: A number of capacitance readout systems presented in the literature and covered by recent patents are briefly described while a biosensor array readout system developed by the authors is presented in this paper. This biosensor array readout system is based on a charge sensitive amplifier that estimates accurately the difference between a selfconfigurable reference capacitance and a biosensor. In the specific implementation, the self-configurable reference capacitance is automatically configured to a value between 0 and 630pF in steps of 10pF. The configuration of the reference capacitance is controlled by a simple finite state machine that can be implemented using a simple CPLD (Complex Programmable Logic Device) such as Altera EPM7064SLC44-10. The proposed system can be used to measure an absolute biosensor capacitance of up to 640pF with a theoretical sensitivity of 2.5fF. The 2.5fF resolution can be achieved using a low cost/high accuracy 12-bit ADC (Analogue/Digital Converter) like a one that has been described by the authors in a recent patent instead of a 17-bit ADC that would be required to measure the biosensor capacitance value with the same accuracy if a constant 320pF reference capacitor had been used. For this reason, the proposed architecture leads to a lower area/power and higher accuracy implementation compared to a read out circuit that would use a fixed reference capacitance. Although the design of the proposed system was inspired by the development of a biosensor array readout system, a similar architecture can be used by any sensor application that should support a broad capacitive input range with high resolution.
Keywords: Biosensor readout, configurable reference capacitors, analogue-to-digital conversion, charge sensitive amplifier, switched capacitance interface. INTRODUCTION Biosensors often allow chemical reactions that influence their capacitance [1]. Such biosensors are used for example in Deoxyribonucleic acid (DNA) analysis as described in [2]. Although the capacitance variation is usually slow and does not require fast digitisation, a high ADC resolution is necessary to observe small capacitance changes starting from an arbitrary high initial value within a range of e.g., 1000pF. The DNA used in these sensors can be retrieved from tissues, blood, saliva etc. Genotype or expression analysis can be based on genomic or complementary DNA respectively. The single stranded DNA binds to a complementary stranded DNA on a biosensor array. Reactions of this type are often called “hybridisation” and a biosensor capacitance change occurs as a result. A hybridisation requires often several minutes or even hours to complete. Although, the monitoring of each individual biosensor is slow, a large number of biosensors (e.g., 64 or 256) may have to be read at regular time intervals. It is essential in this case to achieve a sensitivity of a few fF although the initial capacitance of a biosensor may start from an arbitrary high value (up to 1nF). The target in *Address correspondence to this author at the Computer Science and Telecommunications Dept., TEI of Larisa, TEI Campus, Larisa 41110, Greece; Tel: +302410684542; Fax: +302410684573; E-mail:
[email protected] /13 $100.00+.00
such applications is to accurately monitor how the biosensor capacitance changes rather than recording its absolute capacitance values. Capacitive sensors are also used in several other applications like humidity [3] and pressure [4] measurement, gyroscopes [5] etc. The most popular method for capacitance measurement is the use of Charge Sensitive Amplifiers (CSA) [2] or Switched Capacitance Interface (SCI) [6] or Capacitance to Voltage Amplifier [7]. In the Charge Sensitive Amplifiers a voltage pulse is applied to the capacitor under test and the charge stored there is distributed to a reference capacitor when the input pulse ends. An operational amplifier is used to integrate the voltage accross the reference capacitor and the output of this amplifier may be either a sawtooth curve or a voltage level. In the first case a low threshold comparator may convert the sawtooth curve to a digital pulse whose duration is proportional to the measured capacitance. A counter enabled by the output of the comparator may provide a digital representation of the measured capacitance [2]. If the CSA output is a voltage level, then an ADC like Sigma-Delta, Successive Approximation, Pipelined etc, with appropriate resolution may convert this voltage indication to a digital representation of the capacitance. Switched Capacitance Interface circuits are actually CSAs that use several switches to charge/discharge the reference and the measured capacitor rather than accepting a voltage pulse at their input. In [8] a © 2013 Bentham Science Publishers
Capacitive Sensor Estimation Based on Self-Configurable Reference Capacitance
feedback path connects the output of a CSA or SCI stage to the parasitic capacitances minimizing their effect in linearity and accuracy. Differential Capacitance (i.e., the difference between two unknown capacitors) can be measured by circuits like the one presented in [9] or [10]. In non-differential capacitance applications the difference between a reference and the unknown capacitor is estimated [6]. The closer the reference capacitor to the unknown one is, the higher the accuracy that can be achieved. For this reason, a configurable reference capacitor has been proposed in [11] where 6 input sensors are multiplexed and a combination of 3 capacitors forms a reference value. The first author of [11] has also presented a hummidity and temperature sensor control method based on switching elements that produce pulse series that can be integrated in order to estimate the sensor values [12]. The output of the employed CSA is digitally processed. Configurable on-chip reference capacitor has also been used in [6]. The reference capacitance can be configured in the range of 250fF to 15pF in steps of 250fF. In a recent patent [13] an appropriate readout system for strain and accelerometer capacitive sensors used in MicroElectro-Mechanical Systems (MEMS) is presented. In this approach a specific number of actuator voltage pulses with the same polarity are applied to the sensors and integrated by an SCI circuit that requires a number of switching clock signals (for the Integrate, Reset, Sample stage) leading to a final voltage level that is measured by an ADC. Using multiple actuator voltage pulses instead of a single one and integrating the measured capacitor output, compensates potential noise problems (it can be viewed as a kind of averaging) and adjusts the final output voltage to a desired range eliminating the need of a gain control mechanism. Moreover, the approach presented in [13] does not need actuator voltage pulses with alternating polarities to be applied in order to avoid an asymmetric positioning of the sensor. These are the advantages of the approach presented in [13] compared to a similar read out system presented in [14]. Nevertheless, the accumulation of multiple measurements through the integration performed by a SCI circuit like the one presented in [12] increases the latency of a single sensor read. Using the suggested clock frequency of 10.8kHz the strain sensors can be read with a 20Hz rate and a ±1% error. A very accurate capacitance measurement is performed in [15] based on a delta-sigma converter and a high precision calibration stage. The specific system described in this paper can cover a very broad capacitance range of 640pF with an accuracy of up to 2.44fF. It will be made clear however, that different ranges and resolutions can also be supported based on the proposed architecture. None of the approaches referenced above can cover such a wide range with this accuracy. Moreover, the system can be implemented using low die area mainly due to the small size of the used ADC. The system described in this paper has been partially implemented and evaluated for the read-out of sensors like the ones described in [1]. More specifically, an address decoder that selects one of 64 biosensors has been implemented along with a CSA like the one presented in [6] or [11] to the input of which the selected biosensor is connected. These modules have been implemented using TSCM90nm CMOS technology. A
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digitally implemented Finite State Machine (FSM) was described in VHSIC Hardware Description Language (VHDL) and evaluated seperately using an extremely low cost Altera EPM7064SLC44-10 CPLD that can connect to the CSA, an appropriate combination of external reference capacitors that can provide a reference value between 0 and 630pF in steps of 10pF. Of course the choice of the specifc hardware description language and CPLD component is not restrictive. They were employed just to demonstrate the low complexity of an FSM like the one required by the proposed system. The CSA output can be measured using an appropriate ADC according to the application sensitivity specifications. The authors have proposed a low area/power ADC with a configurable resolution of 4 to 12 bits that could have been employed [16,17]. The CSA used and its simulated output is presented in Section 2. The biosensor array readout system and the implementation of the FSM used for the self-configuration of the reference capacitance are presented in Section 3. Finally, the readout speed and the resolution that can be achieved are discussed in Section 4 along with a comparison with the referenced approaches that provide information about the input capacitance range and the accuracy that they achieve. CHARGE SENSITIVE AMPLIFIER The simplest implementation of the CSA front end appears in Fig. (1). The unknown capacitance Cx is compared to the parallel reference capacitor Cref and the output of the integrator is given by equation (1) when the integration is complete [6].
Vout = VA
C x Cref
(1)
Cf
Rdis reset Cf
-
Cx
Φ
Cref
+
Φ GND or Φ~ V ref reset
CSA Output Vout VA
Fig. (1). Charge Sensitive Amplifier.
The voltage VA is the signal amplitude. The reset signal has the same period with or ~ but lower duty cycle and is used to discharge Cf when is high. Appropriate shifting of the output voltage can be performed if the non-inverting input of the operational amplifier of Fig. (1) is connected to a reference voltage Vref instead of ground. In this case, the output Vout is incremented by Vref. Using a voltage indication that is linearly proportional to the capacitance under test is very important. In [2], no
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reference capacitor Cref is used and the feedback one is discharged through a resistance Rdis that is used in place of the reset switch of Fig. (1). In this case, the varying current that discharges a feedback capacitor like Cf of Fig. (1) leads to an integrator output of the form:
where Q is the charge integrated by Cf during each pulse period and =CfRdis. The authors in [2] use a special technique with schottky diodes to keep the discharge current stable and make the CSA output linear for broader capacitive input ranges. In the present work, the approach of Fig. (1) is used due to its robustness and simplicity since no special components like schottky diodes are needed. The integrator is implemented by the operational amplifier presented in [11] that does not require additional bias voltages. In Fig. (2), the shape of the Fig. (1) CSA circuit signals is shown. A parametric post-layout simulation has been performed for the CSA output by the Spectre simulator in Cadence environment for Cx values between 150pF and 160pF in Fig. (3). The linearity behavior of the CSA circuit in this range has been experimentally verified using external commercial capacitors of 150, 156 and 160pF. A 150pF value has been chosen for the capacitors Cref and Cf of the CSA circuit shown in Fig. (1). A similar parametric post-layout simulation for Cx values between 500pF and 510pF is shown in Fig. (4). The linearity behavior of the CSA circuit in this case has also been experimentally verified using combinations of commercial capacitors and a 500pF value has been chosen for the capacitors Cref and Cf. The signals and ~ have a period of 200usec but it is obvious from Figs. (3, 4) that a significantly shorter period could have been used since the critical transient interval at the beginning of pulse is quite shorter. More specifically a 10usec period is adequate for these signals. The duty cycle of (or ~) and the reset signal is 50% and 25% respectively. The output of the CSA for a capacitance difference between 0 and +10pF is quite linear as can be seen by Figs. (3, 4). Linearity issues will be discussed in more detail in Section 4. The appropriate time to sample the CSA output is when is high. At this time interval an ADC with appropriate resolution can convert the analog CSA output to a digital representation of the measured capacitance.
CSA Signals
CSA Output
Reset
Fig. (2). The shape of the CSA Signals.
Φ
Φ~
150pF 370
CSA Output (mV)
(2)
380 151pF
360
152pF
350
153pF 154pF
340
155pF
330
156pF
320
157pF
310
158pF 159pF
300
0
50
100
150
200
160pF
Time (us)
Fig. (3). CSA Output with Cx between 150pF and 160pF (Cf=Cref=150pF).
335 500pF
330
501pF
325 CSA Output (mV)
Vout
Q t / = e Cf
390
502pF
503pF
320
504pF 315
505pF 506pF
310
507pF 305 508pF 300
509pF 0
50
100
150
200
510pF
Time (us)
Fig. (4). CSA Output with Cx between 500pF and 510pF (Cf=Cref=500pF).
READOUT SYSTEM ARCHITECTURE The architecture of the biosensor array readout system proposed in this paper is presented in Fig. (5). The biosensor array consists of a number of biosensors (64 in the specific case) that share a common pin. This common pin is connected to the CSA inverting input. The specific biosensor that has to be read is selected using an m to 2m decoder (m=6 in the specific implementation). The signal STB initiates a specific read cycle from the biosensor that is addressed using the signals A0..Am-1. The signals and ~ can be generated from the external input signal STB. The signal is applied to the selected biosensor through the m to 2m address decoder. The common pin of the biosensors is connected to the inverting input of the CSA integrator as well as the reference capacitor as was shown in Fig. (1). The reference capacitor is formed by a combination of at least 9 external capacitors (some redundant capacitors are also used to handle capacitor tolerance as will be explained in the following paragraphs).
Capacitive Sensor Estimation Based on Self-Configurable Reference Capacitance
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Biosensor Array
BSY_NRDY DDn-1 … DD0
Biosensor Array Readout Circuit
… LATCH
Α0 Α1 .. Αm-1
mx2m Decoder
…
n-bit ADC Φ
CSA
FSM
Internal Clock Generator
CMP NEG
POS
STB
CLK
CMP Φ~
ENC
0
IN
(P)RESETC
CLK SHIFTER C
SC3 SC2 … SC0
CCCs … CCCs
ENB
0
(P)RESETB
IN
CLK SHIFTER B
SB3 SB2 … SB0
ENA
0
(P)RESETA
IN
CLK SHIFTER A
SA3 SA2
…
SA0
… …
CBCs .. CBCs
…
CACs .. CACs
ENCODER DB0 DB1
… DBk-1
Fig. (5). The architecture of the Biosensor Readout System with Self-Configurable Capacitance Reference.
These capacitors can also be incorporated in the same chip as the readout system but their capacitance would have to be much smaller leading to a limited capacitance input range of the whole system. All of these external capacitors share a common pin that is connected to the common pin of the biosensors and the inverting input of the CSA integrator. The other pin of the reference capacitors is connected through a switch to the ~ signal that is also generated by the input signal STB through an inverter. The reference capacitors and their switches are classified in 3 groups and the parallel connection of the capacitors within a group is controlled by a corresponding shift register (SHIFTER A, B and C). The operation of these shift registers is controlled in turn by a simple Finite State Machine (FSM). Before we describe in detail the FSM, the algorithm for the reference capacitor value formation should be explained. Assuming that an input range of 640pF is adequate, the
reference capacitor value can be expressed in a radix-4 numerical system representation with 3 digits as:
Cref = (b2 4 2 + b1 41 + b0 4 0 )10 pF
(3)
where the digits b2, b1 and b0 can be 0, 1, 2 or 3 and denote how many capacitors of 160pF, 40pF and 10pF respectively have to be connected in parallel. Notice that each external capacitor value is an exponential value of 4 multiplied by 10pF in order to create all the capacitance reference combinations between 0 and 630pF with steps of 10pF. In order to implement any of these reference capacitor combinations, three sets (A, B and C) of 3 capacitors each, is required. The first set (A) has 3 identical 10pF capacitors. The second set (B) has 3 identical 40pF and the third set (C) has 3 identical 160pF capacitors. Higher number of potential combinations can be achieved if more than 3 sets are defined or if the 3 digits in equation (3) had a potentially different radix:
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Cref = (b2 CC + b1C B + b0 C A )Cs
Petrellis et al.
(4)
It should be noticed, that in the present design, radix-4 was used in order to cover the specific capacitance range with the simplest reference capacitance bank and interconnection scheme. A different numerical system may have been selected if a different range had to be covered. The use of external commercial capacitors has some significant drawbacks. First of all, there are several capacitance values that are not commercially available in a single component and have to be formed by a combination of capacitors connected in parallel or even in series. Then, each commercial component has a tolerance from its typical value. Although expensive components may have a small tolerance (e.g., 1%), this tolerance has to be taken into consideration. Parasitic capacitances affect the typical capacitor values too. More accurate capacitor ratios could have been achieved if the reference capacitors were implemented on-chip but their absolute values in this case would have to be quite smaller significantly limiting the capacitance input range of the whole system. The tolerance of the external reference capacitors is handled in this work by using one redundant capacitor in each one of the A, B and C sets mentioned above. Although the reference capacitance is still formed in a radix-4 numerical system as described by equation (3), the digits b2, b1 and b0 can now have 5 values: 0-4 allowing the connection of up to 4 identical capacitors in parallel. Using this extended radix-4 notation a specific capacitance value may have more than one representation. For example, the capacitance of 160pF can be implemented by using a single 160pF capacitor (b2=1, b1=0 and b0=0) or by connecting in parallel four 40pF capacitors (b2=0, b1=4 and b0=0), or by connecting in parallel three 40pF and four 10pF capacitors (b2=0, b1=3 and b0=4). This redundancy reassures that there will be no gaps due to component tolerances in the supported input capacitance range. The CSA output is monitored by a pair of comparators (CMP) that decide whether the measured capacitance is higher or lower than the current reference one (indications POS and NEG respectively of Fig. 5). These indications are used by the FSM that controls the 3 shift registers (A, B and C). The operation of each one of these shift registers is depicted in Fig. (6). Each shift register is a Serial In, Parallel Out (SIPO) register with a Reset, Preset, Enable and Clock input. The bit
EN PRESET
0
that is shifted in, is inserted by the IN pin and the outputs of the shifter are available at the S3-S0 pins. During the reference capacitor self-configuration phase, all the outputs of a shift register have to be initially reset (disconnecting all the attached capacitors), then at a specific time all of them have to be preset to 1 (connecting all the attached capacitors in parallel) and finally some capacitors have to be gradually disconnected by shifting in, one or more 0’s as shown in Fig. (6). The algorithm that can exploit such a shifting operation in order to perform the appropriate self-configuration is the following: 1)
Connect all CC capacitors (Cref=4CCCS)
2)
Repeat disconnecting CC capacitors until Cref=cCCCS< Cx c=4, 3, 2, 1, 0
3)
Connect all CB capacitors (Cref=cCCCS+4CBCS)
4)
Repeat disconnecting CB capacitors until Cref=cCCCS+ bCBCS
