CB16CE Introduction Logic Table Design Entry Method For ESE171 ...
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CB16CE Introduction Logic Table Design Entry Method For ESE171 ...
CB16CE. Macro: 16-Bit Cascadable Binary Counter with Clock Enable and
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For ESE171 Lab Report Use ONLY (From Xilinx ISE 10.1 Help)
CB16CE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
Introduction This design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Create larger counters by connecting the CEO output of each stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input or use the TC output if it does not. This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to activeHigh but can be inverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table Inputs CLR
Outputs
CE
C
Qz-Q0
TC
CEO
1
X
X
0
0
0
0
0
X
No change
No change
0
0
1
Inc
TC
CEO
z = bit width - 1 TC = Qz•Q(z-1)•Q(z-2)•...•Q0 CEO = TC•CE
