Cell-aware Production Test Results from a 32nm Notebook Processor

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and that GE tests [9] are too expensive for production tests. First CA production test ... cells and a notebook processor processed in a 32nm technology were ...
Cell-aware Production Test Results from a 350nm Automotive Design F. Hapke1, M. Hustava2, J. Schloeffel1, V. Bucek2, W. Redemund1, P. Vyncke3, A. Fast1, R. Pospisil2, J. Rajski4 1

Mentor Graphics Hamburg Germany

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ON Semiconductor Brno Czech Republic

Abstract This paper describes an approach to improve the overall defect coverage for a CMOS-based automotive design. We present results from a defect-oriented cellaware (CA) library characterization and patterngeneration flow and its application to 216 library cells and a high quality automotive design processed in a 350nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results achieved after testing 500,000 parts. We also present evaluation results from cell-aware only failing parts.

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Introduction

Physical defects like shorts and opens may occur during any step of the fabrication process. Well-known fault models like stuck-at (SA) [1], transition (TR) [2], bridge (BR) [3], N-detect (ND) [5], gate-exhaustive (GE) [4] and embedded-multi-detect (EMD) [6], as well as timing-aware and layout-aware fault models on interconnect lines, have been presented and used in production for many years. These fault models are insufficient for today’s technologies that require low defect rates. In our previous work, in which we introduced the cell-aware (CA) methodology [7], [8], [11], we showed that the classical SA, TR and ND approaches do not target all real defects in library cells, and that GE tests [9] are too expensive for production tests. First CA production test results for a 45nm process were presented in [10], followed by results from a 32nm process in [11] and [12]. In this paper we focus on a full application of the CA methodology, which includes at-speed CA tests for bridges and opens for a 350nm automotive technology. Also included are production test results from 500,000 tested ICs of this ON Semiconductor automotive design.

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Previous Work

The problem of defects not covered by standard fault models and techniques has been the objective of numerous publications. Several approaches have been published so far to reduce defect rates. Many focused on defects on interconnect wires outside of library cells.

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ON Semiconductor Oudenaarde Belgium

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Mentor Graphics Wilsonville, Oregon USA

In [7] we presented a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used by the ATPG was enhanced to directly target layout-based intra-cell bridge defects. In contrast to previous techniques, the new approach targeted the actual root causes of so far undetected intra-cell defects. In [8] we extended the cell-aware methodology by targeting open defects as well. Cell-internal open defects have been evaluated with respect to their detectability and effectiveness in relation to transition test patterns. It was shown that the quality of transition patterns can be improved significantly by explicitly targeting cell-internal open defects with CA patterns. In [9] a comparison between CA and GE test sets for industrial designs was published showing the advantages of the cell-aware approach. In [10] we presented a method for analyzing smalldelay defects caused by cell-internal bridges and opens. High-volume production results from testing more than half a million ICs showed that slow-speed CA patterns are a very effective way to detect otherwise undetected cell-internal bridge defects. An overview of the latest state-of-the-art of the cellaware methodology was given in [12]. The tutorial covered the whole cell-aware library characterization flow consisting of a layout extraction step, an analog fault simulation step of all cell-internal bridges and opens and the cell-aware synthesis step to create the new cell-aware ATPG library views. These finally can be used in a normal chip design flow to generate production test patterns, which have a significantly higher quality than state-of-the-art patterns. In [11] results from a CA library characterization and pattern-generation flow and its application to 1,900 cells and a notebook processor processed in a 32nm technology were presented achieving significant reduction of DPPM rates. The CA flow enabled the detection of cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. Highvolume production test results from the 32nm notebook processor were presented together with cell-internal diagnosis and physical failure analysis results from one failing part.

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Validation Flow for a 350nm Design



The investigation as shown in Figure 1 incorporates the comparison of the cell-aware (CA) with the traditional SA model and the TR fault model for an industrial design in a 350nm technology.



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The green line is the defect coverage rate of the testable cell-internal defects (always at 100%) for CA slow-speed and at-speed patterns. The blue line is the defect coverage rate for bridges and opens achieved with state-of-the-art SA patterns. The red line is the defect coverage rate for bridges and opens achieved with state-of-the-art TR patterns.



Figure 1: Validation Flow For this the evaluation flow starts with the generation of state-of-the-art SA and TR patterns. The second step in the flow is the verification of the SA and TR patterns with respect to the CA fault model. This evaluation is accomplished by a fault-simulation of the SA and TR patterns considering the cell-internal defects. The third step is the generation of the CA patterns which do achieve the highest possible defect coverage also detecting all cell-internal defects. As described in [12] a library characterization is performed in advance once per technology node to create the needed CA view for each cell of the standard library. The results of this library characterization for the 350nm used in this design are presented in the following two sub-chapters.

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 As can be seen, for about 25% of the cells, the defect coverage of SA patterns is less than 100%; some cells just reach defect coverage of 70%. The cell types with the worst defect coverage figure from SA patterns are ANDOR, MUX21 and XOR cells. The situation is worse for TR patterns: only about 18% of the cells reach 100% defect coverage. In fact, many cells (about 30) have defect coverage of less than 50%, while some cells reach just 20%. The cells with the lowest defect coverage are simple gates with 5 to 8 inputs, multiplexer and ANDOR cells. We also included buffers and inverters, therefore the graph in Figure 2 shows just a green line at the right side from cell number 180 to 215, i.e. nothing can be gained for buffers and inverters.

3.2

The Cell Pattern Graph

This section presents results with respect to the number of test patterns generated on each 350nm library cell in isolation without instantiating the cell in a design. Figure 3 shows the number of test patterns generated for each library cell.

The Defect Coverage Graph

In total 216 cells from a 350nm technology has been analyzed. Figure 2 shows the deficiency of the state-ofthe-art SA and TR patterns to detect all testable cellinternal defects calculated by the CA flow.

Figure 3: Pattern Graph on Standard Cell Level

Figure 2: Defect Coverage Graph The horizontal axis represents the library cells numbered from 0 to 215. The vertical axis represents three defect coverage rates in percent:

The horizontal axis represents the individual library cells (from cell 0 to cell 215). The vertical axis represents the number of patterns for each cell. The cells are sorted in descending order of their pattern count from left to right. The blue line is the sum of SA and TR patterns for each cell, and the green line is the sum of CA slow-speed (1tf) and at-speed patterns (2tf). The 216 analyzed cells include buffers and inverters and as such at the right side of the pattern graph the

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cells with 4 patterns can be seen. In this case the number of SA+TR patterns is equal to the number of CA patterns so that the blue line is hidden and only a green line is visible. The left side of the pattern graph shows simple gates like AND-, NAND-, OR- and NOR-type of cells with 5 to 8 inputs. The cells with 25 CA patterns at the left side of the x-axis are AND, NAND, OR and NOR cells with eight inputs. The peak in the graph at the x-axis position around 40 is from ANDOR-type of cells with 4 and 3 inputs. The pattern graph in Figure 3 clearly shows that stateof-the-art SA and TR patterns are insufficient to detect all detectable cell-internal bridges and cell-internal opens. Nearly all cells require more patterns to detect all cell-internal defects and the CA ATPG is forced to generate those patterns.

3.3

Defect Coverage Gain

For this analysis we performed the CA validation flow as described in Figure 1 followed by various fault simulations and ATPG runs with those generated CA library views and the selected 350nm automotive design (shown in Figure 9). By fault-simulating the existing SA and TR patterns with the CA fault simulator the defect coverage of SA and TR patterns have been obtained. Based on that, a CA slow-speed and at-speed test pattern set was created to increase the defect coverage compared to SA and TR patterns.

Figure 4: Slow-speed Defect Coverage Gain An overview of the defect coverage gain by cell type achieved with the slow-speed CA patterns is given in Figure 4. The blue line shows the number of additional CA-only detected defects, the red line the relative coverage gain - both related to the cell type listed on the x-axis. It can be seen from the graph that the ANDOR (AO) cell types contribute most with 154 additional detected defects in this design. The relative coverage gain for the AO cell type is just 0.19%. The second biggest impact to the additional detected defects with 19 defects is from the simple 2:1 multiplexer (mux) cell type. The relative coverage gain for the mux cell type is 0.32%. The biggest relative coverage gain (about 23%) is achieved from a NOR with 8 inputs, i.e. from the nr8 cell type. However, this high relative coverage gain of

about 23% has a medium impact on the overall coverage gain or additional detected defects in this design because the nr8 cell is just instantiated very few times in this design and as such the total coverage gain or the total additional detected defects is only weakly impacted by cell nr8. An overview of the defect coverage gain by cell type achieved with the at-speed CA patterns is given in Figure 5.

Figure 5: At-speed Defect Coverage Gain The blue line shows the number of CA-only detected defects per cell type, the red line the relative defect coverage gain, again with respect to the related cell type. It can be taken from the graph that the ANDOR (AO) cell types contribute most to the additional detected defects (7070) in this design. The relative coverage gain for the AO cell type is 12.7%. The second biggest impact to the additional detected defects (933) is from the simple 2:1 multiplexer (mux) cell type. The relative coverage gain for the mux cell type is 16.2%. The biggest coverage gain (about 40%) is achieved from a NAND with 7 inputs, i.e. from the nd7 cell type. However, this high relative coverage gain of about 40% has a very small impact on the overall coverage gain or additional detected defects in this design because the nd7 cell is just instantiated very few times in this design and as such the total coverage gain or the total additional detected defects is impacted very little from the nd7 cell.

Figure 6: CA-only Detected Defects The total number of additional CA-only detected defects from the slow- and at-speed CA patterns is shown in Figure 6. Clearly the ANDOR-type of cells

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contributes the most with 7223 additional detected defects. The mux cells contribute with 952 defects, nd3 adds 651 defects, the NOR with two inputs (nr2) adds 570 defects and the NAND with two inputs (nd2) 540 defects. All other cell-types shown range between 400 and 200 defects.

3.4

Cell-aware Detections in AO Cells

To further investigate the large CA only detected defects in ANDOR (AO) cells types, we selected the AOP4 cell. This cell is an AO cell with 4 inputs. The state-of-the-art test pattern count for this cell is 10, but CA requires 23 patterns. Figure 7 shows the layout of this AO4P cell and one of the defects (named D30) that is not guaranteed to be detected with state-of-the-art test patterns.

detect this bridge defect safely, there is just one test pattern in the total of the 16 possible input patterns that will detect that bridge. This input pattern is A=1, B=0, C=0 and D=0. A state-of-the-art SA test pattern will typically not contain this input pattern. The CA ATPG is forced deterministically to generate the required pattern to safely detect the bridge defect D30.

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Production Test of a 350nm Design

For evaluating the effectiveness of the CA slow-speed and at-speed patterns in relation to the normal production test, we chose a 350nm automotive design code-named “ULAA”, see Figure 9.

Figure 9: ON Semiconductor 350nm Automotive Design Figure 7: Layout of the AO4P Cells Figure 7 shows a bridge defect D30 (shown in red) on metal1 between the cell input “B” and a cell internal net “3”. It is obvious that this bridge defect is likely to occur during the production process. Figure 8 depicts the same bridge defect D30 mapped back to the transistor schematic of the cell.

This design integrates high performing power efficient analog and digital parts. Analog implements the LIN physical layer and analog front end interfacing the external sensor. Digital implements the LIN data link layer, LIN application layer and DSP logic responsible for processing of ADC bit stream generated by analog front-end. The design also includes complex DFT logic to achieve the top class analog and digital testability.

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Experimental Test Flow

To investigate the effectiveness of the CA patterns in relation to the normal production test patterns (consisting of IddQ, SA, layout based Bridge and TR patterns), we added the experimental CA patterns to the test program and changed the test flow to log unique fails of the CA patterns as shown in Figure 10.

Figure 8: Transistor Schematic of the AO4P Cell The above figure shows the bridge defect D30 between the cell input “B” and the cell internal net “3”. To

Figure 10: Production Test Flow

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The production test consists of a slow-speed IddQ test, followed by slow-speed SA & Bridge, and an at-speed TR test. The experimental patterns consist of a CA slow-speed (CA-1) as well as a CA at-speed test (CA2). All experimental patterns were in data-collection mode, otherwise known as “continue on fail”. The production patterns have been executed in “stop on fail” mode. This means that any fail detected by the CA patterns completely passed the normal production tests. The number of production and experimental test vectors applied to the chosen 350nm automotive chip is shown in Figure 11.

Figure 12: Projection of Achievable PPM Reduction This data shows that the CA patterns detect a total of 44 rejected parts that state-of-the-art SA, Bridge and TR patterns do not detect.

Figure 11: Number of Test Vectors As can be seen, the quantity of the CA-1 slow-speed test vectors (47k) is very small compared to existing slow-speed production (1073k) vectors which is a normal SA test followed by a layout aware Bridge test. The sum of SA & Bridge test is in total 1073k vectors and both tests were performed at low-speed. The quantity of the CA-2 at-speed test vectors is 847k. This means the test vector count increase is a total of 894k vectors; the existing production test has 1527k test vectors, leading finally to an overall increase of 59% for the test vector count. The CA-1 slow-speed patterns are top-off patterns to the existing SA & Bridge patterns. The CA-2 at-speed patterns are top-off patterns to the existing TR at-speed patterns. The final goal of CA patterns is to obsolete the SA and TR patterns because the CA patterns are by definition a superset of SA and TR patterns. This would then reduce the test vector count further, which requires additional experiments - running the CA patterns in parallel with SA + TR at-speed patterns to prove that CA patterns are capable of detecting all rejects the SA + TR at-speed patterns detected.

4.2

Wafer Sort Results

After enhancing the production test program as shown in Figure 10, we applied the normal production patterns and experimental CA patterns during wafer sort for the 350nm automotive design. Figure 12 summarizes the reject count and their projection to the measured defect rate reduction in parts per million (PPM) after testing 500,000 ICs.

The slow-speed CA patterns detect a total of 4 parts. These reject counts can be directly correlated with measured PPM rates i.e., the slow-speed CA patterns result in a measured defect rate reduction of 8 PPM. The at-speed CA patterns detect a total of 40 parts resulting in a measured defect rate reduction of 80 PPM. The Venn diagram also shows the overlap between the two CA tests which was 0 in this experiment. In total, the CA tests rejected extra parts missed by state-of-theart tests for this 350nm design at a measured rate of 88 PPM.

4.3

Validation of Test Results

The 44 failing parts have been further analyzed. The CA-2 at-speed patterns run with the same timing as the TR at-speed patterns. The rejects of CA-2 at-speed patterns are test escapes of TR at-speed testing. The validation of the test results (retesting of the rejected parts using the standard and CA flow) confirmed that all 44 rejects are permanent fails. The 4 parts that failed the CA-1 slow-speed patterns represent the slow-speed/static defects which are equivalent to 8 PPM after testing of 500K devices. The other 40 failing parts are parametric outliers based on the post-layout STA. In normal mode the top operational frequency of digital is 10MHz±3% (tolerance of on-chip RCOSC over the temperature range). Just a small portion of the design (less than 10%) is running at the top frequency, the rest of digital is running on divided clock (2MHz resp. 500kHz). Digital is synthesized at 15MHz WC (150°C & 2.25V) corner to guarantee enough timing margin for safety critical automotive applications. From post-layout STA,

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following are the worst setup time timing slacks (BC corner: -40°C & 3.63V):  

BC corner WC corner

32.08ns 57.5ns

The analysis confirms that the CA method detects various otherwise undetected defects or parametric timing outliers. For the selected 350nm automotive design an additional 44 parts were rejected on a total of 524,000 parts.

Initially the high limit (HTL) for TR at-speed resp. CA2 at-speed was set to 63ns. During test program characterization the limits for TR at-speed resp. CA-2 at-speed were changed on final limits running in production. TR at-speed and CA-2 at-speed patterns are running only at cold insertion (test time reduction), as the experiments in production showed that screening of atspeed defects at hot does not further improve the test quality. From the 80 PPM detected by CA-2 at-speed patterns (it is valid also for TR at-speed), the majority of the devices are fully functional at-speed (for both WC and BC corner). This is achieved due to a visible over constraining during the synthesis and P&R. With introduction of the novel pattern sets (TR at-speed resp. CA-2 at-speed) for mature technologies (ONS mixedsignal 350nm), we finally have a method to screen the delay defects in digital and we do not need to rely on over constraining. This will allow further optimization of power dissipation and the area of the digital.

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Based on this result, we can state that the CA method detects various otherwise undetected defects (mainly parametrical defects) and does improve overall test quality. This is also valid for processes which are mature and have low PPM rates.

[6] J. Geuzebroek, E.J. Marinissen, A. Majhi, A. Glowatz, and F.

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Future Work

We will apply the CA method on more designs and other technologies. Further investigation will be done on the CA identified parametric outliers. We will perform layout-aware and cell-internal diagnosis runs on failing CA parts. Physical diagnosis analysis will be done for selected failing ICs. Introduction of CA patterns is increasing the test time and - what is even more serious - the requirements on tester memory are also increased proportionally. For complex designs the application of HW compression is necessary once the CA patterns are introduced. Our future work will be integrating the CA flow with HW compression and further analyzing the benefits on test quality and test cost.

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Conclusion

We presented library characterization of 216 cells from a 350nm technology and CA production test results from a 350nm ON Semiconductor automotive design.

Acknowledgments

The authors thank Andreas Glowatz, Mark Kassab and Kan Thapar for their assistance, valuable discussion, implementations, and insight during this project.

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