Cell

SA 21.2: 1M-Cell 6b/Cell Analog Flash Memory for Digital Storage P. L. Rolandi, R. Canegallo, E. Chioffi, D. Gerna, G. Guaitini, C. Issartel, F. Lhermet, M. Pasotti, A. Kramer SGS-Thomson Microelectronics, Agrate Brianza (MI), Italy This standard flash-EEPROM contains 1M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6Mb memory with 257Mb/cm2 array density. High-density digital storage techniques for floating gate devices (>8 levels) require the use of feedback in the programming loop (pulse and verify method) and substantially different reading and programming circuitry from conventional memory devices. Several prototypes have been previously reported that store 4 levels per device (2b) while maintaining industry standard retention times of roughly 10 years [1]. The goal of the approach reported here is to demonstrate higher densities in the range of 4-6b, achieved at the cost of reduced retention times. Devices with these characteristics present an attractive low-cost alternative for storage of digital data that is typically kept for only a limited period of time and does not need high throughput, such as personal data like digital still images and recorded speech. Alternative analog storage techniques are reported, but because these memory devices do a direct analog storage (analog I/O), rather than storage of a multi-level digital value, they are incompatible with digital compression techniques and result in reduced system-level storage density [2]. Analog programming and reading techniques have been used on unconventional floating gate devices for specialized analog computing applications [3]. This fully-digital multi-level memory is based on similar circuit techniques applied to standard memory devices and combined with predictive programming algorithms that greatly increase both storage density and programming speed. The memory is composed of conventional Flash array core divided into two 500k sectors, a word-line and a bit-line decoder, 8 digital sense amplifiers plus an analog sense amplifier with 8 channel analog multiplexer (Figure 1). Analog circuits are necessary for high-density storage of digital data based on analog threshold reading and pulse sequences providing reliably predictable programming curves. Analog programming places special constraints on the precision of the erase operation. Erasing uses standard fast digital sense amplifiers with 2 voltage references to verify that all erased thresholds are within a predetermined range. The analog sense amplifier is a close-loop circuit that directly reads the stored threshold of the device under a particular bias condition (Figure 2). This provides read precision of about 2.5mV in less than 5µs; better than 10b in analog. The precision of the read threshold is fundamental for the multi-level programming used, because precision beyond that of the programming precision target, enables algorithms containing a mixture of feedback and feedforward programming techniques. Figure 3 shows the voltage gate of a cell during programming. A pulse sequence that provides a highly-predictable programming curve is applied to the device (region A). After that, the flash is read (region B), and then the point in the sequence at which the device will be exactly programmed can be predicted precisely. The bulk of device programming is in a fast feedforward mode based on this predicted programming curve (region C). Regions B, D, F of the picture are verify phases and the corresponding analog voltage value is the threshold of the device under programming (Vth of Figure 2). This precision programming is self-compensated for

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device variations over distance and time. The number of verifies is minimized and almost independent from the target precision. The analog programming precision achieved is better than 7.8mV which, in a voltage range of 4V, corresponds to 9b. With this algorithm, it is possible to choose programming precision by increasing or decreasing programming speed. Faster programming curves are harder to predict with accuracy. Their use results in loss of precision. Figure 4 shows the measured tradeoff between programming speed and precision. An example of a 5b (32 levels) distribution diagram is shown in Figure 5, where average programming time with 8 cells programmed in parallel is 500µs giving 100µs/B equivalent writing speed. In a digital memory, probability of bit error during read must be zero. The main sources of error are: read precision (including noise at the output of the amplifier and analog to digital conversion error) and charge loss over time from the floating gate. In this chip, charge loss is the more critical and its effect is a shift and an increased spread of the programmed threshold values for each level. The shift effect is partially compensated using reference cells programmed at all levels, while the spread effect influences the separation among levels. Retention time monotonicly decreases with increased programming precision. Results of retention tests on chips previously stressed though application of hundreds of program-verify-erase cycles are performed. Figure 5 shows threshold distribution measurements after a 200 hours bake at 250°C with the whole chip programmed at 4b precision. Using 16 reference devices to store the analog threshold levels, the chip perfectly retrieves the stored digital data, corresponding to at least 4/5 years equivalent retention at room temperature. At 6b programming precision, the high temperature retention time is reduced to roughly the room temperature equivalent of 6 months, sufficient for specialized applications such as storage of voice messages. Retention tests based on 3 months storage at room temperature show no significant threshold variations. Perfect digital data retrieval allows this high density memory to be compatible with digital compression algorithms, where loss of a single bit can result in significant distortion during data retrieval because of decompression. A single chip stores and retrieve a set of 24 VGA full-color images compressed in standard JPEG and a second chip stores and retrieves 40 minutes of compressed speech using lpc10 algorithm at 2.4kb/ s. In both cases, data retrieval and decompression are perfect. The chip is fabricated in a standard 3V 0.5µm common-ground NOR Flash-EEPROM process (2 polys, 2 metals) with channel hot electron programming and Fowler-Nordheim tunneling erasing. The cell is 1.45x1.61µm2, resulting in an array density of 257Mb/cm2. The tunneling oxide and gate oxide thickness are 110Å and 120Å. A micrograph of the chip is shown in Figure 7. Acknowledgments: The authors thank R. Bez, G. Campardo, P. Cappelletti, G. Crisenza, C. Golla, A. Grossi, A. Maurelli, A. Modelli, A. Perelli, G. Tamiazzo for support and L. Fumagalli for help in testing. References: [1] Jung, T., et al., “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” ISSCC Digest of Technical Papers, pp.32-33, Feb., 1996. [2] Van Tran, H., et al., “A 2.5V 256-Level Non-Volatile Analog Storage Device Using EEPROM Technology,” ISSCC Digest of Technical Papers, pp.270-271, Feb., 1996. [3] Kramer, A., et al., “55GCPS CAM Using 5b Analog Flash,” ISSCC Digest of Technical Papers, pp.44-45, Feb., 1997

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Figure 1: Chip block diagram.

Figure 4: Programming time/precision trade off.

Figure 2: Analog sense amplifier. Figure 5:

Figure 3: Programming

Threshold distribution of 5b programming.

phase.

Figure 6: Retention measurement with 4b.

Table 1:

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Device parameters.

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SA 21.2: 1M-Cell Analog Flash Memory for Digital Storage

Figure 7:

© IEEE 1998

Chip micrograph.

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