Challenges and Opportunities of Extremely Thin SOI (ETSOI) CMOS Technology for Future Low Power and General Purpose System-on-Chip Applications A. Khakifirooz, K. Cheng, P. Kulkarni, J. Cai*, S. Ponoth, J. Kuss, B. S. Haran, A. Kimball, L. F. Edge, A. Reznicek, T. Adam, H. He, N. Loubet+, S. Mehta, S. Kanakasabapathy, S. Schmitz, S. Holmes, B. Jagannathan**, A. Majumdar*, D. Yang**, A. Upham, S.-C. Seo, J. L. Herman, R. Johnson, Y. Zhu*, P. Jamison, Z. Zhu**, L. H. Vanamurth, J. Faltermeier, S. Fan, D. Horak, H. Bu, D. K. Sadana*, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, W. Haensch*, E. Leobondung, G. Shahidi* IBM Research at Albany Nanotech, Albany, NY 12203, *IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 ** IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533 + STMicroelectronics at Albany Nanotech, Albany, NY 12203 257 Fuller Rd., Albany, NY 12203, phone: (518)292-7198, e-mail:
[email protected] Introduction Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2]. We have also demonstrated that analog and I/O devices can be fabricated in thin silicon, removing the speculated need for hybrid bulk-thin SOI or thick-thin SOI for SoC application. I/O and high-performance analog devices can be scaled as aggressively as logic transistors [2] and a single device architecture fabricated by a universal process can be used for both analog and logic applications. The fact that a simple device isolation can be used along with dispensable no need to body contact increase the area efficiency of ETSOI. These enable ETSOI to be a cost-competitive solution for next generation technologies. In this paper we discuss some of the concerns that must be addressed before ETSOI technology can be used for mainstream CMOS. Raised S/D Structure Fig. 1 shows a TEM cross section of the ETSOI MOSFET with a gate length of 25 nm and channel thickness of 6 nm. A raised source/drain structure is needed to contact the thin silicon channel. However, the RSD structure increases the total transistor parasitic capacitance. This is especially a concern for future technology nodes, where parasitic capacitance dominates the total transistor load. We have developed a faceted epitxy process to reduce the parasitic capacitance. The epitaxy process is tuned to form (111) facets as opposed to (311) facets in order to enable adequate RSD thickness in future technology nodes. Fig. 2 shows TCAD simulation results indicating that 15% reduction in the total parasitic capacitance is achieved at a given series resistance if a faceted epitaxy is used instead of the conventional vertical RSD [1]. Furthermore, the faceted RSD increases the strain coupling from stress liners to the channel [2] and also increases the silicide contact area. Device Scaling and Performance Fig. 3 shows the VT roll-off of the low-power ETSOI MOSFETs demonstrating excellent short-channel control down to LG=25 nm [1]. Matched low-power NFET/PFET VT is obtained with a single HK/MG stack, further simplifying the CMOS integration. Figs. 4 and 5 show the performance of the low-power and high-performance NFETs and PFETs, respectively. With VDD=0.9 and at Ioff =1nA/μm, NFET and PFET transistors have a drive current of 650 and 480 μA/μm, respectively. High-performance devices have a drive current of 870 and 660 μA/μm for NFET and PFET, respectively and at
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Ioff=100nA/μm. PFET performance is in particular respectable owing to small series resistance (Rext < 170 Ω.μm) obtained by in-situ doped SiGe RSD and implant-free extension formation [1, 2]. As shown in Fig. 6, NFET Rext is still high partly due to high silicide contact resistance to in-situ doped Si:C RSD. Hence, further NFET performance increase is possible by optimizing the epitaxy process and contact engineering. Fig. 7 shows the RF performance of the ETSOI devices. NFET and PFET transistors demonstrate a cut-off frequency of 300 and 260 GHz, respectively, with LG=25 nm and contacted gate pitch of 260 nm [3]. No substrate contact is required for analog and RF devices due to the absence of history effect in fully-depleted transistors. Global Device Variability We have reported excellent device matching with a record AVT of 1.25 mV.μm in ETSOI devices as a consequence of negligible random dopant fluctuation in undoped channel and minimized LER with implant-free process [2]. However, it is critical to study global device variation as well. One of the main concerns with ETSOI is the silicon thickness variation across the wafer. As shown in Fig. 8, silicon thickness usually has a 1.5 nm range across the wafer after thinning from 70nm to target Si thickness. Significantly better uniformity is achieved starting with thin SOI wafers. Fig. 9 shows that the short channel saturation VT varies within 70 mV across the wafer. To better understand the contribution of the silicon thickness to VT variation, we electrically estimated the channel thickness from C-V measurements with and without a backbias as shown in Fig. 10. Silicon thickness is estimated by fitting the C-V curves with Schrödinger-Possion solutions. Fig. 11 shows a contour plot of the estimated TSi with 1.5 nm range across the wafer, consistent with ellipsometry measurements in Fig. 8. Fig. 12 shows the correlation between short-channel VT and the estimated channel thickness demonstrating a sensitivity of 25 mV/nm. These results provide a guideline for silicon thickness uniformity across the wafer. Conclusions We explored some of the challenges of the ETSOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity requirement. Acknowledgements We would like to thank the operation and process teams at Albany Nanotech and IBM East Fishkill. References: [1] K. Cheng et al., Symp. VLSI Tech., 2009, p. 212. [2] K. Cheng, et al., to be presented in IEDM, 2009. [3] A. Khakifirooz, et al., to presented in ISSCC, 2010.
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