Functional software-based self-testing (SBST) has been recently studied by ... or medium size and performance open-source processors have been studied and ...
Challenges in Scaling Software-Based Self-Testing to Multithreaded Chip Multiprocessors Dimitris Gizopoulos University of Piraeus, Greece Abstract Functional software-based self-testing (SBST) has been recently studied by leading academic research groups and applied by major microprocessor manufacturers as a complement to other classic structural testing techniques for microprocessors and processor-based SoCs. Is the SBST paradigm scalable to testing multithreaded chip multiprocessors (CMPs) and effectively detect faults not only in the functional components but also in the threadspecific and core interoperability logic? We study the challenges in scaling existing software-based self-test capital (uniprocessor self-test programs and self-test generation techniques) to real, multithreaded CMPs, like Sun’s OpenSPARC T1 and T2. Since this type of CMPs is built around well studied microprocessor cores of mature architecture (like SPARC v9 in the OpenSPARC case), tailoring, enhancing and scheduling of existing uniprocessor self-test programs can be an effective methodology for software-based self-test of CMPs.
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State-of-the-art
Functional self-testing of microprocessors was studied a few decades ago and has recently captured again the interest of several academic research groups due to the extensive use of microprocessors and embedded processors of various performance, cost, size and power consumption categories. Software-based self-testing (SBST) is a term that is typically used to refer to self-test approaches that do not involve DFT modifications and are based on the execution of normal programs from on-chip memories (caches) during manufacturing testing or from the main memory during periodic on-line testing. SBST is usually proposed as an effective supplement to classic testing techniques like scan. Academic research efforts on SBST have been reported in [1]-[8] including studies of pipelined processors, speculative execution (branch prediction), utilization for on-line testing as well as efforts towards automatic self-test programs generation. Software-based self-test scheduling for test application time reduction in symmetric multiprocessors was recently studied in [8]. Industry efforts in utilizing SBST as a supplement to other techniques used in manufacturing testing were reported in [9], [10].
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Academic Processor Benchmarks
University research in the area of microprocessor test and DFT has been constrained by the lack of “real”, complex microprocessor designs for experimentation. Several small
or medium size and performance open-source processors have been studied and promising results have been reported. Unfortunately, those processor models were rather simple (some without performance mechanisms like pipeline, others without exception handling or floatingpoint arithmetic support, etc.) and relatively small (less than 40K gates) to guarantee successful scaling of the proposed approaches to real large industrial designs. Even the most complex benchmark used in recent works in the area [3], [4], [5], [8], a publicly processor model from www.opencores.org named OpenRISC which provides support for integration in an SoC as well as simulation and synthesis, is still far from being considered a real, industrial high-performance microprocessor. Given the dominance of the chip multiprocessors in the processor market the last years, the problem of lack of real benchmarks in the academic community is accentuated. Availability of Sun’s OpenSPARC T1 and T2 models and full support for simulation, synthesis, etc, offers university research groups working in the area of microprocessor testing, verification and related topics, the ability to actually evaluate their approaches both on a processor core (SPARC v9 core) and also overall on a complex multithreaded chip multiprocessor (CMP) design.
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Key Points of this Study
Effective scaling of a software-based self-test approach (for manufacturing testing or on-line testing) to chip multiprocessors requires:
comprehensive testing of individual processor cores (at the same test quality levels of a standalone uniprocessor), and
extension and enhancement of the self-test programs to detect faults in the multiprocessor-specific logic (interconnection network, thread-selection logic in multithreaded architectures, multiple execution units or multiple storage units)
The main objectives of our study in scaling uniprocessor self-test wealth to complex chip multithreaded (CMT) architectures like OpenSPARC are the following:
determine uniprocessor self-test programs that can be applied unaltered to test the functional units shared among the multiple threads of each individual core; apply self-test routines to identical components of the different execution units/pipelines within a single processor core of the multiprocessor;
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modify uniprocessor self-test programs and schedule them to different treads to detect faults in the per thread modules (modules repeated for each thread of the core); effectively test the thread-selection logic; reduce test program size using a single copy of the self-test programs executed in parallel by all the processor cores; reduce test application time taking advantage of the thread-level parallelism (TLP); set up time-efficient experiments for fault simulation and fault injection to evaluate detection capabilities of the self-test programs The above points are among the most important ones that microprocessor test and self-test research in the near future is expected to focus on.
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Acknowledgements
This is a joint work of the author and M.Psarakis, M.Hatzimihail, A.Apostolakis of the Computer Systems Laboratory of the Department of Informatics, University of Piraeus, Greece. Work supported in part by the General Secretariat of Research and Technology of the Ministry of Development under research grant PENED 03ED229.
References [1] L.Chen, S.Ravi, A.Raghunathan, S.Dey, “A Scalable Software-Based Self-Test Methodology for Programmable Processors”, IEEE/ACM Design Automation Conference, pp. 548–553, 2003. [2] F.Corno, E.Sanchez, M.Sonza Reorda, G.Squillero, “Automatic Test Program Generation – a Case Study”, IEEE
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[9] [10]
Design & Test of Computers, vol. 21, no. 2, pp. 102–109, 2004. S. Gurumurthy, S. Vasudevan and J. Abraham, “Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor”, IEEE Intl. Test Conf., paper 27.3, 2006. M.Psarakis, D.Gizopoulos, M.Hatzimihail, A.Paschalis, A.Raghunathan, S.Ravi, “Systematic Software-Based SelfTesting of Pipelined Processors”, IEEE/ACM Design Automation Conf., pp. 393-398, 2006. C.H.-P.Wen, L.-C.Wang, K.-T.Cheng, K.Yang, W.-T.Liu, J.-J.Chen, “Simulation-based Target Test Generation Techniques for Improving the Robustness of a SoftwareBased-Self-Test Methodology”, IEEE Intl. Test Conf., paper 36.3, 2005. A.Paschalis, D.Gizopoulos, “Effective Software-Based SelfTest Strategies for On-Line Periodic Testing of Embedded Processors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 24, no. 1, pp. 88-99, January 2005. M.Hatzimihail, M.Psarakis, D.Gizopoulos, A.Paschalis, “A Methodology for Detecting Performance Faults in Microprocessor Speculative Execution Units via Hardware Performance Monitoring”, IEEE Intl. Test Conf., paper 29.3, 2007. A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, “Functional Self-Testing for Bus-Based Symmetric Multiprocessors”, IEEE Design Automation and Test in Europe Conf., pp. 393-398, 2008. P.Parvathala, K.Maneparambil, W.Lindsay,“FRITS–A Microprocessor Functional BIST Method”, IEEE Intl. Test Conf., pp. 590–598, 2002. I.Bayraktaroglu, J.Hunt, D.Watkins, “Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issue”, IEEE Intl. Test Conf., paper 27.2, 2006.
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