Chapter 2 FPGA Fundaments

Chapter 2 FPGA Fundaments

1

Overview -- Categories of Programmable Logic Devices (PLDs) „ „ „

Simple Programmable Logic Devices (SPLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

2

PLD Categories

3

Design Factors Affecting PLD Architectural Selection

4

PLD Design

5

SPLD Device Overview „

Simplest PLD (SPLD) devices „ „

PAL: Programmable Array Logic PLA: Programmable Logic Array „ „

Two logic gate array architectures Boolean ANDs and ORs

6

Simplified PAL Architecture

7

SPLD Characteristic

8

CPLD Device Overview „

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CPLD: Complex programmable Logic Device Complexity and density: „

FPGAs > CPLDs >SPLDs

9

Basic CPLD Structure Input/Output

Macro Input/Output

Macro

Macro Input/Output

Switch Fabric Macro

Macro

Macro

Input/Output

10

CPLD Decision Tree

11

CPLD Characteristics

12

CPLD to FPGA Comparison

13

A Mapping of Functionality for CPLD and FPGAs

14

Operational Categories of FPGA Devices

15

FPGA Device Overview „ „

FPGA were introduced in 1985 by Xilinx FPGA were developed to address the gap between CPLD and ApplicationSpecific Integrated Circuits (ASIC) devices

16

Typical FPGA Characteristics

17

FPGA Types

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One-time-programmable FPGA OTP: One-Time-Programmable

ISP: In-System-Programming

19

FPGA Manufacture

20

SRAM-Based FPGA Architecture

21

Fundamental FPGA Structure „ „ „ „ „ „ „

Logic blacks Routing matrix and global signals I/O blocks Clock resources Multiplier Memory Advance features 22

FPGA Logic Block Structure „

Logic block: logic cell, slice, macrocell, and logic element (LE)

23

Look-Up-Tables (LUTs) Element „

A LUT is simply a memory element

24

Combine Logic Block „

Some example names for these combined logic block groups are: tile, configurable logic block (CLB), logic array block (LAB) and MegaLAB

25

FPGA Routing Matrix and Global Signals

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Carry Chain Logic

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Global Low-Skew Routing Resources „

These resources are typically „ „

„

Limited in quantity Be reserved for high-performance and high-load signals

Global routing resources „ „

Clock Control signals 28

FPGA I/O Blocks „

The ring of I/O banks is used to interface the FPGA device to external components

29

I/O Block (IOB) Structure „

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An IOB includes input and output registers, control signals, muxes and clock signals Unused FPGA inputs should not be left floating

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I/O Block (IOB) Structure (cont’)

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I/O Interface Standards „

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Single-ended and differential operational modes are typically supported Single-ended standards „

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PCI, LVTTL

Differential standards „

LVDS, LVPECL 32

IOB Configurable Feature „ „ „ „ „ „

Pull-up or Pull-down Status of “unused” I/O I/O slew rate I/O drive strength Supported I/O standards Characteristic impedance termination 33

FPGA Clock Resource „

Clock manipulation can be implemented based on „ „

„

„

Phase-locked loop (PLL) Delay-locked loop (DLL)

PLLs generate the desired phase or frequency output by a voltagecontrolled oscillator PLLs are inherently analog circuits 34

FPGA Clock Resource (cont’) „

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DLLs access signals from a calibrated tapped delay line circuit internal to the FPGA to produce the desired clock phase or frequency DLLs are digital circuits

35

PLL and DLL Clocking

36

Global Clocking and Regional Clocking

37

FPGA Memory „ „

Two primary types of memory within FPGAs Distributed memory „

„

Takes advantage of the fact that LUT elements are implementation of SRAM memory blocks

Block memory „

The implementation of dedicated SRAM memory blocks within the FPGA 38

FPGA Memory (cont’) „

Memory elements embedded within FPGA are usually refereed to as „ „ „ „

Block RAM, Embedded system block (ESB), System RAM and Content Addressable Memory (CAM)

39

Advance FPGA Features „ „ „ „

Enhanced clock features Intellectual property (IP) Embedded processors (Hard and Soft) Digital signal processing (blocks, tools, design flow)

40

Generic FPGA Architecture

41

Q&A

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摘自戴晨志,激勵高手 42