Chapter 2b: Switch-Level Modeling - Wiley

Chapter 2: Structural Modeling

Chapter 2b: Switch-Level Modeling Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ ™ ™ ™

Objectives Switch primitives Delay specifications Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Objectives After completing this chapter, you will be able to ™ Describe what is the structural modeling ™ Describe how to instantiate switch primitives ™ Describe how to model a design in switch primitives ™ Describe how to specify delays in switches ™ Describe other features of switch primitives

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ƒ MOS switches ƒ CMOS switch ƒ Bidirectional switches

™ Delay specifications ™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Switch Primitives ™ Ideal switches – without a prefixed letter “r” ™ Resistive switches – with a prefixed letter “r” • MOS switches • nmos • pmos • cmos • Bidirectional switches • tran • tranif0 • tranif1 • Power and ground nets • supply1 • supply0

• Resistive switches • rnmos • rpmos • rcmos • Resitive bidirectional switches • rtran • rtranif0 • rtranif1 • Pullup and pulldown • pullup • pulldown

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ƒ MOS switches ƒ CMOS switch ƒ Bidirectional switches

™ Delay specifications ™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

The nmos and pmos Switches ™ To instantiate switch elements switch_name [instance_name] (output, input, control);

ƒ The instance_name is optional

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Example 1 --- The CMOS Inverter

module mynot (input x, output f); // internal declaration supply1 vdd; supply0 gnd; // NOT gate body pmos p1 (f, vdd, x); nmos n1 (f, gnd, x); endmodule Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Example 2 --- CMOS NAND Gates module my_nand (input x, y, output f); supply1 vdd; supply0 gnd; wire a; // NAND gate body pmos p1 (f, vdd, x); pmos p2 (f, vdd, y); nmos n1 (f, a, x); nmos n2 (a, gnd, y); endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Example 4 --- A Pseudo nMOS Gate module my_pseudo_nor(input x, y, output f); supply0 gnd; // Pseudo nMOS gate body nmos nx (f, gnd, x); nmos ny (f, gnd, y); pullup (f); endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ƒ MOS switches ƒ CMOS switch ƒ Bidirectional switches

™ Delay specifications ™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

CMOS Switch ™ To instantiate CMOS switches cmos [instance_name] (output, input, ncontrol, pcontrol);

„ The instance_name is optional Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

An Example --- A 2-to-1 Multiplexer

module my_mux (out, s, i0, i1); output out; input s, i0, i1; //internal wire wire sbar; //complement of s not (sbar, s); //instantiate cmos switches cmos (out, i0, sbar, s); cmos (out, i1, s, sbar); endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ƒ MOS switches ƒ CMOS switch ƒ Bidirectional switches

™ Delay specifications ™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Bidirectional Switches

„ To instantiate bidirectional switches: tran [instance_name] (in, out); tranif0 [instance_name] (in, out, control); tranif1 [instance_name] (in, out, control); • instance_name is optional Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ™ Delay specifications ƒ MOS/CMOS switches ƒ Bidirectional switches

™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Delay Specifications --- MOS/CMOS Switches ™ Specify no delay mos_sw [instance_name](output, input, …); cmos [instance_name](output, input, …);

™ Specify propagation delay only mos_sw #(prop_delay)[instance_name](output, input, …); cmos #(prop_delay)[instance_name](output, input, …);

™ Specify both rise and fall times mos_sw #(t_rise, t_fall)[instance_name](output, input, …); cmos #(t_rise, t_fall)[instance_name](output, input, …);

™ Specify rise, fall, and turn-off times mos_sw #(t_rise, t_fall, t_off)[instance_name](output, input, …); cmos #(t_rise, t_fall, t_off)[instance_name](output, input, …); Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ Objectives ™ Switch primitives ™ Delay specifications ƒ MOS/CMOS switches ƒ Bidirectional switches

™ Signal strengths

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Delay Specifications --- Bidirectional Switches ™ Specify no delay bdsw name [instance name](in, out, control);

™ Specify a turn-on and turn-off delay bdsw name #(t_on_off)[instance name](in, out,control);

™ Specify separately turn-on and turn-off delays bdsw name #(t_on, t_off)[instance name](in, out, control);

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ ™ ™ ™

Objectives Switch primitives Delay specifications Signal strengths ƒ Signal strengths ƒ trireg examples

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Signal Strengths ™ Can be weakened or attenuated by the resistance of the wires

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Single Strength Reduction

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

Syllabus ™ ™ ™ ™

Objectives Switch primitives Delay specifications Signal strengths ƒ Signal strengths ƒ trireg nets

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

trireg Nets ™Driven state ™Capacitive state

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

An Example of trireg Net ™At simulation time 0 ƒ ƒ ƒ ƒ

a, b, and c = 1 x=0 y -> 0 z -> driven state and = strong0

™At simulation time 10 ƒ b=0 ƒ y -> a high-impedance ƒ z -> capacitive state and = medium0

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

An Example of Charge Sharing Problem ™At simulation time 0 ƒ a=0 ƒ b=c=1 ƒ x, y, and z = strong1

™At simulation time 10 ƒ b=0 ƒ y -> capacitive state and = large1 ƒ z -> driven state and = large1

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 2: Structural Modeling

An Example of Charge Sharing Problem ™At simulation time 20 ƒ c=0 ƒ z -> capacitive state and = small1

™At simulation time 30 ƒ c = 1 again, ƒ y and z share the charge

™At simulation time 40 ƒ c=0 ƒ z -> capacitive state and = small1

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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