Chapter 7:
NEW APPLICATIONS FOR ION IMPLANTATION: LIFE IN A VERTICAL CMOS WORLD, MATERIALS MODIFICATION and DEEP PROTON IMPLANTS Michael I. Current Current Scientific, San Jose, CA, USA
[email protected] ABSTRACT This chapter looks in some detail at the methods and process issues for high-dose implantation for formation of planar and 3D CMOS devices and materials. Among the topics discussed are: implants for enhancement of carrier mobility in CMOS channels, doping of sub-10 nm fullydeleted CMOS in planar and finFET structures, tuning of damage accumulation profiles by control wafer temperatures during implantation for both cryo and “hot” conditions, use of dopant and non-dopant ions for materials modification, diffusion controls, resist stability enhancements and local plasma etch rate tuning. The chapter concludes with some examples of the use of MeV protons for membrane separation and lamination of 3D CMOS device layers. . CHAPTER CONTENTS
Page
1. Implant technology in a post-scaling world 1.1 60 years of scaling; shallow junctions to finFETs 1.2 Mobility enhancers 1.3 Fully-depleted channels; finFET doping 1.4 Leakage current controls for bulk finFETs 2. Materials modification applications 2.1 Dopant diffusion controls 2.2 Etch rate controls 2.3 Resist adhesion 3. Deep proton implants 4. Summary References
7-2 7-6 7-12 7-22 7-39 7-41 7-44 7-47 7-49 7-52 7-53
7-1
1.0 Introduction: Implant technology in a post-scaling world The modern world of high-performance electronics has largely been built on the steady increases in the performance of CMOS transistor driven devices, accompanied by the proportional decrease, over many orders of magnitude, in the cost per transistor and memory storage bit. The linked progression in increasing IC chip complexity and decreasing cost comprise the basics of Gordon Moore’s “laws” [ref to IEEE Spectrum articles]. The basic switches in these electronic devices are predominantly variations on a planar CMOS transistor (Fig. 1.0.1), with the current flow between a heavily-doped “source” junction to a corresponding “drain” controlled by voltages applied to a “gate” electrode placed over a lightly-doped “channel” region.
Figure 1.0.1. Sketch of major structures in a planar CMOS transistor. Providing the doping levels and locations for the various junctions and conducting regions in planar CMOS transistors has been the principal function of ion implantation equipment in IC fabrication. The precision, stability and overall flexibility of ion implantation techniques has led to doping process spanning a dose of range of 106 and energies from ≈100 eV to several MeV (Fig. 1.0.2). For 28 nm planar CMOS process, the number of implants per system-on-chip (SOC) device ranges from 40 to 60 implant steps [Tsukemoto10].
Figure 1.0.2. Doses and energies for major doping implants for CMOS transistors, Si-based PV cells and formation of SOI and laminated materials.
7-2
This chapter will discuss the changes in ion implantation processing in present day (2014) and near-future applications, driven by improvements in logic and memory IC devices, Si-based photo-voltaic (PV) devices and the emerging range of methods for formation of laminated heterogeneous materials wafers and intimate stacking of 3D circuits. 1.1 60 years of scaling: shallow junctions to finFETs For over half a century, the principal method for improving CMOS transistor drive currents, switching speeds and chip size has been to systematically shrink the lateral and vertical dimensions of the basic source/gate/drain regions (Fig. 1.1.1).
Figure 1.1.1. Scaling of IC devices from 1958 through the ITRS09 roadmaps for highperformance logic (micro-processors). The CMOS features tracked are the physical gate length, Lgate, source/drain extensions junction depth, XjSDE and equivalent oxide thickness of the dielectric layer insulating the gate electrode from the channel region, EOT. The long time scale and near-exponential trends in feature sizes masks the challenges to be met to achieve this unprecedented record of consistent feature size shrinking, “scaling”, and the many changes to ion implantation (and other) tools and process needed to accomplish this result. For example, since the mid-1980’s, the main new developments in ion implantation have been along two diverging paths; continual improvements in the throughput of low-energy, near and sub-keV, for doping of “shallow junctions”, sub-20 nm, for source/drain extensions (SDE) and development of MeV ion implanters for doping of deep wells for memory and imaging devices. For the last 20 years, device modelers have been aware that materials limitations of doped Si junctions and SiO2 insulators were leading to an “end of the roadmap” for planar CMOS at gate lengths of ≈25 nm (fig. 1.1.2) [Taur 98 &02].
7-3
Figure 1.1.2. Approximate dimensions, doping levels and depletion boundaries for a 1998 model of an nMOS transistor with a 25 nm effective gate length at the limits of leakage current and switching performance [Taur98]. The principal doped regions in this model nMOS transistor are (1) a source/drain (without shallow SD extension structures), (2) a highly-doped “super-halo” channel (formed by tilted wafer implants) and (3) a doped poly-Si gate electrode. “End of Roadmap” bulk planar CMOS doping profiles With the general consensus that shrinkage of bulk planar CMOS to gate lengths significantly shorter than 20 to 25 nm will not result in improved device performance and will lead to unacceptably high leakage currents and device variability, one can develop a stable picture of the doping profiles to be used in high performance planar bulk Si CMOS going forward using the Denard scaling relationships and associated ratios for “well tempered” CMOS transistors [Denard73]. The leading scaling ratio linking lateral (lithography and etching driven) and vertical (doping driven) features is that the source/drain extension (SDE) junction depth is between ½ to 1/3 of the gate length dimension. In order to avoid current crowding, high series resistance and problems in forming metal/junction contacts, the source/drain contact junction is significantly deeper, approximately equal to the gate length. The halo doping region under the SDE extends down to the depth of the contact region. CMOS well depths for single-well devices commonly extend to the depth of shallow trench isolation (STI) structures, which are 200 to 300 nm deep for logic devices. The dose-energy windows and doping profiles (calculated by SRIM) for 25 nm gate length bulk planar CMOS transistors are shown in Fig. 1.1.3.
Figure 1.1.3. Dose-energy and profiles for 25 nm bulk planar CMOS.
7-4
“End of Roadmap” Strategies: New Materials and Vertical Devices The limitations of “end of roadmap” planar CMOS transistor performance, even after achieving stable control of shallow junction formation, has led to: (1) introduction of new materials and strained structures for improved carrier mobility and (2) use of fully-depleted channel designs. In addition to fully-depleted channels, the desire to continually increase device packing density (for improvements in performance, yield, cost of manufacturing and chip size) has fostered the development of vertical channel and memory devices. Vertical and “ultra-slim” junctions The transition to the use of vertical channels, led by the use of “tri-gate” transistors in 22 nm logic at Intel, has actually been underway for most of the last decade. The need to increase the density of memory cell arrays in DRAMs drove the replacement of planar transistor gates by “recessed channels”, where the gate electrode and oxide was placed in a deep trench surrounded by source and drain contacts, establishing long channel, low leakage cell control behavior while minimizing the lateral area of the “RCAT” device (Fig. 1.1.4) [Kim03, Kim06, Lee08].
Figure 1.1.4. Sketch of planar and vertical (“recessed channel array transistor”, RCAT) word line transistor gates in DRAM devices.
Elaborations of the RCAT gate design to include buried channel paths through the bottom of the vertical gate have evolved into an increasingly wide variety of buried and exposed multi-fin structures in advanced DRAM and NAND memories [Lee07, Koo08]. The development of dual-gate transistors in the form of various “finFET” designs has also been under active development for over a decade (Fig. 1.1.5). The difficulties in limiting off-state currents in planar CMOS gates of less than 25 nm led to the switch to finFET devices. In the case of Intel, finFETs are referred to as “tri-gate” channels to reflect the gate control from the top as well as the two sides of the exposed channels [Bohr11].
7-5
Figure 1.1.5. Side-on view of a planar MOS channel (left) and end-on view of channels for bulk and silicon-on-insulator (SOI) finFETs (right). The first production ICs made with finFET transistors were 22 nm Intel logic and SRAMs using a “bulk” finFET design built on Si wafers and deep etch fins with a pitch of ≈60 nm (Fig. 1.1.6). The doping issues for these and other fully-depleted channel transistors will be discussed later in section 1.4.
Figure 1.1.6. Sketch of a 3 channel bulk finFET after fin etching, oxide re-fill, deposition and patterning of the gate electrode and before formation of spacer oxides, doping of extension and contact regions, deposition of fin links with heavily-doped CVD “bars” and first level metal contacts (left) and a cross-section TEM image of the fin channel and gate stack for the 22 nm Intel “tri-gate” transistor [Giles12]. 1.2. Mobility enhancers: Throughout most of the IC development timeline shown in Fig. 1.1.1, improvements in transistor drive currents and switching speeds were obtained by reducing the lateral and vertical dimensions of the transistors, “scaling”, with appropriate changes in doping concentrations, oxide thickness and drive voltages [Dennard73]. For CMOS transistors smaller than 130 nm, leakage current through SiO2 and SiONx gate oxides limited the gate oxide thickness to ≈1.2 nm. Although gate and contact pitch dimensions continued to shrink for 90 nm and smaller nodes, the limitations on gate oxide thickness restricted further scaling of the S/D and channel regions.
7-6
CMOS performance, especially drive currents, continued to improve by use of various methods to increase the carrier mobility in the channel regions by introduction of strain on the channel materials. At the introduction of 45 nm CMOS production, the classic poly-Si/SiO2 gate stack was replaced by a variety of metal gates and high-dielectric constant, “high-k”, oxides mostly based on HfO2. The net effect of channel strain and high-k/metal gate, HKMG, materials includes improved CMOS drive currents over 4x the levels obtainable by dimensional scaling alone (Fig. 1.2.1).
Figure 1.2.1. Drive current performance factors for Intel pMOS transistors for 130 to 32 nm devices [Kuhn10]. Stress engineering with epitaxial deposition of source/drain regions Since 90 nm CMOS (circa 2000), the focus on process development shifted from “Dennard scaling”, that is, proportional shrinking of gate lengths, gate oxides and junction depth by ≈0.7 for each scale cycle (or “node”), to finding ways to increase transistor drive currents by increasing carrier mobilities in the channels by application of uniaxial strain. For pMOS devices, the required compressive strain was provides by the growth of B-doped SiGe stressors by selective epi in etched regions close to the spacer edges [Ghani03]. Additional compressive strain was applied to the pMOS channel with various “stress memorization” implants into the poly-gates, from shallow trench isolation (STI) processes and from a capping nitride layer. The principal CMOS stressor regions are sketched in Fig. 1.2.2.
7-7
Figure 1.2.2. Sketch of CMOS stress methods providing compressive stress in the pMOS channel and tensile stress in the nMOS channels (stress directions shown with arrows). Application of the B-doped, SiGe epi approach for the nMOS channels, selective epi growth of Pdoped Si:C, are more challenging, even though the required C concentrations are much less (≈2% substitutional C) than the Ge levels on the pMOS side (≈45%) [Kim07]. The principal difficulty is that the growth of epitaxial Si:C with high substitutional C levels requires repeated deposition and etch-back steps at low temperatures and limits the chamber throughput to 1 or 2 wafers per hour. Stress engineering with implantation Adequate nMOS stress levels, sufficient for ≈10% drive current improvements, can be obtained by intentional formation of stacking fault defects by regrowth of deep amorphous layers at the spacer edges [Wei07, Lim10]. Such defects are common features of implant process as studied in detail by Sanger et al. [Sanger07a]. The general process is sketched in Fig. 1.2.3.
Figure 1.2.3. Sketch of formation of nMOS tensile stressors through formation of angled stacking faults at the intersections of vertical and horizontal regrowth fronts following deep Ge amorphization implants.
7-8
Stacking fault tensile stressors are common features in 32 nm nMOS transistors from Samsung and Intel (Fig. 1.2.4) as easily seen by the characteristic 45o orientation defects in TEM analysis.
Figure 1.2.4. 32nm nMOS from Samsung and Intel showing stacking fault stressors [James11]. Tensile strain with atomic and molecular Carbon ion implants Direct high-dose implantation of C, combined with n-type dopants and some variant of a diffusion-less anneal, provides a direct and productive approach to obtaining higher tensile strains in nMOS transistors [Liu07, LiFatou07]. The key to achieving high (1 to 2%) C substitutionality seems to be the regrowth of a C-rich amorphous Si layer. In one approach, a sequence of PAI, doping and C+ ion implants are followed by a low-temperature SPE anneal, yielding a 1.65% C substitutional level in the SDC regions, a 35% increase in electron mobility and 15% improvement in drive current (when combined with a nitride stress layer) at the cost of a 10x higher junction leakage current (related to the SPE anneal and EOR damage from the PAI step) (Liu07]. When C-rich molecular ions are used for the implant, a dense amorphous layer is formed (similar to the case for Borane-type molecular dopants) removing the need for a separate PAI cycle (Fig. 1.2.5). After laser annealing (1175 C, 0.8 ms), the amorphous layers created by the molecular ions are regrown resulting in high level of tensile strain, seen in the displacement of the secondary peaks from the Si lattice peak in XRD rocking curves (Fig. 1.2.6). The use of C14H14+ ions resulted in a near doubling of the substitutional C levels (to 1.35%) over the C 7H7+ implanted regions (Table 1) for a common C-dose of 2x1015 C/m2 for all cases.
7-9
Figure 1.2.5. TEM images of Si implanted with 6.6 keV/atom implants at 2x1015 C/cm2 using C+ (left) and C7H7+ (right) ions [Li-Fatou07].
Figure 1.2.6. XRD rocking curves for C+, C7H7+ and C14H14+ implanted Si after a 0.8 ms laser anneal at 1175 C [Li-Faou07].
High-mobility materials With the shift to vertical channels in finFETs, the group of strain enhancement techniques used for planar CMOS (Fig. 1.1.2) become more complex and can be harder to implement [Bedell14]. Attention has shifted to use of channel materials with intrinsically higher carrier mobility, such as Ge, SiGe and GeSn for hole conduction in pMOS and InGaAs and GaAs for electron conduction in nMOS (Fig. 1.2.7 and 1.2.8).
7-10
Figure 1.2.7. InGaAs quantum well device (QW) and switching times for various compound semiconductor and elemental channels [Sadana10].
Figure 1.2.8. QW and finFETS for InGaAs channels [Radosavljevic11]. The implant requirements associated with the use of these high-mobility channel materials include the need to develop efficient ion sources and process for doping of III-V compound semiconductors, such as Si, Te, Sn and S for n-type and C, Ge and Zn for p-type materials. “Monolayer” channel materials The next step in this process of utilization of high-mobility channel materials is the incorporation of 2-dimensional, “monolayer” conductors, such as MoS2, WSe2, GeHx, graphene as well as some of the many varieties of carbon nanotubes (CNT) and Si (and other semiconductor) nanowires into planar and vertical CMOS transistors (Fig. 1.2.9).
Figure 1.2.9. The combination of a MoS2 molecular channel and an array of single-walled (carbon) nanotubes (SWNT) on an SOI substrate to form a CMOS inverter circuit [Huang12].
7-11
Doping of molecular MoS2 and CNTs has been done in saturation mode by absorbtion of chemical vapors and hydrocarbon-based dopants (Fig. 1.2.10). To achieve controlled doping of molecular channels by ion beam means, the ion energy must be low enough (≈100eV or less) so that the dopants are incorporated in the thin channel film without extensive disruption of the molecular structure. This “deposition with dose control” will require a new level of beamline designs to achieve the required level of ion beam quality, with tight controls on the ion energy distribution and angular divergence.
Figure 1.2.10. Saturation doping of MoS2 a film by vapor doping of a donor layer of K[Fang13].
1.3. Fully-depleted CMOS channels: A characteristic feature of “post-roadmap” CMOS is the use of fully-depleted (FD) channels, where the gate/channel geometries are arranged so that the electrostatic potential from the gate is sufficient to exclude all mobile carriers from the channel, resulting in very low off-state leakage currents. FD-SOI CMOS The most direct implementation of FD CMOS is a modification of the planar CMOS designs that have been used for the last decade for “partially-depleted” SOI-CMOS. In FD-SOI CMOS, the channel thickness is reduced to 10 20 h/cm3) p-Si (an opposite trend than the case shown for HNA in Fig. 2.2.3 right). In another example where the doping effect depends on the specific etch chemistry, heavily ndoped poly-Si etches quickly in Cl+ based plasmas. However, the doping effect on etch rate is not present in F+ based plasma etching [Reyes-Betano03]. 3. Selected autocatalytic etching reactions. Autocatalytic reactions produce reaction products that influence the reaction rate. An example is the etching of SiO2 by HF (in solution, vapor and plasma environments). Details of the mechanism depend on the local pH and concentration of primary components and various buffers. HF etching of SiO2 also changes with various forms of oxide with different densities and chemical bonding; formed by thermal reactions (as “dry” or “wet” (H2O containing atmospheres of O2), by CVD and sputter deposition, etc.) [Knotter09]. For conditions where H2O on the surface is scarce, such as in vapor-HF flows and plasma environments, the product H2O from low-rate initial reaction is a catalyst for initiation of the more rapid reaction outlined above (see Fig. 2.2.2, right).
7-46
Etching of Si in HNA solutions has far more complex chemistry, with various local Si surfaces, acting as anodic and cathodic sites in sequence, leading to Si oxidation and oxide dissolution [Darling12]. The important intermediary in the HNA reaction on Si is HNO 2, which assists the oxidation of Si and acts as an autocatalytic agent. In acid baths that are agitated by stirring and ultrasonic vibrations, reaction products are rapidly removed from the etched surface and dissolved into the solution. However, for heavily-doped Si, the presence of free carriers increases the formation rate of important intermediate reaction products such as HNO2. So for heavily doped (>1019 carriers/cm3) Si, the HNA etching reaction is sustained, even with strong solution agitation, resulting in strong etching action for heavily-doped compared to more lightly doped regions (Fig. 2.2.4).
Figure 2.2.4. Etched thickness in Si doped with B and As in [1:2:3] HNA in a stirred, ultrasonic mixed solution [Charavel06]. Plasma etching reaction paths “mimic” many cases of wet etching reactions, with additional complications from more diverse intermediate elements, multiple charge states, energetic ion impacts, variable evaporation rates and partial pressures and generally less well-known specific reaction rates between components. The net effect is that the influence of ion implantation, through damage and doping effects, on plasma etching rates is still a highly empirical art form, evolving continually. 2.3. Photoresist “freezing” for multi-exposure lithography Ion implantation has long been used to pre-condition photoresist (PR) patterns for various processes, such as adding a deep cross-linked and C-rich skin to PR for enhanced durability during exposure to reactive ion etch plasmas and to reduce the amount of PR outgassing for sensitive dopant implants in order to avoid dose errors. With the extended use of sub-wavelength optical patterning, ion implant conditioning and the resulting PR line shrinks have become a routine process. With the elaboration of litho patterning to include dual and quad exposures, the effects of ion implant conditioning have been extended to include enhancement of the adhesion of multiple litho patterns of PR to the underlying wafer coatings and reduction of line edge and line width roughness [Samarakone11]. PR line shrinkage with ion implantation is illustrated in Fig. 2.3.1 for a dual-exposure process. The usual ion for PR conditioning is Ar+, mainly for its ease of use and relative lack of process complications.
7-47
A key challenge for dual-exposure litho process is that the first level PR layer needs to stay in place throughout the spin coat, exposure, develop and curing of the second layer. If the first level PR adhesion to the wafer is not sufficient, the solvents in the develop cycle of the second layer can de-laminate the PR lines (Fig. 2.3.2). As the C-rich crust forms on the surface of the PR line, the dimensional integrity of the printed line increases as the surface “stiffens” and solvent absorption decreases. These effects improve both the line edge and line width roughness of fine lines, especially if the implant included exposures with high beam tilt angle so that the sides as well as the tops of the PR line are encrusted [Martin10]. The effects of both adhesion and line roughness improvements with ion implantation are shown in Fig. 2.3.2.
Figure 2.3.1. Sketch of PR lines for a dual-exposure process utilizing ion implant line shrinks.
Figure 2.3.2. PR lines implanted with 2 keV (left (a)) and 5 keV (left (b)) Ar + ions showing resist lifting after subsequent processing for the 2 keV case and shrinkage of PR line width, CD, and reduction of line width roughness, LWR, with 2 and 8 keV Ar+ ion implants into PR (right) [Martin11]. Ion beam effects on photoresists. As ions are stopped in organic PR masks, many local bonds are broken by the ion and secondary recoil atom impacts. This forms a C-rich, heavily cross-linked “crust” is formed with a depth roughly equal to the full extent of the implanted ion profile [Hattori09, Oerhlein11]. Detailed measurements of G-rich crusts formed after high-dose implants give a crust thickness equal to the
7-48
ion beam range, , in the resist plus 3 times the straggling, (Fig. 2.3.3). As the C-rich crust is formed, the PR line shrinks in both the vertical and lateral directions.
Figure 2.3.3. Sketch of ion beam effects on photoresist, showing outgassing of volatile resist materials leaving a C-rich surface crust and formation of H2-filled bubbles under the crust layer (if the wafer temperature during implant rises above the decomposition point of short-chained resist components) (left) and ion range and crust thickness for As, B and BF2 implants (plot based on data from Hattori09). Detailed measurements of Ar+ ion energy, dose and incidence angle on PR adhesion and LER showed the positive effects of low-energy bombardment with strong side-wall exposure (Fig. 2.3.4) [Kikuchi11].
Figure 2.3.4. Line edge roughness (LER) for Ar ion exposures showing the usefulness of lowenergy beams and large tilt and twist angles [Kikuchi11] (left) and sketches of crust layer thickness and location for various ion beam incidence on a resist line. 3. H-Cut Wafer Splitting for membranes, laminated materials and 3-D CMOS Hydrogen implantation at high enough doses (≈5x1016 H/cm2) to induce planar lateral splitting in crystalline Si, Ge and GaAs, etc., under proper conditions has been used for the last decade to manufacture silicon-on-insulator (SOI) wafers as well as for lamination of diverse types of photonic and photovoltaic materials and structures [Soitec12, Atwater03, Henley08]. The development of high-current beamlines for higher energy, up to several MeV, proton beams has led to commercial applications for formation of free-standing membranes of Si, sapphire and other materials [Henley08, GTAT]. In addition, increasing attention is being paid to the options
7-49
for H-cut implants for direct lamination of CMOS device layers to for 3-D circuit arrays [OrBach11, Koyanagi13]. The effects of high-dose H implant into Si are sketched in Fig. 3.1. For relatively shallow H implants, up to a few hundred nm, into an exposed Si wafer, H2-filled surface blisters form during the implant and during subsequent thermal processing. The thickness of the blister skin is equal to the H range in Si, increasing with energy. If the H-implanted Si wafer is bonded to an oxidized “handle” wafer before thermal processing, the chemical etching of Si by the accumulated H atoms results in the formation of thin “platelet” voids aligned along the wafer surface plane in Si(100) at the depth of the H implant peak. If this bonded pair of wafers is heated to ≈450°C or subjected to appropriate mechanical force, a planar “cleave plane” will form along the platelets in the H-rich region and the wafers can be separated. After removal of the H-rich damaged layer, the handle wafer, oxide, and transferred layer becomes an SOI wafer ready for CMOS and photonic device processing. If a higher energy proton beam is used to implant H at a deep enough location, the overlying Si is stiff enough to drive the formation of planar platelets rather than surface blisters, without the need for the bonded handle wafer.
Figure 3.1. Schematic for high-dose (≈5x1016 H/cm2) implants into Si for (left) a shallow H profile into an open Si wafer surface, resulting in surface blisters, (middle) a shallow H profile with an oxide covered Si handle wafer bonded to the implanted wafer before thermal treatment, resulting in Si layer splitting and (right) a deep H profile into a Si wafer, resulting in a freestanding membrane after layer splitting. Monte-Carlo calculations [Ziegler] of H and target atom recoil profiles for high-dose, low and high-energy proton profiles in Si and sapphire are shown in Fig. 3.2. The residual damage associated with the target recoils during the ion stopping is important for H implants because H diffuses easily in Si and migrates away from the initial stopped profile unless it is trapped by local defects. The resulting H distribution follows the damage profile, peaking near the H range but slightly shallower than the initial H depth profile. For a 40keV H profile, typical of SOI wafer and photonic materials fabrication, the H depth and transferred layer thickness is ≈0.4 μm. For a 2 MeV proton beam, used for splitting of free-standing Si membranes for low-mass photovoltaic cells, the range and thickness is ≈50 μm. A 1 MeV proton beam results in 20 um free standing sapphire membranes [Ryding14].
7-50
Figure 3.2. Monte-Carlo (SRIM) calculations of initial H and Si primary recoil distributions for high-dose, 40 keV and 2 MeV protons in Si and 1 MeV protons into sapphire. H-cut splitting can be accomplished in a number of ways, such as thermal splitting at ≈450°C for ≈30 min [Soitec12], mechanical separation at room temperature [Current00b], by exposure to microwave radiation for short periods of time [Thompson05] and thermal stress from high-power laser scans [Henley07]. The heavily damaged and H-rich layer that surrounds the cleave plane can be removed by chemical-mechanical polishing (CMP) [Soitec12], exposure to H2 at temperatures above ≈1100°C [Thilderkvist00], or by specialized etching and polishing procedures, leaving relatively un-damaged crystalline material in the transferred layer. Measurements of carrier recombination rates in free-standing Si membranes, an important consideration for PV cell materials, indicate that high quality Si material survives the passage of high-dose MeV proton beams [Henley08]. H-cut techniques are envisioned to play a central role in formation of 3D ICs [Or-Bach11, Koyanagi13]. In the methods proposed by MonolithIC 3D, a completed CMOS circuit, stopping at the S/D contact formation, is implanted with H at a depth sufficient to separate the device level from the fabrication wafer. Then a temporary bond is made to a transparent handle wafer and the CMOS device layer is separated from the wafer, aligned with a fully interconnected 2 nd CMOS device layer and bonded to it. The 3D structure is completed with the fabrication of shallow vias and interconnects linking the two device layers. Many similar 3D integration methods have been explored, including bonding of CMOS device layers formed on SOI wafers thinned by removal of the handle wafer material by grind and etching methods using the buried oxide layer as an etch stop [Guanari02]. It is estimated that proton acceleration to less than 50 keV would be sufficient to implement the process shown in Fig. 3.3, with a cleave plane depth of less than 500 nm and the use of a temporary bonded carrier wafer.
7-51
Figure 3.3 Schematic of the use of H-cut techniques to split away a completed CMOS front end device (upper) and laminate it to a fully metalized 2nd CMOS layer, to be connected by vias and final metal layers (lower) [Or-Bach11]. 5. Summary The use of ion implantation for doping of CMOS source/drains and gates has extended the scaling of transistors to the “end of the roadmap” for planar CMOS with gate electrode lengths of ≈20 nm and SDE junction depths of less than 10 nm. The transition to fully-depleted planar and vertical channels is well underway in logic, memory and power devices. The interesting story going forward will be the increasingly complex interplay of ion beam and CVD-type methods for formation and doping of 3D device structures. New technologies, such as the use of individually implanted dopants in precise locations to form Qbit structures for “quantum computers”, and use of alternative semiconductor materials for high-mobility channels, such as Ge, III-V alloys and C-based nano-tubes, will be discussed in papers at the Ion Implantation Technology conference that follows this school. Looking beyond the fabrication of CMOS-based switching circuits towards the development of new switching technologies and the more immediate prospects for integration of electrical and optical signals in “photonic” materials and devices, the utility of providing additional atoms to materials and devices with the precision and economic efficiency which are hallmarks of ion implantation techniques point to long and fruitful careers for young, inventive process engineers. The key to progress is always the recognition that innovation is not a “commodity” item. The complexity of the materials challenges and economic pressures for “quick and cheap” solutions continues, as always, to limit the apparent options for innovative engineering. We hope that this school will contribute to the education of young ion implantation process engineers and machine designers and provide information and ideas that, against all the usual odds and with a lot of hard work, luck and gumption, will result in new miracles. “The best way to predict the future is to invent it.” Alan Kay. Acknowledgements The author wishes to thank many contributors to the work described in this chapter and in particular, Takeshi Kuroi at Renesas, Amitabh Jain at Texas Instuments (now at Global Foundries), Susan Felch previously at Varian for many years (now independent), Paul Timans at Mattson (now independent), Dale Jacobon at SemEquip (now at Coherent), John Hautala at Epion (now at Varian) and Mike Mack at Epion (now at Cape Ann Technology LLC).
7-52
References: M.S. Ameen, L.M. Rubin, M.A. Harris, C. Huynh, “Properties of ultralow energy boron implants using octadecaborane” J. Vac. Sci. Technol. B26(1) 373-376. Ameen08a M.S. Ameen, M.A. Harris, C. Huynh, R.N. Reece, “Dose rate effects: the impact of beam dynamics on materials issues and device performance”, IIT08, AIP Proc. CP1066, 30-33. (2008). Atwater03 H.A. Atwater, M.I. Current, M. Levy, T. Sands, “Integration of heterogeneous thin-film materials and devices”, 768th Symp. Proc. Materials Research Society (2003). Beasom02 J.D. Beasom, Trench MOS Gate Devices, US Patent US 6,368,920 B1 (2002). Bedell14 S.W. Bedell, A. Khakifrooz, D.K. Sadana, “Strain scaling for CMOS”, MRS Bull. 39, Feb, 2014, 131-137. Bergemont12 A. Bergemont Maxim: “Lessons from 15 years of mixed signal ICs”, slides (2012). Bohr11 M. Bohr, “Evolution of scaling from the homogeneous era to the heterogeneous era” IEDM11 (2011). Brailove11 A.A. Brailove, “Kerf-free wafering: technology overview”, (2011), http://www.avsusergroups.org/joint_pdfs/2011-2brailove.pdf. Charavel06 R. Charavel, J-P. Raskin (U. Louvain), “Tuning of etch rate by implantation: Silicon, polysilicon and oxide”, Ion Implant Technology 2006. Collart06 E.J.H. Collart, B.J. Pawlak, R. Duffy, E. Augendre, S. Severi, T. Jassens, P. Absil, W. Vandervorst, S. Felch, R. Scheutelkamp. N.E.B. Cowern, “Co-implantation for 45 nm PMOS and NMOS source-drain extension formation: device characterization down to 30 nm physical gate length”, IIT06, AIP CP866 (2006) 37-40. Current96 M.I. Current, “Ion implantation for silicon device manufacturing: a vacuum perspective”, J. Vac. Sci Technol. B14(3) (1996) 1115-1123. Current98 M.I. Current, M.A. Foad, J. England, D. Lopes, C. Jones, D. Su, “200 eV to 10 keV Boron implantation and rapid thermal annealing: A SIMS and TEM study”, J. Vac. Sci. & Technol. B16 (1/2) (1998) 327-333. Current00 M.I. Current, M.A. Foad, A.J. Murrell, E.J.H. Collart, G. deCock, D. Jennings, “Process integration issues for doping of ultra-shallow junctions”, J. Vac. Sci Technol. B18(1) (2000) 468-471. Current00b M.I. Current, S.W. Bedell, I.J. Malik, L.M. Feng, and F.J. Henley, ”What is the future of sub100 nm CMOS: ultrashallow junctions or ultrathin SOI?”, Solid State Technol., (2000). Darling11 R.B. Darling, Washington U. http://www.ee.washington.edu/research/microtech/ cam/PROCESSES/PDF%20FILES/WetEtching.pdf Dennard73 R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, A. LeBlanc, “Ion implanted MOSFET’s with very short channel lengths”, IEDM73 pp.152-155. Duffy06 R. Duffy, A. Heringa, J. Loo, E. Augendre, S. Severi, G. Curatola, “”Low-leakage ultrascaled junctions in MOS devices; from fundamentals to improved device performance”, ECS Transactions, 3(2) (2006) 19-33. Duffy07 R. Duffy et al., “Solid phase epitaxy versus random nucleation and growth in sub-20 nm wide fin field-effect transistors”, Appl. Phys. Lett. 90 (2007) 241912. Duffy08 R. Duffy et al., “Doping fin field-effect transistor sidewalls: Impurity doe retention in silicon due to high angle incident ion implants and the impact on device performance”, J. Vac. Sci. Technol. B26(1) (2008) 402-407. Elliman87 R.G. Elliman, J.S. Williams, S.T. Johnson, E. Nygren, “Ion beam induced amorhization and crystallization processes in Si and GaAs”, Mater. Res. Soc. Proc. 74 (1987) 471-476. Faifer06 V.N. Faifer, M.I. Current, T.M.H. Wong, V.V. Souchkov, “Non-Contact Sheet Resistance and Leakage Current Mapping for Ultra-Shallow Junctions”, J. Vac. Sci. Technol. B24(1) (2006) 414-420. Faifer 07 V.N. Faifer, D.K. Schroder, M.I. Current, T. Clarysse, P.J. Timans, T. Zangerle, W. Vandervorst, T.M.H. Wong, A. Moussa, S. McCoy, J. Gelpey W. Lerch, S. Paul, D. Bolze, J. Halim, “ Influence of halo implant on leakage current and sheet resistance of ultra-shallow p-n junctions, J. Vac. Sci. Technol. B25(2007)1588-1592. Fang13 H. Fang, H. Tosun, G. Seol, T-C. Chang, K. Takei, J. Gup, A. Javey, “Degenerate n-doping of few-layer transition metal dichalcogenides by potassium”, Nano Lett. 13, 1991-1995 (2013). Ameen08
7-53
S. Felch, et al., “Optimized BF3 P2LAD implantation with Si-PAI for shallow, abrupt and high quality p+/n junctions formed using low temperature SPE annealing”, IIT02, (2002) 52-55. Felch08 S.B. Felch, et al., “Ultra-shallow junctions formed by C co-implantation with spike plus submelt laser annealing”, J. Vac. Sci. Technol. B26(1) (2008) 281-285. Fuse10 G. Fuse et al., “Momentum transfer implantation for sidewall doping of FinFETs”, SSDM10. Ghani03 T. Ghani, et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors", IEDM03 (2003) 978 – 980. Goeckner99 M. J. Goeckner, S.B. Felch, Z. Fang, D. Lenoble, J. Galvier, A. Grouillet, C-F. Yeap, D. Bang, and M-R. Lin, J. Vac. Sci. Technol. B17, 2290 (1999). Gossmann93 H.J. Gossmann, C.S. Rafferty, H.S. Luftman, F.C. Unterwald, T. Boone, J.M. Poate, J. Appl. Phys. Lett. 63(5) (1993) 639-41. Gosele99 U. Gosele, Q-Y. Tong, “Semiconductor Wafer Bonding: Science and Technology”, Electrochem. Soc. (1999). See page 150. Guanari02 K.W. Guanari et al., Electrical integrity of state-of-the-art 0.13 um SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication, Proc. Conf. Int. Electron Devices Meeting IEDM (2002), pp. 943-945. Hattori09 T. Hattori, Y-J. Kim, C. Yoon, J-K. Cho, “Novel single-wafer chamber dry and wet hybrid system for stripping and ion-situ cleaning of high-dose ion-implanted photoresists”, IEEE Trans. Semicond. Manuf. 22, 468-474 (2009). Henley07 F.J. Henley and N.W. Cheung, “Controlled process and resulting device”, U.S. patent # US2007/0122997 A1 (2007). Henley08 F.J. Henley, A. Lamm, S. Kang, Z. Liu, and L. Tian, “Direct film transfer (DFT) technology for kerf-free Silicon wafering”, 23rd European PV Solar Energy Conf. (2008). Hisamoto98 D. Hisamoto, et al. “A folded-channel MOSFET for deep-sub-tenth micron era” IEDM98,pp.1032-1034 (1998). Hobler89 G. Hobler, S. Selberherr, IEEE Trans. Computer-Aided Design 8 (1988) 450. Hook12 T. Hook, FDSOI Workshop. Feb 2012. Haung12 J. Hung et al., “A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter”, Nanotechnology 23 (22) (2012). Huff05 H.R. Huff, D.C. Gilmer, eds., “High Dielectric Constant Materials: VLSI MOSFET Applications”, Springer (2005). ITRS13 Detailed reports, tables and presentations at www.itrs.net. Izumida11T. Izumida et al., “Advantage of plasma doping for source/drain extension in bulk fin field effect transistor” JJAP 50 (2011) 04DC15. James12 D. James, www.chipworks.com, posted April 2012. Jan05 C-H. Jan, P. et al., “A 65 nm ultra low power logic platform technology using uni-axial strained silicon transistors”, IEDM05 (2005). Jones96 E.C. Jones, N.W. Cheung, “Modeling of leakage mechanisms in sub-50 nm p+-n junctions”, J. Vac. Sci. Technol. B14(1) (1996) 236-241. Kakoschke87 R. Kakoschke, H. Binder, S. Rohl, K. Masseli, I.W. Rangelow, S. Saler, R. Kassing, “Ion implantation into three-dimensional structures”, Nucl. Instr. & Meth. B21 (1987) 142-147. Kawasaki07 H. Kawasaki et al., “FinFET process integration technology for high performance LSI in 22nm mode and beyond”, IWJT07. Kicuchi11 Y. Kikuchi, D. Kawamura, and H. Mizuno, “Study of ion implantation into EUV resist for LWR improvement”, 7969th Proc. SPIE, (2011), pp. 7969-88. Kim03 H.S. Kim et al.,”An outstanding and highly manufacturable 80 nm DRAM technology”, IEDM03 (2003). Kim06 Y-S. Kim et al., “Fabrication and electrical properties of a local damascene finFET cell array in sub-60 nm feature sized DRAM”, J. Semicond. Technol. and Science 6(2) (2006) 61-67. Kim07 Y. Kim, Z. Ye, A. Lam, A. Zojaji, Y. Cho, S. Kuppurao, “Selective Si:C epitaxy in recessed areas and characterization of their material properties”, ECS Trans. 6(1) (2007) 409-417 Koo08 J-M. Koo et al., “Vertical structure NAND Flash array integration and paired finFET multi-bit scheme for high-density NAND Flash memory application”, VLSI08 (2008) 120-121. Koyanagi13 M. Koyanagi, “Heterogeneous 3D Integration: Technology enabler toward future superchip”, IEDM13 (2013). Felch02
7-54
L.A. Larson, J.M. Williams, M.I. Current, “Ion implantation for semiconductor and materials modification”, Revs. Accelerator Science and Technology, 4 (2011) 11-40. Lee07 D-H. Lee et al., “Improved cell performance for sub-50 nm DRAM with manufacturable bulk finFET structure”, VLSI07 (2007) 164-165. Lee08 H. Lee et al., “Fully integrated and functioned 44 nm DRAM technology for 1 Gb DRAM”, VLSI08 (2008) 86-87. LiFatau07 A. Li-Fatou, A. Jain, W. Krull, M. Ameen, M. Harris, D. Jacobson, “Increase of carbon substitutionality and silicon strain by molecular ion implantation”, ECS Trans. 11(6) (2007) 125-129. Lim10 K.Y. Lim et al., (Samsung), “Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices”, IEDM10 (2010). Liu07 Y. Liu, O. Gluschenkov, J. Li, A. Madan, A. Ozcan, B. Kim, T. Dyer, A. Chakravarti,K. Chan, C. Lavoie, I. Popova, T. Pinto, N. Robedo, Z. Luo, R. Loesing, W. Hemnson, K. Rim, “Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy”, VLSI07 (2007) 4A-2. Martin-Bragado09 I. Martin-Bragado, V. Moroz. “Facet formation during solid phase epitaxy regrowth:lattice kinetic Monte Carlo model” Appl. Phys. Lett. 95 (2009) 123123. Mizubayachi13 W. Mizubayashi et al., “Heated ion implantation technology for highly reliable metalgate/high-k CMOS SOI finFETs”, IEDM13. Mizuno88 B. Mizuno, I. Nakayama, N. Aoi, M. Kubota, T. Komeda, Appl. Phys. Lett. 53 (1988) 2059. Mok08 K.R.C. Mok, et al., “Comprehensive model of damage accumulation in Silicon”, J. Appl. Phys. 103 (2008) 014911. Morehead71 F.F. Morehead, B.L. Crowder, “A model for the formation of amorphous Si by ion bombardment”, in Ion Implantation, eds. F.H. Eisen & L.T. Chadderton, (1971) 25-30. Noda13 T. Noda et al., “Analysis of dopant diffusion and defects in fin structure using atomistic Kinetic Monte Carlo approach”, IEDM13. Ninomiya11 S. Ninomiya et al., “New combination of damage control techniques using SEN’s singlewafer implanters”, IWJT11 (2011). Nowak04 E.J. Nowak, “Maintaining the benefits of CMOS scaling when scaling bogs down” IBM J. Res. & Dev. 46(2/3) (2002) 169-180. Oehrlein11 G. Oehrlein, R. Phaneuf, D. Graves, “Plasma-polymer interactions: a review of progress in understanding polymer resist mask durability during plasma etching for nanoscale fabrication”, J. Vac. Sci. Technol. B 29, 010801-1-35 (2011). Or-Bach11 Z. Or-Bach, D.C. Sekar, B. Cronquist, and I. Beinglass, Monolithic 3D integrated circuits, Future Fab. Int. 37, (2011). Pawlak06a B.J. Pawlak, et al., “Effect of amorphiztion and carbon co-doping on activation and diffusion of boron in silicon”, Appl. Phys. Lett. 89 (2006) 062110. Pawlak06b B.J. Pawlak, et al., “Suppression of phosphorous diffusion by carbon co-implantation”, Appl. Phys. Lett. 89 (2006) 062102. Pawlak06c B. J. Pawlak, et al., “The Carbon co-implant with spike RTA solution for Boron extension”, Mater. Res. Soc. Proc. Vol. 912 (2006) 0912C01-03. pg. 21-26. Radosavljevic11 M. Radosavljevic et al.,”Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-k gate dielectric and scaled gate-to-drain/gate-to-source separation”, IEDM11 (2011). Reyes-Betanzo03 C. Reyes-Betanzo et al., “Fabrication of submicron structures in polycrystalline Silicon by reactive ion etching using Fluorine and Chlorine-containing plasmas”, Electrochem. .Soc. Proc. Microelectronics Technology and Devices (2003) Ryding14 G. Ryding, private communication (2014). Sadana06 D.K. Sadana, M.I. Current, “Fabrication of Silicon-on-insulator (SOI) and strain-Silicon-oninsulator (sSOI) wafers using ion implantation”, in Ion Implantation: Science and Technology, ed. J.F. Ziegler, (2006). Sadana10 D.K. Sadana, lecture notes for school before IIT10 (Kyoto) (2010). Larson11
7-55
Saenger08
K.L. Saenger, S.W.Bedell, M. Copel, A. Majumdar, J.A. Ott, J.P. de Souza, S.J. Koester, D.R. Wall, D.K. Sadana, “Effect of elevated temperature on amorphization and activation fin As-implanted Silicon-on-insulator layers”, MRS Vol 1070 (2008). Samarakone11 N.Samarakone, et al., Double printing through the use of ion implantation”, in Optical Microlithography, 6924th Proc. SPIE (2011), pp. 69242B-1-69242B-13. Sasaki04 Y. Sasaki, C.G. Jin, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, K. Tsutsui, H. Iwai, Proc. of VLSI04 (2004). Sekar11 K. Sekar et al., “Cluster carbon implants-cluster size and implant temperature effect” IWJT11 (2011). Soitec12 http://www.soitec.com/pdf/SmartCut_WP.pdf Solomon03 P.M. Solomon, D.J. Frank, J. Jopling, C. D'Emic, O. Dokumaci, P. Ronsheim, W.E. Haensch, "Tunnel current measurements on P/N junction diodes and implications for future device design," IEDM03 (2003) 233-236. Suguro01 K. Suguro, et al., “Advanced ion implantation technology for high performance transistors”, Mater. Res. Soc. Proc. 669 (2001) J1.3. Tauer02 Y. Tauer, “CMOS design near the limit of scaling”, IBM J. Res. & Dev. 46 (2002) 213-221. Thilderkvist00 A-L. Thilderkvist, S. Kang, M. Fuerfanger, and I.J. Malik, Surface finishing of cleave SOI films using epi techniques, Proc. IEEE Int. SOI Conference (2000), pp.12-13. Tsukamoto10 K. Tsukamoto, et al., “Evolution of Ion Implantation technology and its Contribution to Semiconductor Industry”, AIP Conf. Proc 1321 (2010) 9-16. Thompson05 D.C. Thompson, et al., “Microwave-cut Silicon layer transfer,” Appl. Phys. Lett 87, 224103-1-3 (2005). vanDal08 M.J.H. vanDal et al., Ion implantation for low-resistive source/drain contacts in finFET devices” MRS08 (2008). Van den Berg02 J.A. Van den Berg, et al., “Characterization by medium energy ion scattering of damage and dopant profiles produced by ultrashallow B and As implants into Si at different temperatures”, J. Vac. Sci. Technol. B20(3) (2002) 974-983. Wei07 A. Wei et al., (AMD), “Multiple stress memorization in advanced SOI CMOS technologies”, VLSI07 (2007). Wei81 C-Y. Wei, M.I. Current, D.S. Seidman, “Direct observation of the primary state of damage of ion-irradiated tungsten: I. Three-dimensional spatial distribution of vacancies”, Phil. Mag. 44 (2) 459-491 (1981). Williams85 J.S. Williams, R.G. Elliman, W.L. Brown, T.E. Seidel, “Dominant influence of beam-induced interface rearrangement on solid-phase epitaxial crystallization of amorphous Silicon, Phys. Rev. Lett. 55(14) (1985) 1482-1485. Zeigler08 J.F. Ziegler, J.P. Biersack, and M.D. Ziegler, “SRIM: Stopping and range of ions in matter”, (2008), www.srim.org. Zschatzsch11 G. Zschatzsch et al., “High performance nMOS finFET by damage-free, conformal extension doping”, IEDM11 (2011). Zographos08 N. Zographnos, I. Martin-Bragado, “A comprehensive atomistic Monte Carlo model for amorphization/recrystalllization and its effects on dopants”, Mater. Res. Soc. Proc. 1070 (2008) 1070-E03-01.
7-56
