Nov 28, 2005 - MOSFET dalam aplikasi digital. Kumpulan peranti ini, yang dikenali sebagai peranti elektronik-nano, dijangka akan memberikan bentuk ...
CHARACTERISATION OF BALLISTIC CARBON NANOTUBE FIELD-EFFECT TRANSISTOR
RAHMAT BIN SANUDIN
UNIVERSITI TEKNOLOGI MALAYSIA
CHARACTERISATION OF BALLISTIC CARBON NANOTUBE FIELD-EFFECT TRANSISTOR
2005/2006 RAHMAT BIN SANUDIN
√
11, JALAN PANDAN, TAMAN PERDANA, 83000 BATU PAHAT, JOHOR.. 28 NOVEMBER 2005
PM DR. RAZALI ISMAIL 28 NOVEMBER 2005
I hereby declare that I have read this thesis and in my opinion this thesis is sufficient in terms of scope and quality for the award of the degree of Master of Engineering (Electrical – Electronics and Telecommunications)
Signature
:
Name of supervisor
:
PM Dr. Razali Ismail
Date
:
28 November 2005
CHARACTERISATION OF BALLISTIC CARBON NANOTUBE FIELD-EFFECT TRANSISTOR
RAHMAT BIN SANUDIN
A project report submitted in partial fulfilment of the requirements for the award of the degree of Master of Engineering (Electrical - Electronics & Telecommunications)
Faculty of Electrical Engineering Universiti Teknologi Malaysia
NOVEMBER 2005
ii
I declare that this thesis entitled “Characterisation of Ballistic Carbon Nanotube Field-Effect Transistor” is the result of my own research except as cited in the references. The thesis has not been accepted for any degree and is not concurrently submitted in candidature of any other degree.
Signature
:
Name
:
Rahmat bin Sanudin
Date
:
28 November 2005
iii
To my beloved parents and wife
iv
ACKNOWLEDGEMENT
I would like to thank my supervisor, Associate Professor Dr. Razali Ismail, for giving me the opportunity to work on this project for two semesters; his advice, comments, support, and contacts have been invaluable. These past two semesters have been a struggle for me at times; however, I have learned an enormous amount. Without a strong background, this field was difficult to enter and hard to find a focused project; however the discussions and advice on the topic with my supervisor were very helpful. Also, his comments on my thesis were especially enlightening. I would like to thank research group at Purdue University, West Lafayette. Their response to my email regarding the device simulation in MATLAB is truly helpful. It was wonderful to have the perspective and knowledge of someone working on research within the nanotube field. I would not have been producing the simulation result as presented in this thesis without the help and support from these people. And last but not at all least, I would like to thank my family especially my wife who had gotten me through everything, good and bad. I do not know how to thank her enough with her endless amount of thought provoking comments and confidence. Thank you also to all my colleagues, who are very supportive and others who have provided assistance at various occasions.
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ABSTRACT
Scaling process of silicon transistor, particularly MOSFET, in the past decades had increased the performance of silicon transistor with reduction of its size. However, the scaling process will eventually reaches its limit and by that time a new group of devices are expected to replace MOSFET in digital applications. This group of devices, known as nanoelectronic devices, is expected to offer better device geometry in nanometre scale with superior performance. Carbon nanotube fieldeffect transistor (CNFET), one of nanoelectronic devices, is a transistor with its channel is made of carbon nanotube and it is designed to provide the solution for scaling process and the possibility of coexistence with current silicon technology. The purpose of this project is to study the behaviour of CNFET and the main focus is on the simulation of its current-voltage (I-V) characteristic. The simulation study is carried out using MATLAB program and the result obtained is used to compare the device performance with MOSFET. Further analysis is also made to see the effect of oxide thickness and carbon nanotube diameter on the device performance, in particular the drain current. From the simulation study, it is concluded that the performance of CNFET has no significant advantage over MOSFET and its performance is also affected by both nanotube diameter and oxide thickness.
vi
ABSTRAK
Proses penskalaan terhadap transistor silikon, terutamanya MOSFET, selama beberapa dekad yang lalu telah berjaya memperbaiki pencapaian peranti ini serta mampu mengurangkan saiz peranti ini. Namun, proses ini akan tiba di had keupayaannya dan pada masa itu beberapa peranti baru akan menggantikan MOSFET dalam aplikasi digital. Kumpulan peranti ini, yang dikenali sebagai peranti elektronik-nano, dijangka akan memberikan bentuk peranti yang lebih baik dalam skala nanometer dan juga pencapaian yang mengkagumkan. Transistor tiub-nano karbon (CNFET), salah satu daripada peranti elektronik-nano, merupakan transistor yang mempunyai saluran yang diperbuat daripada tiub-nano karbon dan ianya direkabentuk untuk memberikan penyelesaian terhadap masalah penskalaan dan berkemungkinan untuk diintegrasikan bersama teknologi silikon. Tujuan projek ini adalah untuk mengkaji sifat peranti ini dan fokus utama diberikan kepada simulasi terhadap sifat arus-voltan (I-V) peranti ini. Kajian simulasi ini dibuat menggunakan program MATLAB dan hasil keputusan yang dicapai akan digunakan untuk membandingkan pencapaian peranti ini dengan MOSFET. Analisis selanjutnya dilakukan untuk melihat kesan diameter tiub-nano karbon dan ketebalan oksida terhadap pencapaian peranti ini, atau lebih tepat lagi terhadap arus drain. Hasil keputusan yang dicapai daripada kajian simulasi mendapati bahawa pencapaian peranti ini tidak mempunyai kelebihan yang nyata berbanding MOSFET dan pencapaian peranti ini juga dipengaruhi oleh diameter tiub-nano karbon serta ketebalan oksida.
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TABLE OF CONTENTS
CHAPTER
1
2
TITLE
PAGE
TITLE PAGE
i
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENTS
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
x
LIST OF FIGURES
xi
LIST OF SYMBOLS
xv
LIST OF APPENDICES
xvii
INTRODUCTION 1.1
Project objectives
1
1.2
Scope of project
2
1.3
Layout of thesis
2
OVERVIEW OF MOSFET AND NANOELECTRONIC DEVICES 2.1 2.2
MOSFET: Gateway to nanoelectronic devices
4
Limitations to MOSFET scaling
7
2.2.1
Short channel effect
7
2.2.2
Tunnelling effect
9
viii
2.3
2.2.3
Ballistic transport
9
2.2.4
Threshold voltage
10
2.2.5
Oxide thickness
11
2.2.6
Theoretical limit
12
2.2.7
Technology limit
13
2.2.8
Economy limit
13
Introduction to nanoelectronic devices
14
2.3.1
Single-electron transistors
14
2.3.2
Resonant tunnelling devices
17
2.3.3
Carbon nanotube field-effect
2.3.4 2.4
3
transistor (CNFET)
22
Sub-10nm MOSFET
23
Summary
25
CARBON NANOTUBE STRUCTURES, PROPERTIES AND GROWTH 3.1
Background
26
3.2
Structure of Carbon Nanotube
27
3.2.1
Single-Walled Carbon Nanotube
27
3.2.2
Multi-Walled Carbon Nanotube
29
3.3
3.4
3.5
3.6
Properties of Carbon Nanotube
30
3.3.1
Electron transport in SWNT
33
3.3.2
Electron transport of MWNT
34
Growth of Carbon Nanotube
34
3.4.1
Chemical Vapour Deposition
35
3.4.2
Arc Discharge
37
3.4.3
Laser Ablation
38
3.4.4
Gas-phase Catalytic
38
Carbon Nanotube Applications
39
3.5.1
Electronic device
39
3.5.2
Chemical and Physical Sensors
40
Summary
45
ix 4
CARBON NANOTUBE FIELD EFFECT TRANSISTOR 4.1
4.2
5
Structure of CNFET
47
4.1.1
Back-gated CNFET
47
4.1.2
Top-gated CNFET
49
4.1.3
Vertical CNFET
50
Operation of CNFET
51
4.2.1
Schottky-barrier CNFET
52
4.2.2
MOSFET-like CNFET
53
4.3
P-type versus N-type CNFET
54
4.4
Application of CNFET
56
4.5
Summary
59
RESULT AND ANALYSIS 5.1
Methodology
61
5.2
Result
65
5.3
Analysis
67
5.3.1
Comparison with MOSFET
67
5.3.2
Effect of gate oxide thickness on drain current
5.3.3
Effect of CNT diameter on drain current
6
68 73
5.4
Discussion
79
5.5
Summary
80
CONCLUSION AND FUTURE WORK 6.1
Conclusion
81
6.2
Future work
83
REFERENCES
84
APPENDIX A
88
APPWNDIX B
92
x
LIST OF TABLES
TABLE NO.
TITLE
PAGE
3.1
Classification of carbon nanotube.
28
3.2
Important electrical and mechanical properties of CNT.
31
5.1
Drain current corresponding to gate oxide thickness.
74
5.2
Drain current corresponding to CNT diameter.
78
xi
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
2.1
Structure of MOSFET.
5
2.2
(a) MOSFET at OFF state, (b) MOSFET at ON state.
5
2.3
Semiconductor technology minimum feature size trend
6
2.4
Intel CPU transistor count trend.
6
2.5
Short-channel-transistor leakage current mechanisms.
8
2.6
Potential barrier between two transistors.
9
2.7
Ballistic transport in transistor channel.
2.8
Measured and calculated oxide tunnelling current vs. gate voltage for different oxide thickness.
2.9
10
11
Trends of threshold voltage and gate oxide thickness vs. channel length for CMOS technology.
12
2.10
Tunnel junction and its schematic diagram.
15
2.11
Circuit for single-electron transistor (SET).
15
2.12
Energy band diagram when (a) Coulomb blockade and (b) tunnelling.
16
2.13
Structure of Resonant Tunnelling Diode (RTD).
17
2.14
(a) Schematic diagram of RTD structure,(b) RTD in OFF state, (c) RTD is in ON state.
18
2.15
I-V characteristic of RTD.
19
2.16
(a) Schematic of RTD latch, (b) load-line diagram.
20
2.17
(a) Delay, (b) OR gate, (c) XOR gate (also NOT) (d) AND gate.
2.18 2.19
21
(a) RTD shift register schematic diagram, (b) simplified overlapping clock waveform.
21
Double-gate SBFET with silicide/metal source and drain.
23
xii 2.20
Cross section of CNFET.
24
2.21
CNT structure.
24
3.1
Three types of single-walled carbon nanotube.
28
3.2
The graphite sheet of a nanotube showing state vectors a1 and a2 and axis vector T about sheet is rolled.
28
3.3
Structure of multi-walled carbon nanotube.
29
3.4
Current induced electrical breakdown process in multi-walled carbon nanotube.
3.5
Different rolling direction and resulting electrical conduction type.
3.6
32
Metallic SWNT has armchair structure and semiconducting has zigzag structure.
3.7
30
32
Typical device geometry for electrical transport measurement.
34
3.8
Schematic setup for chemical vapour deposition.
35
3.9
Top and side view of grown CNT.
36
3.10
The process step to produce SWNT by CVD process using methane as source of carbon.
36
3.11
Apparatus for arc-discharge.
37
3.12
Single-walled carbon nanotube produced by laser ablation.
38
3.13
CNT-based field-effect transistor.
40
3.14
Category of CNT-based chemical sensors.
40
3.15
Equivalent circuit of chemiresistors.
41
3.16
Structure of CNT-based resonator.
42
3.17
Equivalent circuit model to describe electrical characteristic of resonator with no load condition.
42
3.18
Structure of CNT-based flow sensor.
43
3.19
Charge injection on CNT-based electromechanical structure.
44
3.20
Basic cell of CNT-based IR detector.
44
4.1
Image of back-gated CNFET.
48
4.2
Schematic cross section of back-gated CNFET.
48
4.3
Top-gated structure of CNFET.
49
4.4
Device structure of vertical CNFET.
50
xiii 4.5
Another view of vertical CNFET.
51
4.6
Diagram of Schottky-barrier CNFET (SB-CNFET).
52
4.7
Diagram of MOSFET-like CNFET.
53
4.8
Characteristic of CNFET due to annealing process.
55
4.9
CNFET characteristic due to exposure to potassium atom.
56
4.10
Schematic diagram of intermolecular logic gate.
57
4.11
AFM image of intramolecular logic gate.
57
4.12
Schematic of CNFET-based NOT gate.
59
4.13
Schematic of CNFET-based NOR gate.
59
5.1
The simulation model for ballistic CNFET.
62
5.2
Flow chart of simulation process.
64
5.3
Flow chart of simulation process in MATLAB program.
65
5.4
Structure of simulated ballistic CNFET
66
5.5
Plot of ID vs. VD.
66
5.6
Plot of ID vs. VG.
67
5.7
ID vs. VD for sub-10nm MOSFET.
68
5.8
ID vs. VG for sub-10nm MOSFET.
69
5.9
Simulated ballistic CNFET with 1nm diameter and varying gate oxide thickness.
5.10
Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 0.5nm.
5.11
72
Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 2.5nm.
5.17
72
Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 2.0nm.
5.16
71
Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 2.0nm.
5.15
71
Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 1.0nm.
5.14
70
Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 1.0nm.
5.13
70
Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 0.5nm.
5.12
69
Plot of ID vs. VG for CNT diameter 1.0nm and gate
73
xiv oxide thickness 2.5nm. 5.18
Simulated ballistic CNFET with 1.5nm gate oxide thickness and varying nanotube diameter
5.19
77
Plot of ID vs. VD for CNT diameter 2.0nm and gate oxide thickness 1.5nm.
5.24
76
Plot of ID vs. VG for CNT diameter 1.5nm and gate oxide thickness 1.5nm.
5.23
76
Plot of ID vs. VD for CNT diameter 1.5nm and gate oxide thickness 1.5nm.
5.22
75
Plot of ID vs. VG for CNT diameter 0.5nm and gate oxide thickness 1.5nm.
5.21
75
Plot of ID vs. VD for CNT diameter 0.5nm and gate oxide thickness 1.5nm.
5.20
73
77
Plot of ID vs. VG for CNT diameter 2.0nm and gate oxide thickness 1.5nm.
78
xv
LIST OF SYMBOLS
αD
-
Coefficient of drain capacitance
αG
-
Coefficient of gate capacitance
αS
-
Coefficient of source capacitance
CD
-
Drain terminal capacitance
CG
-
Gate terminal capacitance
CS
-
Source terminal capacitance
CΣ
-
Total capacitance
D(E)
-
Carbon nanotube density of states at top of the barrier
EF1
-
Source Fermi level (eV)
EF2
-
Drain Fermi level (eV)
f(E)
-
Probability that a state with energy E is occupied
h
-
Planck’s constant (eV-s)
I0
-
Extrapolated current per width at threshold voltage
ID
-
Drain current (I)
ION
-
On-current
IOFF
-
Leakage current
kB
-
Boltzmann’s constant (eV/K)
m
-
Gate voltage swing required per unit of electron potential
N0
-
Equilibrium electron density at top of the barrier
N1
-
Positive velocity states filled by source
N2
-
Negative velocity states filled by drain
q
-
Electronic charge (C)
T
-
Operating temperature (K)
UL
-
Laplace potential
UP
-
Potential due to mobile charge
Uscf
-
Self-consistent potential at top of the barrier
VD
-
Drain voltage (V)
xvi VG
-
Gate voltage (V)
VS
-
Source voltage (V)
Vt
-
Threshold voltage (V)
xvii
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
A
MATLAB Source Code for Ballistic CNFET Simulation
88
B
Mathematical Derivation for Ballistic CNFET Simulation
92
CHAPTER 1
INTRODUCTION
As an introduction, this chapter presents the objectives and scopes of this project and background of this project. This chapter also gives outline of this thesis as well as summary of content for each chapter.
1.1
Project Objectives
The main interest of this project is to study the characteristic one nanoelectronic device. Ballistic carbon nanotube field-effect transistor (CNFET) is chosen as one of nanoelectronic devices that have great potential to be the switching device for future. The main objectives of this project are as follows: a) Understand the device characteristic, fundamental equation and mathematical model of CNFET. b) To attain and investigate the I-V characteristics of CNFET.
The means through which the main objectives could be achieved are: a) To study the behaviour of carbon nanotube, the most important material that is used to build CNFET. b) Identify the most suitable structure of CNFET that can promote ballistic transport.
2 1.2
Scope of Project
The scope of this project is to carry out simulation study of carbon nanotube field-effect transistor using MATLAB program based on the mathematical model. The structure of MOSFET-like CNFET is used in this project because this structure has better performance than Schottky-barrier CNFET (SB-CNFET). The simulation result is then compared with MOSFET in order to measure the level of CNFET performance.
1.3
Layout of Thesis
This thesis consists of six chapters beginning with this chapter. Chapter 1 gives the objectives and scope of the project as well as the layout of thesis.
Chapter 2 presents an overview of nanoelectronic devices such as single electron transistors, resonant tunnelling diode and carbon nanotube field-effect transistor. This chapter also discussed the limiting factors that prevent improvement in MOSFET performance as its size is kept on shrinking.
Chapter 3 is dedicated to carbon nanotube, the material used as transistor channel in CNFET. This chapter discussed the background of carbon nanotube, its basic structure as well as its properties that make it very special material. Growth technique of this material is presented briefly to give an overview of how this material is produced.
Chapter 4 deals with CNFET, the basis of research in this project. It starts with its structure, followed by simple explanation on its operation and finally the applications associated with this device.
3 Chapter 5 presents the simulation result of this project. This result is then analysed through comparison with MOSFET and also factors that affects the performance of CNFET.
Finally, Chapter 6 gives conclusion for the whole project. This chapter also presents several recommendations for future work.
CHAPTER 2
OVERVIEW OF MOSFET AND NANOELECTRONIC DEVICES
This chapter gives an overview of MOSFET in brief and all the nanoelectronic devices that has been identified to replace silicon MOSFET for future digital applications. MOSFET has been in the heart of digital applications for decades and the successful scaling process in MOSFET is the main factor to push this device close to its limit nowadays. However, this does not mean MOSFET will be used forever in digital system since this device will eventually reaches its limit and thus several new devices have been identified in order to replace MOSFET in future. These new devices, also known as nanoelectronic devices, are explained in general in this chapter.
2.1
MOSFET: Gateway to nanoelectronic devices The history of metal-oxide-semiconductor field-effect transistor (MOSFET)
starts as early as 1964 when the first MOSFET is invented and since then, this device has dominated in digital application especially related to modern computers. This is not surprising since MOSFET offers high reliability and low power consumption, plus it can also be packed in large numbers within a single integrated circuit due to its relatively small size. Metal-oxide-semiconductor field effect transistor or MOSFET is a device that has three terminals which are gate, source and drain terminals. The gate terminal is a metal electrode that controls the current flow from source to drain [1]. The gate voltage needs to be higher than threshold voltage in
5 order to permits current flow in MOSFET. Source terminal is usually grounded and there is very small drain voltage applied [2].
As the gate voltage is raised above the threshold voltage, an inversion layer or channel is created and hence electrons will flow from source to drain terminal and current flows from drain to source terminal. There is no current flow to gate terminal since there is an oxide barrier that acts as insulator. Figure 2.1 shows the structure of MOSFET, followed by MOSFET when it is in off-state in Figure 2.2a and Figure 2.2b shows when MOSFET is in on-state.
Figure 2.1: Structure of MOSFET.
(a)
(b)
Figure 2.2: (a) MOSFET at OFF state, (b) MOSFET at ON state.
Scaling is a process of reducing the size of MOSFET and at the same time to improve its performance. The first method was introduced in 1974 in which by reducing the MOSFET dimension, the device density, switching speed and energy is also improved. In ideal scaling [3], as the dimension and the operating voltage is reduced by a factor of 0.7, there are a lot of improvements arise such as the area
6 density is doubled, switching delay is reduced by a factor of 0.7 and the switching energy is halved. The switching speed can be estimated when the gate capacitance, operating voltage and drive current are known. Switching energy is reduced as a result of lower total combination parasitic capacitance due to smaller device size and lower operating voltage. Reduction of switching energy is very important since the overall circuit power is very crucial especially if the system is used for a long period continuously.
The development of scaling process has produced reduction of MOSFET size since 1970 and also at the same time improved the switching speed and energy. The result can be seen in Figure 2.3 below in which the MOSFET decreases from 3µm to 0.13µm. As a result, the density of integrated circuit has also increased tremendously in the past 30 years as shown in Figure 2.4.
Figure 2.3: Semiconductor technology minimum feature size trend.
Figure 2.4: Intel CPU transistor count trend.
7
The trends of this skyrocket development are related to what is known as “Moore’s Law”, initiated by Gordon Moore, the Intel’s founder. It is predicted that the performance of integrated circuit will double in every 18 months. However, as the size of MOSFET continues to decrease even further, sooner or later the scaling process will not be able to meet the demand for future expectation and application. This is due to the fact that there are several factors that could affect the performance of MOSFET as its size becomes too small. The effect that could arise as the MOSFET reaches nanoscale size will be discussed in the next section.
2.2
Limitations to MOSFET scaling There are several effects that appear as the MOSFET size reaches nanometre
scale and becomes the limiting factor that affect the performance of the MOSFET itself. The factors are as follows: a)
Short channel effect
b)
Tunnelling effect
c)
Ballistic transport.
d)
Oxide thickness
e)
Threshold voltage
Another perspective of limitation factors to scaling process of MOSFET, as proposed in [4], is given as follows:
2.2.1
a)
Theoretical limit
b)
Technology limit
c)
Economical limit.
Short channel effect Short-channel effect is a notable effect that occurs as the size of MOSFET is
reduced [5]. The short-channel effect introduces several leakage current mechanisms
8 in MOSFET such as reverse-bias p-n junction current, weak inversion current, and drain induced barrier lowering (DIBL) current [6].
Reverse-bias p-n junction exists due to minority carriers’ diffusion near the depletion region and due to electron-hole pair generation in depletion region of reverse-bias junction. Weak inversion current occurs when gate voltage is lower than threshold voltage. Drain induced barrier lowering (DIBL) current exists when source’s potential barrier is reduced as a result of the drain’s depletion region interacts with the source. The existence of DIBL will lower the threshold voltage. Gate-induced drain lowering (GIDL) current occurs in high electric field between gate and drain, and it also occurs along the channel width between gate and drain.
Another leakage current mechanism, punchthrough, occurs when drain and source depletion regions touch deep in the channel. Narrow-width current arises when the channel length is reduced to less than 0.5µm. Gate-oxide tunnelling current occurs when the oxide layer is made very thin and also causes gate leakage current tunnelling through oxide bands. Finally, hot-carrier injection occurs when hot carriers is injected into the oxide. Figure 2.5 below shows the leakage current mechanisms that exist due to short-channel effect [6].
Figure 2.5: Short-channel-transistor leakage current mechanisms: reverse-bias p-n junction leakage ( I1), weak inversion ( I2), drain-induced barrier lowering ( I3), gateinduced drain leakage ( I4), punch-through ( I5), narrow-width effect ( I6), gate oxide tunneling ( I7), and hot-carrier injection ( I8).
9
2.2.2
Tunnelling effect Another effect occurs as the MOSFET is scaled down is tunnelling effect.
Normally, the transistors are separated sufficiently enough so that the operation of one transistor does not affect another transistors. The separation is made by inserting material that acts as a barrier between any two transistors. However, as the size of MOSFET is made very small and the barrier distance is also small, there is possibility that the carriers of one MOSFET cross the barrier. The tunnelling effect increases exponentially as the barrier distance is decreased. Figure 2.6 below shows the potential barrier between two transistors.
Figure 2.6: Potential barrier between two transistors.
2.2.3
Ballistic transport Ballistic transport is another effect that exists when MOSFET is scaled down.
The ballistic transport is a deviation of carrier transport mechanism in MOSFET [7]. Normally, when an electron travels from source to drain, it will experience scattering effect that causes its energy to decrease. However, as the device size is made very small, this mechanism starts to change. The electron now travelling from source directly to drain without facing any scattering effect because the distance travelled is very small. Ballistic transport effect caused the on-current to improve, due to less scattering happens in the device, and hence it is seen as a desired effect rather than the limiting effect of MOSFET performance. Figure 2.7 shows how the ballistic transport exists in scaled down MOSFET.
10
Figure 2.7: Ballistic transport in transistor channel.
2.2.4
Threshold voltage Another limitation to MOSFET scaling is the threshold voltage that is not
decreasing in the rate proportional to channel length. Threshold voltage is defined as the gate voltage at which current starts to flow in the channel. The threshold voltage is almost held constant when the channel length is between 1µm - 0.1µm and the threshold voltage deviates even further when channel length is below 0.1µm as shown in Figure 2.9 [8].
As the transistor is scaled below 0.1µm, below the threshold, the current does not drop to zero immediately but it decreases exponentially inversely proportional to thermal energy. This is because there are some thermally distributed electrons at source terminal have enough energy to overcome potential barrier controlled by gate voltage and this behaviour is determined by thermodynamics and independent of power supply and channel length.
Higher threshold voltage gives higher leakage current in the transistor since the leakage current, Ioff, is given as ⎛ qVt ⎞ I off = I 0 ⎜ − ⎟ ⎝ mkT ⎠
where I0 is extrapolated current per width at threshold voltage, m is dimensionless ideality factor (typically ≈1.2) and Vt is the threshold voltage. Since lower leakage
11 current is desired for a transistor, thus the threshold is needed to be as low as possible. The leakage current is reduced ten times for every 0.1V reduction of threshold voltage. Thus, as MOSFET is scaled down, the threshold voltage should be seriously considered in order to have strong performance.
Figure 2.9: Measured and calculated oxide tunnelling current vs. gate voltage for different oxide thickness.
2.2.5
Oxide thickness As the size of MOSFET is reduced, both the voltage level and gate-oxide
thickness must also be reduced [8]. The gate oxide thickness is reduced in proportion with channel length in order to ensure that gate terminal will have more control than drain terminal. The thin layer of oxide thickness will eventually cause gate leakage current to increase. This effect is also related to quantum effect tunnelling that dominates in MOSFET as the oxide thickness is reduced. The tunnelling current due to thin oxide layer probably looks negligible compared to on-state current in
12 MOSFET as depicted in Figure 2.8, but it has significant effect when the chip is at standby mode.
Another effect due to the thin oxide thickness is loss of inversion charge and also the transconductance as a result of inversion-layer quantization and polysilicongate depletion effect [4]. Take for an example, for polysilicon doping of 1020 cm3, a 2nm oxide thickness loses 20% of inversion charge at 1.5V gate voltage. Therefore, thin gate-oxide thickness will affect the performance of scaled-down MOSFET.
Figure 2.8: Trends of threshold voltage and gate oxide thickness vs. channel length for CMOS technology.
2.2.6
Theoretical limit In theoretical limit, three important limits are identified; thermal limit,
quantum limit and power dissipation limit. Thermal limit is the amount of energy required to write a bit of data and it must bigger than thermal fluctuations in order to avoid bit error to occur. Current CMOS need about 10-13 J to write a bit and the trend is to reduce this amount in order to reduce power dissipation as well. Quantum limit is defined as E/f where E is the thermal limit and f is the frequency. CMOS circuit currently operates higher than quantum limit but as scaling reaches below 100nm, it
13 is expected the limit is approached as E is decreased and f is increased. Power dissipation limit is given by p=EfnP where n is device density and P is the probability of device switches in a clock cycle. Power dissipation limit is found to be around 100W/cm2. As the size MOSFET is scaled down, the frequency increases, thus high density and low energy per bit are needed in order to ensure CMOS is operating within power dissipation limit.
2.2.7
Technology limit Technology limit is related to limitation of MOSFET technology as the
minimum size of MOSFET is expected to be only around 30nm. The limit is due to the fact that Zener breakdown will occur at source/substrate junction. Besides, leakage at gate is also starts to surface and it is very difficult to control channel current. Scaling below 30nm length will require changes to MOSFET design, particularly incorporating dual-gate design. This design has been proven to be effectively eliminates short-channel effect.
2.2.8
Economy limit Economy limit is also an important factor that caused the progress of
MOSFET scaling slowing down. This is because it is expected the reduction of cost per function is at the same rate, provided new system design and new technique is used in the process of CMOS to reduce overall system cost. Collaboration among semiconductor companies is also being practised when it comes to built chip plant in order to cope with huge cost.
All these factors affect the process of scaling MOSFET further down too deep in nanoscale range. Hence, it is necessary to find solution by introducing new type of device that can replace MOSFET in near future that will not only continue what MOSFET can do today but also can support high demand in future applications.
14 There are several nanoelectronic devices which are still under research and it is just a matter of time before they are going to be realised for home and commercial use. The next section will introduce these nanoelectronic devices categories and their application as well.
2.3
Introduction to nanoelectronic devices Since scaling process of MOSFET is about to reach its limit, therefore several
options of devices have been investigated so that future demand in digital applications can be supported. Among the promising nanoelectronic devices are divided into several categories as follows: a) Single-electron transistors b) Resonant tunnelling devices c) Sub-10nm MOSFET d) Carbon nanotube field-effect transistor (CNFET)
2.3.1
Single-electron transistors Single-electron transistor (SET) is one of the devices that are actively under
research worldwide. Basic operation of SET is described in [1], with its detail description is also discussed in [9], and it is included in description of emerging devices as described in [8]. Single electron transistors are switching devices that uses controlled electron tunnelling to amplify current. The basic part of SET, as shown in Figure 2.10, consists of two tunnel junctions connected in series with sharing a common electrode [10]. Tunnel junction consists of two pieces of metal separated by a very thin insulator and naturally it has electric capacitance based on its geometry. The electrons move from one metal electrode to another electrode through the insulator by means of tunnelling.
15
Figure 2.10: Tunnel junction and its schematic diagram.
Basic building block of single electron devices and circuits consists of placing two tunnel junctions in series to form an SET as shown in the Figure 2.11 below. The island is formed by capacitively coupled between Cg and the node between the two junctions [11]. The circuit very much the same as field effect transistor of three terminals with the island acts as a gate terminals, drain terminals is the node connected to power supply and grounded node is the source terminal. Each of tunnel junctions is characterised by its capacitance, C1 and C2, and tunnel resistance, R1and R2.
Figure 2.11: Circuit for single-electron transistor (SET).
Coulomb blockade is a phenomenon in SET that suppresses the tunnelling process due to charging barrier energy. Coulomb charging energy is actually opens a gap in energy spectrum of the island that forbids tunnelling until the barrier is
16 overcame by sufficient applied voltage. Once an electron enters the island, a new Coulomb blockade exists until the electrons tunnels out of the island.
Coulomb staircase, on the other hand, is almost the same phenomenon as Coulomb blockade except that higher threshold exists in which two electrons or more are needed to be injected. In other words, Coulomb staircase is a series of successive high number of electrons tunnelling across the junction. Coulomb oscillations are series of combination of gate voltage and drain voltage that go through a series of oscillations or resonances when Coulomb blockade is lifted. Figure 2.12 below shows the energy band diagram during Coulomb blockade and during tunnelling.
(a)
(b)
Figure 2.12: Energy band diagram when (a) Coulomb blockade and (b) tunnelling.
The applications of SET are very wide, from digital applications to analogue applications as well [12]. In digital applications, SET can be used as voltage state logics, charge state logics, background-charge-insensitive memory and Nonvolatile Random Access Memory (NOVORAM). Analogue applications are not that widely used as in digital applications but they are very promising. Among the analogue applications are supersensitive electrometry, single-electron spectroscopy, DC current standards, temperature standards and infrared radiation detector. Single electron memory is also possible since it has the scalability of semiconductor current and very high potential memory densities [11].
Further digital applications have also been proposed, which is to build singleelectron
encoded
logic
(SEEL)
memory
circuits,
Boolean
gate-based
implementations such as RS latch, D latch, flip-flop and also threshold gate-based
17 implementations of the same memory elements [13]. Fabrication processes of SET and memory devices are also have been published in [14] using two methods; PAttern-Dependent
OXidation
(PADOX)
and
Vertical
PAttern-Dependent
OXidation (V-PADOX).
2.3.2
Resonant tunnelling devices Resonant Tunnelling Devices is a device that employs quantum effect in a
simplest form and the basic operation is discussed in detail in [1]. The simplest type of Resonant Tunnelling Devices is Resonant Tunnelling Diode (RTD). The structure of RTD is made of layers of two different semiconductor III/IV alloys, such as GaAs and AlAs. Figure 2.13 below shows the structure of RTD.
Figure 2.13: Structure of Resonant Tunnelling Diode (RTD).
In Figure 2.14 shows the operation of RTD with an island or potential well is created in between two insulators. When an electron resides in the 10nm spaced island, quantum mechanics restrict its energy to either one of finite discrete quantized energy level. This is the basis of RTD operation. Electron flow is made possible by means of tunnelling quantum mechanically through two barriers. The electron is tunnelling only if its energy level is the same as energy level in the island. Otherwise, current does not flow and the device is at off state. Whenever the energy of incoming electron is at the same level as energy in the island, then only current can flow and hence the device now is at on state.
18
Figure 2.14: (a) Schematic diagram of RTD structure,(b) RTD in OFF state, (c) RTD is in ON state.
Figure 2.15 shows the I-V characteristics of RTD. First, because of the tunnelling of electrons, current through RTD increases with the increase of VD. Then, when VD continues to increase, at one point (ION), no electron on the left can tunnel into the well, and current begins to decrease. If VD keeps on increasing, current begins to increase once again due to thermal mechanisms.
ION is the peak current generated by the tunnelling of electrons. IVALLEY is the valley current due to the decrease in electrons tunnelling. Large ratio of ION/IVALLEY is desirable because larger ratio means higher gain for the negative differential resistor region. Besides, larger ratio often implies smaller IVALLEY. Smaller IVALLEY will lead to lower power dissipation since IVALLEY is usually the leakage current.
19
Figure 2.15: I-V characteristic of RTD.
One obvious difference between RTD and MOSFET is that RTD has several switching states due to several energy levels exist in the RTD. This is the advantage of RTD where it can represent more logic levels since multi-state switching behaviour permits this device to count more than one logic level compared to MOSFET. This advantage brings an interest to build hybrid microelectronicnanoelectronic device in which RTDs are attached onto source or drain terminal of MOSFET as presented in [1].
The performance of RTD can be judged from the following result presented by Compańō [8]: • 80GBit/s optoelectronic delayed flip-flop. • 50nW TSRAM cell with a 150µm 2 footprint (200 times lower power than GaAs SRAM). • Generic logic circuits operating at 12GHz with 20µm minimum feature size. • Memory circuits. • Multi-valued logic circuits. • Monolithic 4-bit 2 Gsps analogue to digital (ADC) converters. • 3GHz clocked quantisers with 40dB spur free dynamic range. • 40GHz static binary frequency dividers. • 2GB/s photo detectors with low switching energies of 30fJ.
20
Another applications based on RTD are also have been proposed by Mathews et.al. [15]. The applications are RTD latch, RTD logic gates and RTD circuit. RTD latch is formed by two RTDs in series; the one closer to the ground is called ‘drive RTD’ and the other one closer to the bias voltage is called ‘load RTD’. The state indicated by the data node voltage, which is 0 and 1, is specified by instantaneous voltage and current of drive RTD.
The current injected by load RTD to data node determines the final state of latch. If input current is close to the threshold current, then the final state is 1, otherwise it is 0. The advantages of latch RTD are it operates faster and it has low dissipation power. Figure 2.16 shows the schematic diagram of RTD and load-line diagram of two stable states.
Figure 2.16: (a) Schematic of RTD latch, (b) load-line diagram.
RTD logic gates are formed by RTD latch and enhancement-mode FET as source- follower buffer. This combination allows higher current and reduces switching time. Saturated resistor is added to improve RTD logic gates performance in which it acts as a current limiter. There are four types of RTD logic gates; DELAY, OR, XOR and AND gates. The fifth RTD logic gate, NOT gate, is implemented on the same XOR structure provided that one of the inputs is set to 1. Figure 2.17 shows the structure four types of RTD logic gates.
21
Figure 2.17: (a) Delay, (b) OR gate, (c) XOR gate (also NOT) (d) AND gate.
In RTD logic circuit design, shift registers operation is the best example to illustrate circuit logic design for RTD. Shift registers are made of two RTD DELAY gates which operate as master-slave D type flip-flop. Data is latched into first clock cycle and latched into slave in the other clock cycle. The schematic of RTD shift registers and overlapping clock waveforms are shown in Figure 2.18.
Figure 2.18: (a) RTD shift register schematic diagram, (b) simplified overlapping clock waveform.
22
However, there several problems that arise related to RTD and need further study as mentioned by Goldhaber-Gordon et. al. [1]: • RTD does not turn off the current completely when it is off-resonance which can lead to on state and off state cannot be distinguished. • RTD is very sensitive to current and voltage fluctuations and may cause easily to off-resonance. • Materials of RTD currently are not satisfied and hence different combination of semiconductor alloys is needed. • RTD also accumulates random background charges which in turn can trouble the device operation. • It is extremely difficult to make island and tunnel barrier uniformly and precisely. These are some of the drawbacks that arise related to RTD and that means there are still a lot of challenges lie ahead in order to realise RTD as a mass production device in the future.
2.3.3
Sub-10nm MOSFET Sub-10nm MOSFET is a nanoelectronic devices category that has good
compatibility with current fabrication process and design approach. This device has been investigated extensively through simulation as demonstrated by Guo [17], Huang, Zhang and Yang [18], which using Schottky Barrier MOSFET (SBFET). Others investigated ballistic MOSFET, which uses double-gate model, as presented by Ren [19], Naveh and Likharev [20] and Rahman [21]. Schottky Barrier MOSFET (SBFET) has a similar device structure to the conventional MOSFET, but the source/drain region is made of silicide or metal rather than heavily doped semiconductor [17]. The structure of SBFET is illustrated in Figure 2.19.
23
Figure 2.19: Double-gate SBFET with silicide/metal source and drain. SBFET has advantages in terms of fabrication process and device performance. In fabrication process, SBFET eliminates needs to have extremely high doping in source-drain region that is very challenging to do in nanoscale dimension. In view of device performance, SBFET delivers more on-current by eliminating parasitic resistance and also it has much lower leakage current. In simulation process [17], it is found that on-current of SBFET almost matches MOSFET on-current as the Schottkty barrier is reduced. It is concluded that negative Schottky barrier is needed to achieve high on-current value in SBFET.
Another approach to do simulation on SBMOSFET is by using metallic material for source and drain regions with intrinsic substrate is used to isolate the neighbouring electrodes [18]. It is concluded the tunnelling MOSFET is not affected by short channel effect and thus it promises further scaling to be less than 10nm. The tunnelling MOSFET must be supported by fully intrinsic substrate since doping cannot control characteristics of nanoscale transistor.
An interest in sub-10nm MOSFET is to study ballistic transport effect. Ballistic approach initially uses 1-D approximation for device electrostatics but this approach is found to be inaccurate because the effect of quantum tunnelling does not take into account. Model of simulation is based on dual-gate MOSFET with ultrathin undoped silicon channel connecting n-doped source and drain. It is concluded that for ultrathin channel transistor, it is still suitable choice for digital application, provided with good choice of oxide thickness.
24 2.3.4
Carbon nanotube field-effect transistor (CNFET) One of the promising nanoelectronic devices for nanotechnology era is
carbon nanotube field-effect transistor (CNFET) due to its superior both electrical characteristic. The structure of CNFET is almost the same as MOSFET but the silicon channel is replaced by semiconducting carbon nanotube. The cross section of CNFET structure is shown in the Figure 2.20 below.
Figure 2.20: Cross section of CNFET.
Carbon nanotube (CNT) is the most interesting carbon nanostructures with large application potentials. CNT is a hollow cylinder composed of one or more concentric layers of carbon atoms in honeycomb lattice arrangement [16]. The structure of CNT can be thought as a rolled graphite sheet to form a tube and the bond at the end of sheet forms the close of the tube as shown in Figure 2.21 below.
Figure 2.21: CNT structure.
The explanation of CNFET is very short in this chapter since CNT will be discussed in detail in Chapter 3 and CNFET is explained further in Chapter 4. This is because the focus of this thesis is to investigate the characteristic of CNFET.
25
2.4
Summary In this chapter, the development of scaling process of MOSFET for the past
30 years has been reviewed. It shows that due to aggressive approach of scaling process, the size of MOSFET has been reduced to almost 1/3 of its original size and at the same time density of integrated circuit is increased tremendously as a result of smaller size of MOSFET. Nevertheless, scaling process is now near its limit due to several factors that may deteriorate MOSFET performance and it is expected that scaling process may not be able to provide the same improvement as it has shown in the past.
Thus, several options of devices are proposed, known as nanoelectronic devices, which can replace MOSFET with smaller size, lower dissipation power, and higher on-current to support high-demand applications in the future. Among the nanoelectronic devices includes single-electron devices (SET), resonant tunnelling devices (RTD) and carbon nanotube field-effect transistor (CNFET). Each device has its own characteristics that can be applied in digital application as discussed in the earlier sections.
The next chapter will introduce the carbon nanotube in more detail including its structure, properties and growth. Although carbon nanotube is said to be the best candidate to replace silicon MOSFET, other nanoelectronic devices are also capable to do the same task but in different function and operation. Nevertheless, the successful era of MOSFET for decades is the essential factor to push the technology of digital applications nowadays.
CHAPTER 3
CARBON NANOTUBE STRUCTURES, PROPERTIES, GROWTH AND APPLICATIONS
In this chapter, basic issues regarding carbon nanotube are discussed since this material is the heart of carbon nanotube field-effect transistor, one of the nanoelectronic devices for future applications. In the subsequent sections, the structure, properties, growth process and applications of carbon nanotube is presented in short and simple explanation.
3.1
Background In 1991 a Japanese scientist, Sumio Iijima, studied the carbon soot created by
a direct current arc-discharge between carbon electrodes, he discovered a range of molecules that have been the object of intense scientific research ever since. Using a high-resolution transmission electron microscope (HRTEM), it is found that this long molecules consisting of several coaxial cylinders of carbon. This discovery drives the research field for carbon nanotube although the preparation of carbon filaments were already started in 1980’s and 1970’s through the synthesis of vapour grown carbon fibres [22].
The first carbon nanotube discovered is the multi-walled carbon nanotube, giving the remarkable structures and properties of carbon nanotubes that might give some unique applications. Less than two years later, single-walled carbon nanotube was
27 discovered by Iijima and his group through experiment work. The finding of SWNT is more important since the structure is more fundamental and became the basis for theoretical studies of large bodies.
3.2
Structure of Carbon Nanotube Carbon nanotube (CNT) is a hollow cylinder that composed of one or more
concentric layers of carbon atoms in a lattice arrangement [16]. Basically the structure can be divided into two categories; multi-walled nanotubes and singlewalled nanotubes.
3.2.1
Single-Walled Carbon Nanotube A single-walled nanotube (SWNT) is a graphene sheet that is rolled into a
cylindrical shape so that the structure in one-dimensional with axial symmetry. SWNT is generally has a diameter of 1 – 2nm and a length of up to 100 micrometers. SWNT can be classified into three types; armchair, zigzag and chirality. Armchair and zigzag nanotubes are also known as achiral SWNT since its mirror image is identical to the original structure. The name of armchair and zigzag come from the shape of cross-sectional ring as shown in Table 3.1.
On the other hand, chiral nanotubes exhibit spiral symmetry with its mirror image cannot be restructured from the original one. Figure 3.1 shows the terminations of these three types of SWNT and from this figure, it depicts the terminations are consist of hemisphere of fullerene [23]. This hemisphere, also called ‘cap’, contains six pentagons and an appropriate number of hexagons that perfectly fit the shape of the hemisphere.
These three types of SWNT depend on the chirality factor. The chirality is defined by a single vector called the chiral vector [23]. Figure 3.2 illustrates the
28 chiral vector as shown below. Vectors OA and OB defines the chiral vector Ch and translational vector. The chiral vector can be expressed in term of real state space unit vectors a1and a2. Ch = na1 + ma2, (n, m are integers, 0 ≤ |m| ≤ n) Table 3.1: Classification of carbon nanotube. Type
Shape of cross section
Chiral vector
Armchair
(n,n)
Zigzag
(n,0)
Chiral
Combination of armchair and (n,m) zigzag cross section
Figure 3.1: Three types of single-walled carbon nanotube.
Figure 3.2: The graphite sheet of a nanotube showing state vectors a1 and a2 and axis vector T about sheet is rolled.
29
Different way of rolling the graphite sheet will give different type of carbon nanotube as mentioned before. Assuming the graphite sheet is rolled about vector T, if vector T is parallel with C-C bond, armchair structure is obtained. In contrast, if vector T is perpendicular with C-C bond, then zigzag structure is attained. Otherwise, then chiral structure is formed if vector T is neither parallel nor perpendicular to C-C bond. The values of m and n are also related to which type of a specific nanotube structure. Armchair SWNT corresponds to the case n = m and zigzag corresponds to m = 0 whereas all other combinations lead to chiral nanotubes.
3.2.2
Multi-Walled Carbon Nanotube
Multi-walled carbon nanotube (MWNT) is the first nanotube found in 1991 by Iijima. Since then, the new era of research in carbon nanotube has started. A MWNT is composed of a set of coaxially arranged SWNT of different radii [24]. Distance between nearest neighbour shells is approximately about the van-der-Walls distance for two graphite carbon lattices which is about 3.4Ǻ. The outer diameter of MWNT is actually depends on the growth process and typically of order 20nm and up to 100nm. Figure 3.3 depicts the structure of MWNT.
Figure 3.3: Structure of multi-walled carbon nanotube.
30
There is a process to destruct the concentric shells in MWNT starting with the outer shell. This can be done by applying large current into the MWNT and hence the outer shell will have large portion of current flowing through. The concentric shell will eventually break as the current value exceeds 109 A/cm2. The breaking process of concentric shells is due to what is known as current induced electrical breakdown. The process is illustrated in Figure 3.4.
Figure 3.4: Current induced electrical breakdown process in multi-walled carbon nanotube.
3.3
Properties of Carbon Nanotube The reason why CNT is very suitable for future digital electronic application
is not due to its small size but its overall properties characteristics especially the electrical properties [16]. One of the properties of CNT is that its carrier transport is one-dimensional. This type of transport can suppress the scattering effect and at the same time can promote the ballistic transport. As a result, the power dissipation of CNT is very low.
The chemical bonds among the C atoms in CNT are satisfied and there is no need for passive dissipation of dangling bonds as in silicon. Thus the CNT-based electronic devices are not tied to use the SiO2 as the insulator but high dielectric constant and crystalline insulators can be used.
Another property of CNT is that CNT has a strong covalent bonding to give not only tremendous mechanical and thermal stability but a good resistance to
31 electromigration. In fact, the thermal conductivity in CNT is roughly twice of diamond [25]. Therefore, CNT can stand very high current density of up to 109 A/cm2. Another interesting property of CNT is its dimension does not controlled by fabrication process but it is totally determined chemically. These are some of the remarkable properties of CNT and hopefully the CNT-based devices can take advantage from these properties. The important electrical and mechanical properties are summarised in Table 3.2 below.
Table 3.2: Important electrical and mechanical properties of CNT. Electrical conductivity
Metallic or semiconducting
Electrical transport Energy gap Maximum current density Thermal conductivity Diameter Length Gravimetric surface E-modulus
Ballistic (no scattering) Eg (eV) ≈ 1/d (nm) ~1010 A/cm2 6000 W/km 1-100 nm Up to milimeters > 1500 m2/g 1000 GPa
In general, all the properties explained previously are related to single-walled CNT (SWNT). The electrical properties are coming from the graphene, the material that the CNT is made of. Graphene sometime known as zero-bandgap semiconductor since it is metallic in one direction and semiconducting in the other direction [26]. Thus, the electrical properties of SWNT can be classified into two categories; metallic and semiconducting.
Depending on how the graphene is rolled, it produces either metallic SWNT or semiconducting SWNT as shown in Figure 3.5 and Figure 3.6. As shown in both figures, armchair structure leads to metallic SWNT whereas zigzag structure leads to semiconducting SWNT.
32
Figure 3.5: Different rolling direction and resulting electrical conduction type.
Figure 3.6: Metallic SWNT has armchair structure and semiconducting has zigzag structure. The electrical properties of SWNT are also due to the electron confinement in nanotube [27]. There is only two movement allowed within the tube; forward and backward, plus the momentum conservation and energy. These factors help to reduce the scattering effect to take place in electron transport. Less scattering effect leads to reduce electrical resistance in nanotube and hence, CNT can carry current density of up to 109 A/cm2, 2-3 orders higher than metal such as Al and Cu. The electrical properties of metallic and semiconducting SWNT are discussed in the next section.
33
3.3.1
Electron transport in SWNT The model of electron transport in SWNT is very interesting to study
especially after semiconducting SWNT has been employed in field-effect transistor by Tans et. al. [28]. SWNT provides almost perfect model system for onedimensional conductors with electron-electron correlation affects the properties of conduction electrons. SWNT is also atomically uniform, structurally robust and chemically inert [29]. In general, electron transport in SWNT is ballistic, negligible scattering effect since the scattering is longer than electronic distance. This is because very few defect and impurities found in SWNT.
Stable carbon-carbon bonds limits electromigration to occur and hence greater current density is allowed in SWNT, which is about 10µA/nm2 compared to 10nA/nm2 in metal wires. This makes SWNT suitable for demanding digital applications since it supports high current density transport
The device geometry used to investigate the electrical transport in SWNT is the almost same as the structure of field-effect transistor as shown in Figure 3.7. The silicon gate is used to modulate the carrier density of the nanotube. Transport characteristic at room temperature shows two different types. The first one shows weak or no gate voltage dependence of linear response conductance whereas second type has strong gate voltage dependence. The former type indicates that the nanotube is metallic whereas the latter type indicates the nanotube is semiconducting [29].
34
Figure 3.7: Typical device geometry for electrical transport measurement.
3.3.2
Electron transport of MWNT All of the properties that have been described so far are related to single-
walled CNT (SWNT). The electrical properties of multi-walled CNT (MWNT) are actually little bit different from the SWNT. The reason behind this difference is following the complex structure of MWNT [16]. The structure composed of carbon shells with different electronic character and chirality and also the presence of shellshell interactions. MWNT generally shows one-dimensional or two-dimensional transport depending on the diameter. The electrical conduction is determined by the outer shell of MWNT at low temperature and side-bonded to metal electrodes.
3.4
Growth of Carbon Nanotube There are four growth process of CNT discussed in this section; chemical
vapour deposition (CVD), arc-discharge, laser ablation and gas phase catalytic. This section does not intended to give every single detail of each process but only to give an overview of how the process to produce CNT takes place. Among these four processes, CVD turns out to be the most effective way of producing CNT compared
35 to other three. However, several problems have to be considered in CNT growth issue. These problems includes to produce defect-free nanotubes at macroscopic length and to control the nanotube growth on surfaces. The next four sub sections will explain these growth processes.
3.4.1
Chemical Vapour Deposition Chemical vapour deposition (CVD) had been used to produce carbon fibres,
filament and nanotube materials since 10-20 years ago. The process growth in CVD involves heating a catalyst material at high temperature in a tube furnace and at the same time hydrocarbon gas is allowed to flow through the tube reactor for a specified period of time [30]. The materials grown over the catalyst are then collected when the system is cooled at room temperature. The schematic setup for CVD growth is shown in Figure 3.8.
Oven temperature 500 - 1000 °C Figure 3.8: Schematic setup for chemical vapour deposition.
Hydrocarbon, catalysts and growth temperature are the important specification in CVD growth. CVD process involves the dissociation of hydrocarbon molecules catalysed by transition metal, followed by dissolution and saturation of carbon atoms in metal electrode in order to growth nanotube. CVD process is used to grow SWNT using a combination of electrolytic and lithographic approach to control location and orientation of growth [16]. The process involves patterning silicon surface layer lithography and electrolytically etching silicon to form porous silicon
36 on sidewalls. This is followed by photoresist process and finally exposed to metal catalyst and reacting with methane at ~1000°C.
Another approach of CVD growth for SWNT needs methane as source of carbon, temperature range of 850 - 1000°C and the same catalyst used in MWNT [30]. These setting will grow high quality SWNT since the high temperature forms nanotube with small diameter and high strain energy, near defect-free crystalline structures. Methane is the most stable at high temperature and this also helps to avoid self-decomposition in CNT growth. The SWNT grown from CVD process is shown in Figure 3.9 and the lithographic process in CVD is shown in Figure 3.10.
Figure 3.9: Top and side view of grown CNT.
Figure 3.10: The process step to produce SWNT by CVD process using methane as source of carbon.
37 For MWNT growth process, the process employed iron, nickel and cobalt as catalyst and the temperature is between 550 – 750°C. At very high temperature, the process will lead to metal-carbon solution formation. The main disadvantage of CVD process in MWNT growth is that the structure has high defect density, which is believed to be due to low temperature during the process. Low temperature might cause insufficient thermal energy supplied to form perfect crystalline structures.
3.4.2
Arc Discharge Arc-discharge growth process is another growth process developed to
produce high quality of MWNT and SWNT. MWNT is produced by controlling the growth condition such as pressure of inert gas in discharge chamber and the arcing current. MWNT was first obtained from arc-discharge in 1992 at the gram level [30]. The MWNT produced by arc-discharge is straight with length on order of micrometer and diameter in range 5-30 nm. However, there are defect exists such as pentagons and hexagons present at the nanotube walls.
Metal catalyst is needed for SWNT growth in arc-discharge process. The first SWNT produced by arc-discharge is produced in 1993. A carbon anode that contains a small cobalt catalyst in discharge experiment and SWNT is obtained in the soot material. Figure 3.11 below depicts the apparatus for arc-discharge process.
Figure 3.11: Apparatus for arc-discharge.
38
3.4.3
Laser Ablation Laser ablation process has something in common with arc-discharge process.
Both processes involve carbon atoms condensation generated from evaporation of carbon solids and the process temperature is also very high ~3000-4000°C [31]. This method used laser pulses to ablate a carbon target that placed in tube-furnace at 1200°C to produce SWNT. A flow of inert gas is allowed to pass through the chamber in order to collect nanotube at downstream. The produced SWNT normally in the form of ropes consists of tens of nanotubes. Figure 3.12 shows single-walled carbon nanotube produced by laser ablation.
Figure 3.12: Single-walled carbon nanotube produced by laser ablation.
3.4.4
Gas-phase Catalytic Reaction between hydrocarbons or carbon monoxide with catalyst particles is
another way to grow nanotube. This process, known as gas phase catalytic, can be used to grow a bundle of SWNT. The carbon source is carbon monoxide and the temperature is about 1200°C with iron is used as the catalyst in the process [30]. Carbon monoxide is a stable molecule but it is not an efficient carbon source for nanotube growth. However, to enhance the SWNT grow, the carbon monoxide is put at high pressure of up to 10 atm to speed up disproportion carbon molecules into carbon. SWNT produced by this process is about 0.7nm in diameter, the same as C60 molecule.
39
Methane can be used to substitute carbon monoxide to provide an efficient way to produce SWNT. Experimental work by Nikolaev et. al. [32] shows that this process can be used to produce variety of SWNT yield and diameter distribution by controlling the process parameters. This result reveals distinct difference with other growth processes, which is producing SWNT in a continuous-flow process rather than a batch process.
3.5
Carbon Nanotube Applications
3.5.1
Electronic device Normally, semiconductors are used for metal-semiconductor diodes, pn
junction diodes and field-effect transistors whereas metals are used for wiring interconnections. The same scenario is also applied to carbon nanotube, which semiconducting nanotubes are used for field-effect transistor and metallic nanotubes are used for interconnections.
An FET can be built using semiconducting CNT with significant gate modulation effects. This device has a three-terminal structure and CNT is used as channel to conduct current flow. Back-gated structure was employed in the early stage with CNT is placed on an oxidised silicon substrate. Source and drain electrodes are placed on the nanotube as shown in Figure 3.13. The drain current is found to have very strong dependence on gate voltage when drain voltage is held constant and this modulation effect gives the signal gain. Some fundamentals properties have been studied such as subband formation in the channel, long-channel behaviour and use of electrolyte gate. Carbon nanotube field-effect transistor (CNFET) will be discussed in detail in Chapter 4.
Metallic CNT is also suitable for signal and power interconnection since they are capable of carrying very large current density. Since copper is vulnerable to
40 electromigration when current density is very high, therefore CNT-based interconnection gives a good solution.
Figure 3.13: CNT-based field-effect transistor.
3.5.2
Chemical and Physical Sensors Chemical sensors are widely used in monitoring and controlling
environmental pollution, diagnostics in medical applications, and implementing detection of warfare and security threats. CNT has the potential in this application based on the changes in specific properties such as conductivity change in CNT, frequency change and scattering of light due to chemical adsorption. CNT-based chemical sensors can be divided into several categories as shown in Figure 3.14 below.
Figure 3.14: Category of CNT-based chemical sensors.
41
Electrochemistry is a process of transferring charge from one electrode to another. This means that at least two electrodes constitute an electrochemical cell in order to form a closed loop electrical circuit. Cylindrical sheet of CNT has asymmetric distribution of electrons inside and outside the sheet, thus makes the CNT electrochemically active. Electron donor and acceptor elements will either donate or withdraw electrons from CNT and hence giving CNT more electrons or holes respectively to change CNT conductivity. Chemiresistors is a typical example of electrochemistry sensors. Chemiresistors are sensors that measure current change before and during exposure of chemical species while a constant voltage is applied across two sensing materials. Chemisresistors, as depicted in Figure 3.15, are simple two-terminal devices compared to three-terminals of CNFET. These devices are fabricated on an interdigitated electrode and can be used for gas detection at room temperature.
Figure 3.15: Equivalent circuit of chemiresistor.
Thermal sensors are devices are based on the heat generated by a specific reaction as the source for chemical information. The strategy is to put the chemically selective layer on top of thermal probe and measure if there is a change in temperature. In this device, CNT acts as thermally sensitive layer and it measures the change in thermoelectric power during gas exposure.
Resonator is a device that provides frequency signal to reflect the chemical information around the device. The structure of this device, as shown in Figure 3.16, consists of a layer of insulating material, a layer of conducting material and a layer of
42 sensing material. The equivalent circuit of this device can be modelled as Butterworth-Van Dyke circuit as given in Figure 3.17. In this equivalent circuit, the electrical admittance, Y(f), is given as Y(f) = jωC 0* +
1 Zm
where Zm is the electrical impedance for unperturbed resonator.
Figure 3.16: Structure of CNT-based resonator
L1
C 0*
C1
R1
Figure 3.17: Equivalent circuit model to describe electrical characteristic of resonator with no load condition.
Optical sensor operates on the basis of the interaction between sensing material and chemical species causing a change in optical properties. In this device, the optical beam is guided out of spectrophotometer to interact in the sample and
43 reintroduced in the spectrophotometer for further processing. These are all basic explanation on the application of CNT-based chemical sensor devices.
The CNT-based physical sensor can be categorised into flow sensor, electromechanical actuator, vision sensor and acoustic sensor. Flow sensor is based on the generation of current or voltage in a bundle of SWNT. The generation of electric current in the CNT is due to the transfer of momentum from the flowing liquid molecules that creates dragging effect on free-charge carriers in the nanotube. The magnitude of current/voltage is also affected by the ionic strength of the flowing liquid. Figure 3.18 depicts the structure of CNT-based flow meter.
Figure 3.18: Structure of CNT-based flow meter
Electromechanical actuators are used to convert directly electrical energy into mechanical energy through a metal response. CNT-base electromechanical actuators are found to have higher stresses than natural muscle and higher strains than highmodulus ferroelectrics. The nanotube sheet actuators are arrays of nanofiber actuators to provide a novel type of actuation. Figure 3.19 shows the schematic of charge injection in a nanotube-based electromechanical actuator.
44
Figure 3.19: Charge injection on CNT-based electromechanical structure
Band gap of semiconducting CNT is closely related to its diameter and chirality and this property makes CNT very suitable for infrared (IR) sensors. IR devices based on CNT is desirable since it offers large area, ordered and well-aligned high-density arrays. The basic cell of CNT-based IR detector array is illustrated in Figure 3.20 that is composed of MWNT. The operation of this device is realised by absorbing the incident radiation by a group of MWNT that acts as a single pixel in the array. The absorption process will change the conductivity of the cell and this change is used to detect IR radiation. This device is still under conceptual stage and development work is focused on how to reduce dark current and increase the absorption rate.
Figure 3.20: Basic cell of IR detector
CNT is also can be implemented in acoustic device to detect sound. This device, composed of MWNT array, transforms the acoustic energy into electrical form and can be transmitted in electrical transmission. The property of MWNT, which is naturally directional, provides directional information from a single sensor
45 although it contains much fainter sound. This sensor will enable micro-actuators and micro-sensors in gas and liquid environment.
3.6
Summary In this chapter, carbon nanotube is explained in terms of its structure,
properties and also the growth process. Carbon nanotube (CNT) is a honeycomb lattice rolled into a cylinder with its diameter size in nanometre scale and the length can be up to one micrometer. The diameter size of CNT is the smallest size of semiconductor devices so far.
The structure of CNT is classified based on its geometry and also due to its electrical properties. The first classification of CNT is presented based on the geometry structure. In general, CNT can be divided into three types based on the structure called armchair, zigzag and chiral. This classification is based on the shape of cross section of the nanotube. The difference of cross section is due to the different direction of rolling graphene sheet to form the nanotube.
Another classification of CNT is based on the electrical properties of the nanotube. There are two types of CNT; semiconducting and metallic. The metallic CNT is always has armchair structure whereas the semiconducting CNT has the zigzag structure. Metallic CNT can be used electrical interconnection as copper wire and semiconducting can be used as channel in field-effect transistor.
The overall of electrical property of CNT is very interesting to be exploited. The electron transport is ballistic and hence, less resistance exists due to less scattering effect occurs in the nanotube. High electrical density of up to 109 A/cm2 is also observed as a result of little electrical resistant. These properties are very suitable for future digital applications that require very high demand.
46 Next, the growth process is presented concisely to give an overview of how nanotube is produced. There are four processes presented altogether; chemical vapour deposition (CVD), arc-discharge, laser ablation and gas phase catalytic. Among these four processes, CVD is the most effective way to produce the nanotube and it is widely used compared to other processes. Nevertheless, there are room to improve the process in order to produce better outcome from the growth process.
Finally, the applications of CNT are covered to show how the property of CNT can be exploited in the industry. Two types of applications are discussed, in terms of electronic devices and sensors. CNFET is the most popular application of CNT since this device is predicted to outperform MOSFET in the future and the other application is electrical interconnection using metallic CNT. CNT-based sensors described in this chapter are chemical and physical sensors. These sensors provide accurate tools that can be used in industry, biological and even in medical applications.
CHAPTER 4
CARBON NANOTUBE FIELD-EFFECT TRANSISTOR
This chapter explores the insights of the most outstanding application of carbon nanotube in electronic field, the carbon nanotube field-effect transistor (CNFET). The motivation of research in CNFET is fuelled by the unique electrical characteristics of carbon nanotube especially the semiconducting characteristic. Besides, the continuous effort to find future nanoelectronic device that can perform as excellent as MOSFET also push the research of CNFET to be more aggressive. The first section gives an overview of the structure of CNFET followed by the explanation of CNFET operation as a switching device. The next section provides the comparison between CNFET and MOSFET and the final section presents the application of CNFET in digital electronic.
4.1
Structure of CNFET The structure of CNFET basically resembles the structure of MOSFET except
that the silicon channel is replaced by the carbon nanotube. Nevertheless, the arrangement keeps changing in order to improve the performance of the device. In this section, the structure of CNFET will be discussed. The structure can be categorised as back-gated CNFET, top-gated CNFET and recently a new structure has been introduced known as vertical CNFET.
48 4.1.1
Back-gated CNFET CNFET was first demonstrated in 1998 by Tans et. al. [28] to show a
technologically exploitable switching behaviour and this work marked the inception of CNFET research progress. Experimental work by Tans et. al. managed to modulate the conductivity more than five orders of magnitude by applying electrical field to the nanotube [24]. Majority of the early CNFET devices were back-gated with very thick gate insulators made of silicon oxide approximately around 100150nm [16]. This structure used a non-local back-gate with the carbon nanotube side is bonded to noble metal electrodes [33]. Noble metal is a type of metal that resists the attack of acids and other reagents and does not corrode. The image of back-gated CNFET and its schematic cross section of are shown in Figure 4.1 and Figure 4.2 respectively.
Figure 4.1: Image of back-gated CNFET.
Figure 4.2: Schematic cross section of back-gated CNFET. This premature formation results poor characteristics such as low drive current, low transconductance (10-9S) and large contact resistances (>1MΩ) [26]. The unsatisfactory characteristics are due to the bad contacts since the carbon
49 nanotube is just simply laid on the gold electrodes and held weakly by the van der Waals force [16]. The performance can be improved by increasing the gate capacitance by reducing the insulator thickness or increasing the dielectric constant. However, the calculation for gate capacitance of CNFET is different from MOSFET. The introduction of Al2O3 layer on top of patterned Al gate is able to lower the gate voltage and increases the transconductance [24]. Further improvement is followed by the inauguration of top-gated structure. It is needed that each CNFET to be gated individually in order to have a complex integrated circuit.
4.1.2
Top-gated CNFET The next generation of CNFET came in top-gated structure to improve the
device performance. Since the performance in back-gated structure is rated quite poor in terms of the device operation, thus this new structure is expected to bring better result. This structure is fabricated by dispersing the carbon nanotube on an oxidised wafer [16]. Atomic force microscopy (AFM) image is used to identify the single carbon nanotube and then the source and drain terminals, which made of Ti, are fabricated on top of the carbon nanotube. A 15-20nm gate dielectric film is deposited at 300°C through chemical vapour deposition (CVD) process. Finally, a 50-nm-thick gate electrode is patterned by lithography. Figure 4.3 depicts the structure of top-gated CNFET.
Figure 4.3: Top-gated structure of CNFET.
50 This structure gives better out-turn than early structure. The improvement comes from the scaling of the dimension and the adoption of better device geometry as well as the device performance [33]. For example, the electrical field is increased due to the device geometry and contact resistance is reduced by choosing a suitable of contact material. Besides, the threshold voltage is significantly lower than backgated structure, drive current is much higher and transconductance is similarly high (3.35µS per nanotube).
4.1.3
Vertical CNFET The latest development in CNFET progress could be the initiation of vertical
CNFET. This structure with surround-gated is suggested by Choi et. al. in 2004 [34]. The transistor size can be as small as the diameter of carbon nanotube which corresponds to tera-level CNFET and density of 1012 elements per cm-2. The vertical CNFET is prepared through the following steps: nano-pore formation by anodization followed by synthesizing the carbon nanotube, metal-electrode formation, oxide deposition and patterning and finally gate electrode formation. The silicon oxide was deposited at the top of aligned carbon nanotube by electron gun evaporation and followed by holes formation of e-beam patterning and chemical etching. The silicon oxide deposition process is then followed by deposition of top gate electrode. The structure of vertical CNFET is illustrated in Figure 4.4.
Figure 4.4: Device structure of vertical CNFET.
51 In this structure, each carbon nanotube is electrically attached to bottom electrode, source, upper electrode (drain) and gate electrode is put around the carbon nanotube. Each cross point of source and drain electrodes corresponds to a transistor element with a single vertical carbon nanotube. The number of carbon nanotube in transistor depends on the hole-diameter of gate oxide. The vertical CNFET allows higher packing densities that can be achieved since source and drain areas can be arranged on top of each other [24]. On the other hand, real 3-D structures can be made possible because the active devices are no longer bound to the surface of mono-crystalline silicon wafer. Another view of vertical CNFET is shown in Figure 4.5.
Figure 4.5: Another view of vertical CNFET.
4.2
Operation of CNFET Basic principle operation of CNFET is the same as MOSFET where electrons
are supplied by source terminal and drain terminal will collect these electrons. In other words, current is actually flowing from drain to source terminal. Gate terminal controls current intensity in the transistor channel and the transistor is in off state if no gate voltage is applied. In this section, the operation of two different structures is discussed. The first structure is known as Schottky-barrier CNFET and the other one is MOSFET-like CNFET. The structure between these two CNFET is only slightly different but results in different transistor operation.
52 4.2.1
Schottky-barrier CNFET Normally, a potential barrier known as Schottky barrier (SB) exists at every
contact between metal and semiconductor. The barrier height is determined by the filling of metal-induced gap states. These states become available in the energy gap of semiconductor due to interface formed with the metal. The SB is controlled by the difference of the local work functions of the metal and the carbon nanotube. SB is also extremely sensitive to changes of local environment at the contact [35]. For example, gas adsorption changes the work function of metal surfaces. Since this device employs metal as its source/drain terminals and has Schottky barrier at its terminal contact between nanotube and metal, therefore it is called Schottky-barrier CNFET (SB-CNFET). Diagram of SB-CNFET is shown in Figure 4.6 below.
Figure 4.6: Diagram of Schottky-barrier CNFET (SB-CNFET).
SB-CNFET works on the principle of direct tunnelling through the Schottky barrier at the source-channel junction. The barrier width is controlled by the gate voltage and hence the transconductance of the device depends on the gate voltage. At low gate bias, large barrier limits the current in the channel. As gate bias is increased, it reduces the barrier width, which increases quantum mechanical tunnelling through the barrier, and therefore increases current flow in transistor channel. In SB-CNFET, the transistor action occurs by modulating the transmission coefficient of the device.
SB-CNFET shows very strong ambipolar conduction particularly when the gate oxide thickness is reduced (ambipolar conduction will be explained in section 4.3), even the Schottky barrier is zero [36]. This type of conduction causes leakage
53 current to increase exponentially with supply voltage especially when the nanotube diameter is large, which results in limiting device potential. Thus, ambipolar conduction must be reduced in order to improve the performance of SB-CNFET. One of the solutions is to increase the gate oxide thickness. If the gate oxide thickness is high, there is no ambipolar conduction exists when Schottky barrier is zero. Hence, the leakage current is reduced and as a result, the transistor performance is improved. Another alternative is to build asymmetric gate oxide, which is has been proposed recently, in order to suppress the ambipolar conduction [37].
Another issue regarding on SB-CNFET is that this type of transistor suffers from metal-induced-gap states which limit minimum channel length and thus increases source to drain tunnelling. SB-CNFET is also unable to place gate terminal close to source because it can increase parasitic capacitance.
4.2.2
MOSFET-like CNFET The structure of this device is slightly different than SB-CNFET since it used
heavily doped terminals instead of metal. This device is formed in order to overcome problems in SB-CNFET by operating like normal MOSFET. Unlike SB-CNFET, source and drain terminals are heavily doped like MOSFET and hence it is called as MOSFET-like CNFET. This device, as shown in Figure 4.7, operates on the principle of modulation the barrier height by gate voltage application. The drain current is controlled by number of charge that is induced in the channel by gate terminal.
Figure 4.7: Diagram of MOSFET-like CNFET.
54
This type of transistor has several advantages over SB-CNFET. This device is able to suppress ambipolar conduction in SB-CNFET. It also provides longer channel length limit because the density of metal-induced-gap-states is significantly reduced. Parasitic capacitance between gate and source terminal is greatly reduced and thus allows faster operation of the transistor. Faster operation can be achieved since length between gate and source/drain terminals can be separated by the length of source to drain, which reduces parasitic capacitance and transistor delay metric. It operates like SB-CNFET with negative Schottky barrier height during on-state condition and thus it delivers higher on-current than SB-CNFET.
Previous work has shown that this type of device gives higher on-current compared to SB-CNFET and therefore it can justify the upper limit of CNFET performance. Based on the device performance, it is obvious that this device can be used to investigate the ballistic transport in CNFET.
4.3
P-type versus N-type CNFET CNFET are typically p-type, which means they are modulating current in the
channel when negative gate voltage is applied to the device. For p-type operation, when negative gate voltage is applied, it will conduct current in the channel from source to drain and this current is due to holes movement. In contrast, an n-type CNFET conducts whenever a positive gate voltage is applied to the device, which is the current flow in the channel from source to drain is due to the conduction of electrons. In short, CNFET delivers current either a positive or negative gate voltage is applied. This characteristic, allowing both holes and electrons conduction in the same device, is called ambipolar characteristic. Thus, CNFET is an ambipolar device since it conducts current either in negative or positive supply voltage.
Normally, when CNT is used to produce CNFET without any further processing, the devices are invariably p-type. Thus, in order to produce n-type
55 CNFET, another process is needed. There are two ways of producing n-type CNFET from p-type CNFET. The conversion process can be made possible either annealing or doping process.
Annealing is a process of converting p-type CNFET into n-type CNFET through vacuum annealing. In this process, p-type CNFET is heated under vacuum to desorb any adsorbed gas such as oxygen and at the end of this process, the p-type CNFET is converted into n-type CNFET. This conversion process is reversible because if n-type CNFET is exposed to air, the device will return to its original ptype characteristic. The process of annealing is graphically shown in Figure 4.8 below.
Figure 4.8: Characteristic of CNFET due to annealing process.
Another process is called doping process, which the p-type CNFET is doped using electron donors such as alkali metals is depicted in Figure 4.9. Alkali metals, such as potassium, will give the same result as in annealing process with p-type CNFET is transformed into n-type CNFET. Conversion process from p-type to ntype and vice versa is very important especially to develop nanotube complementary logic circuits. Since both p-type and n-type CNFET are needed to build complementary logic circuits, thus this conversion process gives a solution to build nanotube-based logic circuit.
56
Figure 4.9: CNFET characteristic due to exposure to potassium atom.
4.4
Application of CNFET The leading motivation of building CNFET is to use this device in digital
application. Thus, the obvious application of CNFET should be to be used in constructing logic gates. This is the development step in involving carbon nanotube in digital application by integrating CNFET as a logic gate; the basic component in computer. The establishment of logic gates from CNFET will become a benchmark on the suitability of CNFET in digital electronics.
In order to build logic gates from CNFET, both p-type and n-type CNFET are needed. Since most of CNFET produced are p-type, there is less difficulty in getting this type of device. However, p-type CNFET can be changed to n-type by annealing them in vacuum or by direct doping with electropositive element such as potassium. This process shows that p-type character is not an intrinsic property of CNFET.
There are two types of logic gates produced from CNFET, intermolecular and intramolecular logic gates [36]. Intermolecular logic gates are formed by assembling both p-type CNFET and n-type CNFET on the same substrate. The intramolecular logic gate, on the other hand, is produced by fabricating complementary CNFET (p-
57 type and n-type) on a single nanotube. Fabrication process of both intermolecular and intramolecular logic gates described in [36].
To fabricate intermolecular logic gates, first one of two p-type CNFETs are protected by a polymer film known as poly methyl methacrylate (PMMA). PMMA is a type of plastic that is used as a shatterproof replacement for glass and it has a very high transparency. PMMA is preferable than glass since it is lighter and does not shatter. Next, both are converted to n-type after vacuum annealing. The device is exposed to 10-3 Torr of oxygen for three minutes which turns the unprotected n-type CNFET into original p-type while the protected n-type remains. For intramolecular logic gates, a p-type CNFET is covered by PMMA and then a window is opened through e-beam lithography. Half of CNFET is turned into n-type CNFET by doping of potassium through the window. The schematic of intermolecular logic gate and AFM image of intramolecular logic gate is illustrated in Figure 4.10 and Figure 4.11 respectively.
Figure 4.10: Schematic diagram of intermolecular logic gate.
Figure 4.11: AFM image of intramolecular logic gate.
58
By bonding together a p-type and n-type CNFET, a ‘NOT’ gate or voltage inverter is produced; the first logic gate based on carbon nanotube [36]. The NOT gate is a fundamental logic gates that can be used to build all other logic gates, provided it is used along with ‘AND’ gate. The logic gates produced with carbon nanotube works the same way as silicon logic gates. The input voltage is applied simultaneously to the gates of two complementary CNFETs with p-type is polarised by a positive voltage and n-type by a negative voltage. Positive input voltage turns the n-type ON and results negative polarisation voltage at output. In contrast, a negative input voltage turns ON p-type and results positive output voltage. Thus, the characteristic exhibited by this device is the voltage inverter or logic NOT.
An alternative way to produce logic gate is using a logic scheme called resistor-transistor logic [37]. In this scheme, all p-type CNFETs are fabricated on the same chip with voltage of 0V represents logic 0 and voltage of -1.5V represents logic 1. There are two logic circuit produced using this scheme, NOT and NOR gate.
An inverter or NOT gate is build from a CNFET and a 100MΩ resistor. When the input is logic 1, the negative gate voltage pulls holes into CNFET and giving the resistance lower than bias resistor. This pulls the output to logic 0, which corresponds to 0V. When the input is at logic 0, the CNFET is non-conducting and hence the output is pulled to -1.5V, representing logic 1.
A NOR gate is constructed by substituting single CNFET in inverter with two CNFETs in parallel. When either or both of the inputs are at logic 1, the output is pulled to 0V that corresponds to logic 0. When the inputs is at logic 0, none of the CNFET is conducting and therefore the output is pulled to logic 1. Figure 4.12 and Figure 4.13 shows the schematic of NOT gate and NOR gate respectively.
59
Figure 4.12: Schematic of CNFET-based NOT gate.
Figure 4.13: Schematic of CNFET-based NOR gate.
4.5
Summary In this chapter, several basic principles of CNFET are explained. Starting
with various types of CNFET structure, followed by the operation of CNFET and finally the examples of CNFET application are also discussed. From this chapter, it can be seen that from CNFET structure and its behaviour, this device is actually more or less the same as MOSFET except that the material for transistor channel is changed from silicon to carbon nanotube.
The early structure of CNFET, known as back-gated, follows almost the same structure of MOSFET but the source/drain terminals are made of noble metal, such as gold, and later the structure changes to top-gated in order to improve its performance. Finally, vertical structure comes with a possibility that the size of transistor can be as small as the diameter of the nanotube.
The operation of CNFET is dominated by Schottky barrier due to contact between the nanotube and metal terminals of the transistor. Since early structure of CNFET used metal as its terminals, therefore this type of barrier cannot be avoided.
60 This type of transistor, called SB-CNFET, shows strong ambipolar characteristics especially when the gate oxide is thin. This situation result in high leakage current in the transistor that limits the device performance. Hence, another type operation called MOSFET-like CNFET comes to overcome the handicapped in SB-CNFET. It reduces the leakage current in the transistor, suppresses ambipolar characteristic and reduces parasitic capacitance to get faster operation.
Conversion process of p-type CNFET to n-type CNFET provides a solution to build a complementary logic circuit. Since CNFET are typically p-type, therefore there should a way to produce n-type CNFET in order to build nanotube-based logic circuit. Annealing process is simpler than doping process and this process is reversible. Doping process, on the other hand, is also an effective way to produce ntype CNFET.
Finally, the application of CNFET is presented. CNFET itself cannot give any significant in electronic field without building CNFET-based circuit. Intramolecular and intermolecular circuits are the examples of CNFET-based circuit. This circuit is used to get logic gates such as AND, NOT and other gates. Another scheme called resistor-transistor logic is also enable building such logic circuit to be made possible.
CHAPTER 5
RESULT AND ANALYSIS
This chapter explains the methodology used in this project, simulation model used for simulation study, simulation result obtained and finally the analysis and discussion on the result.
5.1
Methodology
This project involves simulation study to investigate the I-V characteristic of CNFET. The simulation study is carried out using MATLAB based on surfacepotential model described by Rahman et. al. [21]. This is a simple, analytical model that can be used to investigate the I-V characteristic of CNFET. The model used MOSFET-like structure in order to investigate ballistic transport in CNFET since this structure is proved experimentally that it could achieve near ballistic transport. The analysis starts at the top of the energy barrier since current remains the same throughout the channel and all scattering mechanism is neglected. At any specified drain/gate voltage, the drain current is calculated based on the total charge that occupied first subband in the nanotube. The process is repeated for all drain/gate voltage in the specified range before all the drain current values are plotted within a single graph.
The model for ballistic CNFET consists of three capacitors, which represents three transistor terminals on potentials at top of barrier. As shown in Fig. 5.1, the shaded region indicates mobile charge at top of the barrier. The mobile charge is
62 determined by the local density of states at top of the barrier, location of source and drain levels, EF1 and EF2, and self-consistent potential at top of the barrier, Uscf.
Figure 5.1: The simulation model for ballistic CNFET.
The process of calculating the drain current is as follows: i) Consider a value of VG, VD, VS and EF1. For simplicity, VS is grounded as potential reference. ii) Compute the total charge on nanotube channel. The charge at top of the barrier contributed from source and drain are given as
N1 =
N2
D(E ) 2
D(E ) = 2
∞
∫ f (E + U
)
(1)
)
(2)
scf
− E F1 dE
scf
− E F2 dE
−∞ ∞
∫ f (E + U
−∞
where N1 represents positive velocity states filled by source and N2 represents negative velocity states filling by drain, EF1(F2) is the source (drain) Fermi level, f(E) is the probability that a state with energy E is occupied (Fermi-Dirac probability), D(E) is the nanotube density of states (DOS) at top of the barrier and Uscf is selfconsistent potential at the top of the barrier. For simplicity, assume source Fermi level as the reference, thus EF1 = 0 and EF2 = –qVDS where q is electronic charge.
63 iii) Uscf must be evaluated in order to solve for charge density at top of the barrier. Uscf can be solved by using superposition. First, Laplace potential is calculated using U L = − q(α G VG + α D V D + α S V S )
(3)
CG C C , α D = D , αS = S CΣ CΣ CΣ
where α G =
Next, potential due to mobile charge is computed as UP =
q2 CΣ
(N 1
∞
∫ D ( E ) f (E − E
where N 0 =
F
+ N 2 ) − N0
(4)
)dE
−∞
Thus, Uscf is found by adding both equations (3) and (4) Uscf = UL + UP = − q (α G VG + α DV D + α S V S ) +
q2 CΣ
(N 1
+ N 2 ) − N0
(5)
iv) Drain current is computed by using formula ID =
[(
(
4qk B T ln 1 + exp E F! − U scf h
)) − ln(1 + exp(E F2
− U scf
))]
(6)
where kB is Boltzman constant, T is operating temperature and h is Planck’s constant. (v) By repeating step (i)-(iv) for a set of (VG, VD) points, the ID(VG, VD) characteristics can be determined.
The detail of mathematical equation is given in Appendix B. The whole process of drain current calculation can be summarised in flow chart as shown in Figure 5.2. The simulation process described above is then implemented in MATLAB program. When the calculation process is written in the MATLAB program, obviously it needs more steps such as declaration of physical constant and input variables. The flow chart of drain current calculation process in MATLAB is shown in Figure 5.3.
64
Figure 5.2: Flow chart of simulation process.
65
Figure 5.3: Flow chart of simulation process in MATLAB program.
5.2
Result
The result obtained from the simulation is I-V characteristic of CNFET. There are two plots obtained; ID vs. VD and ID vs. VG. These two plots will describe the I-V characteristic of CNFET since it shows how the drain current changes correspond to drain/gate voltage change. The structure used in this simulation is MOSFET-like CNFET with coaxial gate terminal as depicted in Figure 5.4. Both source and drain terminals are made of heavily-doped n-type CNT.
66
Figure 5.4: Structure of simulated ballistic CNFET.
The result obtained is based on the assumption that the CNT diameter is 1nm and gate oxide thickness is 1.5nm. The plot of ID vs. VD as shown in Figure 5.5 is almost the same as MOSFET characteristic. In Figure 5.6, the drain current is plotted on logarithmic scale whereas the gate voltage is in linear scale. This graph provides more significant value of leakage current, i.e. the drain current when gate voltage is zero. The IOFF level from the graph is between 2x10-5µA and 8x10-5µA.
Figure 5.5: Plot of ID vs. VD.
67
Figure 5.6: Plot of ID vs. VG.
5.3
Analysis
In this section, analysis on the simulation result for I-V characteristic of CNFET is presented. In the first part, comparison of device performance between CNFET and MOSFET is made and then the following analysis is to study the effect of gate oxide thickness and CNT diameter on drain current level.
5.3.1
Comparison with MOSFET
In order to evaluate CNFET performance, it is essential to make a comparison with MOSFET performance. In this analysis, comparison analysis is between CNFET and ideal 10-nm ballistic MOSFET. For CNFET, it is assumed that the diameter of CNT is 1nm and insulator thickness is 1.5nm. It is needed to compare a dimensionless parameter or with the same dimension parameter. In this case, ION/IOFF ratio is taken as the comparison parameter.
68
To compare device performance between CNFET and MOSFET, simulation result of ideal sub-10nm MOSFET done by Rahman et.al. is taken as a benchmark. The simulation result obtained on ideal sub-10nm MOSFET for ID vs. VD and ID vs. VG is shown in Figure 5.7 and 5.8 respectively. From this result, at gate voltage 0.6V, it is found that on-current is given as 1400µA/µm and leakage current is about 5x10-3µA/µm. Thus, from these drain current values, the ION/IOFF ratio obtained is about 2.8x105.
Next, we want to find the ION/IOFF ratio for CNFET based on the simulation result obtained in this project. Assume that at the same bias voltage, which is at gate voltage of 0.6V, it is found that on-current is about 11µA and leakage current is 4x10-5. Therefore, ION/IOFF ratio for CNFET obtained using this simulation model is about 2.75x105.
This value is slightly lower than ION/IOFF ratio for sub-10nm
MOSFET. Therefore it shows that CNFET has on-par performance with MOSFET in terms ION/IOFF ratio.
Figure 5.7: ID vs. VD for sub-10nm MOSFET.
69
Figure 5.8: ID vs. VG for sub-10nm MOSFET.
5.3.2
Effect of gate oxide thickness on drain current
In the previous analysis, we compare the ION/IOFF ratio between CNFET and sub-10nm MOSFET. Now, we want to look into the effect of oxide thickness on drain current level, i.e. both ION and IOFF level. The nanotube diameter will be fixed at 1nm and the gate oxide thickness is varied from 0.5nm to 2.5nm as depicted in Figure 5.9. Figure 5.10 and 5.11 show drain current for oxide thickness of 0.5nm, Figure 5.12 and 5.13 show drain current for oxide thickness of 1.0nm, Figure 5.14 and 5.15 show drain current for oxide thickness of 2.0nm as well as Figure 5.16 and 5.17 show drain current for oxide thickness of 2.5nm. Next, Table 5.1 shows the level of ION and IOFF for the respective gate oxide thickness at gate voltage of 0.6V.
Figure 5.9: Simulated ballistic CNFET with 1nm diameter and varying gate oxide thickness.
70
Case 1: CNT diameter 1.0nm and gate oxide thickness 0.5nm.
Figure 5.10: Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 0.5nm.
Figure 5.11: Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 0.5nm.
71
Case 2: CNT diameter 1.0nm and gate oxide thickness 1.0nm.
Figure 5.12: Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 1.0nm.
Figure 5.13: Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 1.0nm.
72
Case 3: CNT diameter 1.0nm and gate oxide thickness 2.0nm.
Figure 5.14: Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 2.0nm.
Figure 5.15: Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 2.0nm.
73
Case 4: CNT diameter 1.0nm and gate oxide thickness 2.5nm.
Figure 5.16: Plot of ID vs. VD for CNT diameter 1.0nm and gate oxide thickness 2.5nm.
Figure 5.17: Plot of ID vs. VG for CNT diameter 1.0nm and gate oxide thickness 2.5nm.
74
Table 5.1: Drain current corresponding to gate oxide thickness. Oxide thickness
ION
IOFF
(nm)
(µA)
(µA)
0.5 1.0 1.5 2.0 2.5
38 17 11 9 7
4x10-5 4x10-5 4x10-5 4x10-5 4x10-5
From Table 5.1, it is obvious that the on-current, ION, increases as the gate oxide thickness decreases. In short, on-current is inversely proportional to gate oxide thickness. However, from the graph of ID vs. VG, it is noted that the level of leakage current, IOFF, is not considerably affected by gate oxide thickness. Therefore, we can deduce that the ION/IOFF ratio will increase as the gate oxide thickness is reduced. Thus, the analysis above is matching with the theory of MOSFET-like CNFET, which the leakage current is not increasing significantly when gate oxide is thin since ambipolar characteristic is suppressed in this structure. However, this result might be different in SB-CNFET since ambipolar characteristic is very strong that leads to higher leakage current as gate oxide thickness is reduced.
5.3.3
Effect of CNT diameter on drain current
Diameter size of CNT is known could affect the bandgap in CNT and since the drain current of CNFET is dependent on the total charge that filled up the first subband, therefore it is possible that the drain current too depends on the diameter of CNT. Unlike in the analysis in 5.3.2, now that the gate oxide thickness is held constant at 1.5nm and the nanotube diameter varies from 0.5nm to 2.0nm as illustrated in Figure 5.18. Figure 5.19 and 5.20 show the ION and IOFF respectively for nanotube of diameter 0.5nm, Figure 5.21 and 5.22 show the ION and IOFF respectively for nanotube of diameter 1.5nm along with Figure 5.23 and 5.24 show the ION and IOFF respectively for nanotube of diameter 2.0nm. Next, Table 5.2 shows the level of ION and IOFF for the different CNT diameter at gate voltage of 0.6V.
75
Figure 5.18: Simulated ballistic CNFET with 1.5nm gate oxide thickness and varying nanotube diameter.
Case 1: CNT diameter 0.5nm and gate oxide thickness 1.5nm.
Figure 5.19: Plot of ID vs. VD for CNT diameter 0.5nm and gate oxide thickness 1.5nm.
76
Figure 5.20: Plot of ID vs. VG for CNT diameter 0.5nm and gate oxide thickness 1.5nm.
Case 2: CNT diameter 1.5nm and gate oxide thickness 1.5nm.
Figure 5.21 Plot of ID vs. VD for CNT diameter 1.5nm and gate oxide thickness 1.5nm.
77
Figure 5.22: Plot of ID vs. VG for CNT diameter 1.5nm and gate oxide thickness 1.5nm.
Case 3: CNT diameter 2.0nm and gate oxide thickness 1.5nm.
Figure 5.23: Plot of ID vs. VD for CNT diameter 2.0nm and gate oxide thickness 1.5nm.
78
Figure 5.24: Plot of ID vs. VG for CNT diameter 2.0nm and gate oxide thickness 1.5nm.
Table 5.2: Drain current corresponding to CNT diameter. CNT diameter
ION
IOFF
(nm)
(µA)
(µA)
0.5 1.0 1.5 2.0
5 11 18 25
4x10-5 4x10-5 4x10-5 4x10-5
Table 5.2 gives the value of both on-current, ION, and leakage current, IOFF, at gate voltage of 0.6V. We can see that from Table 5.2, CNT diameter has effect on the drain current especially the on-current, ION. Based on the graph, the IOFF level is not significantly affected, which is the same scenario as in the analysis made in 5.3.2. ION is directly proportional to the CNT diameter with the drain current increases enormously with slight increase in diameter of nanotube. As the IOFF level is almost remains the same, apparently it is clear that the ION/IOFF ratio will definitely increase. Hence, we can say that larger size of CNT will give better performance of CNFET.
79 However, scaling issue will be a major concern if very large diameter of CNT is used in CNFET since one of the advantages of CNFET over MOSFET is that it offers smaller size of transistor.
5.4
Discussion
In the first analysis, the comparison result shows that CNFET is comparable with MOSFET performance in terms of ION/IOFF ratio. Thus, based on this result, there is no significant advantage of CNFET compared to MOSFET. This model only calculates current based on charge that occupy in the first subband of CNFET, which limits on-current that can be obtained. Hence, ION/IOFF ratio obtained in this simulation is comparable to MOSFET although previous works by other researchers [21], [38], [39] give positive result of CNFET over MOSFET.
Next, in second analysis, the effect of gate oxide thickness on drain current level is investigated. From this analysis, it is found that on-current increases as gate oxide thickness is reduced but the leakage current remains almost the same. Since it is known that the MOSFET-like structure is able to eliminate ambipolar characteristic that causes leakage current to increase, thus this analysis is actually verifies this theory.
Finally, the effect of CNT diameter on drain current is also investigated. From this analysis, the on-current is found to be directly proportional with CNT diameter but the leakage current is still unaffected due to the same reason as in the first analysis. Drain current calculated using this simulation model is based on the number of charge that occupies the first subband of CNT. Since bandgap of CNT is dependent on its diameter, therefore drain current, particularly on-current, is definitely affected by diameter of CNT.
80 5.5
Summary
This chapter presents the simulation result obtained in this project and then the result is analysed and discussed as well. Methodology of this project is also explained such as the simulation model used to find the I-V characteristic of ballistic CNFET, how the simulation model is implemented in programming language and the whole process in calculating drain current based on the specified input parameters. The interest in the analysis section is how good CNFET compared to MOSFET given its small size. Although most of previous works done by other researchers have found CNFET has advantage over MOSFET in terms of device performance, but the result obtained in this simulation shows otherwise. The reason behind the difference could be due to the simulation used in this thesis. This thesis used a simple analytical model to attain I-V characteristic of CNFET. The drain current calculated in the simulation model is based on the total charge in the first subband of the nanotube, which leads to lower drain current at any specified drain and gate voltage. Thus, the performance of simulated CNFET using this model is found to be almost similar to MOSFET. Next, the effect of gate oxide thickness and CNT diameter on the drain current is also investigated. At the end of these analysis, it shows that both parameters is actually affects the drain current and hence the performance of ballistic CNFET. Thus, from this chapter, we can conclude that the performance of CNFET is similar with MOSFET and it also depends on the gate oxide thickness and the size of CNT.
CHAPTER 6
CONCLUSION AND FUTURE WORK
This chapter concludes the overall content of this thesis. Recommendations are also given for further work.
6.1
Conclusion
The successful history of scaling process of MOSFET has contributed to high-performance integrated circuit for decades. Scaling process has remarkably continuously improving MOSFET performance as predicted by Moore’s Law. Nevertheless, this process will reach its limit and by that time, MOSFET is no longer improved through the scaling process. Besides, there are also several problems arise as the size of MOSFET reach beyond 10nm scale such as short channel effect and tunnelling effect. Therefore, in order to overcome these problems, several new devices have been proposed that offer better device dimension scale and also great quality of performance. One of the materials with high potential to be an excellent switching device is carbon nanotube.
Carbon nanotube (CNT) is a hollow tube made of graphene sheet that can grow of up to millimetres and the size is within nanometre scale. The size of CNT offers a possibility of building small-scale transistor and it also has unique properties that can boost the device performance such as it can sustain very high current density. Depending on its chirality, CNT can have either semiconducting or metallic characteristic. Semiconducting CNT can be used as transistor channel since it has the
82 characteristic of semiconductor whereas metallic CNT can be used as wire on circuit boards or electronic interconnections.
The main purpose of this project is to study the characteristic of carbon nanotube field-effect transistor (CNFET). Basically, the structure of CNFET is almost the same as MOSFET except that the silicon channel is now being replaced by CNT. The structure of MOSFET has evolved from back-gated to top-gated and recently vertical structure has been proposed. The operation of CNFET can be seen either as Schottky barrier CNFET (SB-CNFET) or MOSFET-like CNFET. While the former structure used metal as its source/drain terminals, the latter structure used highly doped CNT as its source/drain terminals.
SB-MOSFET is widely used in the early structure of CNFET but the main problem associated with this structure is the existence of strong ambipolar characteristic. This characteristic leads to high leakage current, which limits the device performance. MOSFET-like CNFET structure, on the other hand, is able to suppress ambipolar characteristic and hence improve the device performance.
A simple analytical mathematical model is used in this project in order to find I-V characteristic of CNFET. Despite positive result produced in previous work, the simulation result in this project shows otherwise. As stated previously in section 5.5, the reason behind the difference could be due to the simulation used in this thesis. In this thesis, a simple analytical model is used to attain I-V characteristic of CNFET. The drain current calculated in the simulation model is based on the total charge in the first subband of the nanotube, which leads to lower drain current at any specified drain and gate voltage. Thus, from the comparison analysis, the performance of simulated CNFET using this model has no clear advantage over MOSFET. This result reflects the effectiveness of simulation model used in this model. Further improvement of this simulation model is needed in order to prove CNFET has better performance than MOSFET as reported in previous work.
83 Apart from comparison analysis, the effect of gate oxide thickness and CNT diameter on device performance is also analysed. From the analysis, both parameters are found to have significant effect on the device performance, particularly the oncurrent. Analysis results conclude that thinner gate oxide and larger CNT could help to improve the device performance.
As a conclusion, CNFET has large potential that can be exploited to be an effective switching device. CNFET is still far to be a commercial device in electronic industry but the researchers are pushing very hard to improve its performance in order to replace MOSFET as the heart of digital applications.
6.2
Future work
Investigating the CNFET characteristics is very interesting since this device has many aspects that can be explored and improved. For future works, the comparison analysis between CNFET and MOSFET can be extended from on-offcurrent ratio to other parameters such as transconductance and conductance of the device. Expanding the comparison analysis will give a clearer picture of CNFET performance over MOSFET. Besides, since the outcome of simulation analysis in this project is totally based on ideal condition of CNFET, an experimental work including the fabrication process of CNFET will provide more realistic result.
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APPENDIX A
MATLAB Source Code for Ballistic CNFET Simulation
% Simulation model to simulate I-V characteristics of nanoscale carbon nanotube FET (CNFET) % % % Input % ----% Device Specification: % Gate Insulator Thickness, t (m) % Gate Insulator Dielectric Constant, epsr % Tube Diameter, d (m) % Temperature, T (K) % % Terminal Voltage: Number of Bias Points, NV % Voltage Range, VI,VF (V) % % Analytical Model: Source Fermi Level, Ef (eV) % Get Control Parameter, alphag % Drain Control Parameter, alphad % % FETToy for CNTFETs ... clc; %Clear command window close all; %Close all previous work %Physical parameters q = 1.6e-19; T = 300; Kb = 1.38e-23; K = 8.62e-5; h = 6.625e-34; hbar=1.05e-34; eps0=8.85e-12; epsr=3.9; t = 1.5e-9; d = 2e-9;
% Electron charge (C) % Operating temperature (K) % Boltzmann constant (J/K) % Bolzmann constant (eV/K) % Planck's constant (J-s) % Planck's constant (eV-s) % Permittivity of free space (F/cm^2) % Relative permittivity of dielectric constant % Oxide thickness (m) % Nanotube diameter (m)
89 NV = 11; VI = 0; VF = 1.0; Ef = -0.32; alphag = 0.88; alphad = 0.035;
% No. of bias point % Initial bias point (V) % Final bias point (V) % Fermi level for source % Gate control coefficient % Drain control coefficient
kT=Kb*T/q; V=linspace(VI,VF,NV);
% Thermal voltage (eV). % Voltage (gate or drain) steps.
Cins=2*pi*epsr*eps0/log(t/(d/2)); % Insulator capacitance C_SIG=Cins/alphag; % C_SIG=sum of capacitors (see eq. (7b) in [1]). U0=q/C_SIG; % Charging energy (eq. (8b) in [1]). %Calculate D0 and EG for CNTFETs a_cc=1.42e-10; % C-C bond length (m) t0=3.0; % C-C bonding energy (eV) D0=8/(3*pi*a_cc*t0); % DOS [1/(m*eV)] EG=2*a_cc*t0/d; % Band Gap [eV] N0=N_CNT(D0,EG,kT,Ef); % Electron concentration at the top of the barrier in neutral device. I0=(2*q*Kb*T/pi/hbar); % Valley degeneracy is 2 for kVg=1:NV % Bias loop begins. Vg=V(kVg); for kV=1:NV Vd=V(kV); mu1=Ef; mu2=mu1-Vd; % Source and drain fermi levels. UL=-(alphag*Vg)-(alphad*Vd); % Laplace potential. Uscf=fzero(@Uscf_zero,0,optimset('tolx',1e-12), D0,EG,mu1,mu2,kT,UL,U0,N0); %Uscf_zero=(UL+U0*(N_CNT(D0/2,EG,kT,mu1-Uscf) +N_CNT(D0/2,EG,kT,mu2-Uscf)-N0))-Uscf; fermi_flag=1; if (mu1-Uscf)/kT 1), h1=semilogy(V,I([1,3,5,7,9,NV],:)); else h1=semilogy(V,I, 'k'); end set(h1,'linewidth',[lwpl]); set(gca,'Fontsize',[fsize],'linewidth',[lwbor]); xlabel('V_G [Volt]'); ylabel('I_D [µA]'); title('Graph I_D vs V_G','Fontsize',18); % Create graph title legend(['V_{D}=',num2str(V(1),3)],['V_{D}=',num2str(V(3),3)],['V_{D}=',num2str( V(5),3)],['V_{D}=',num2str(V(7),3)],['V_{D}=',num2str(V(9),3)],['V_{D}=’,num2st r(V(end),3)],2); grid on; %Plot Id-Vg (linear) figure(2); if (NV > 1), h1=plot(V,I([1,3,5,7,9,NV],:)); else h1=plot(V,I); end set(h1,'linewidth',[lwpl]); set(gca,'Fontsize',[fsize],'linewidth',[lwbor]); xlabel('V_G [Volt]'); ylabel('I_D [µA]'); title('Graph I_D vs V_G','Fontsize',18); % Create graph title legend(['V_{D}=',num2str(V(1),3)],['V_{D}=',num2str(V(3),3)],['V_{D}=',num2str( V(5),3)],['V_{D}=',num2str(V(7),3)],['V_{D}=',num2str(V(9),3)],['V_{D}=',num2st r(V(end),3)],2); grid on; %Plot Id-Vd figure(3); h1 = plot(V,I(:,[1,3,5,7,9,NV])); set(gca,'Fontsize',[fsize],'linewidth',[lwbor]); set(h1,'linewidth',[lwpl]); xlabel('V_D [Volt]');
91 ylabel('I_D [µA]'); title('Graph I_D vs V_D','Fontsize',18); % Create graph title legend(['V_{G}=',num2str(V(1),3)],['V_{G}=',num2str(V(3),3)],['V_{G}=',num2str( V(5),3)],['V_{G}=',num2str(V(7),3)],['V_{G}=',num2str(V(9),3)],['V_{G}=',num2st r(V(end),3)],-1); grid on; % Make the grid lines visible
APPENDIX B
Mathematical Derivation for Ballistic CNFET Simulation
This section presents the mathematical derivation of current-voltage (I-V) characteristic for ballistic CNFET. Figure B-1 illustrates how the states at top of the barrier are filled using E-k relationship. The energy reference is the top of barrier at zero terminal voltage. The source Fermi level, EF1, drain Fermi level, EF2, and potential at top of barrier are expressed with respect to the energy reference.
Figure B-1: Illustration of how k-states at top of the barrier are filled by the two Fermi levels
93 The positive k-states are occupied according to source Fermi level as N1 =
1 A
∑
d 2k
f (E − E F1 ) =
∫ ∫ 2 (2π )
f (E − E F1 )
f (E − E F1 )dE
1 2
2
k x > 0,k y
k x > 0,k y ∞
∫
=
−∞
∫ 2π
S(E)
1 2
∇E(k)
(B1)
dS
Where S(E) is a constant energy in k-space, dS is an element area on this surface and dE is the distance between the surfaces S(E+dE) and S(E). Defining the density∇E(k)
of-states (DOS) as
(
D E − U scf
)=
dS
∫
1 , ∇E (k )
(B2)
− U scf f (E − E F1 )dE
(B3)
S(E − U scf )
2π
2
we finally have N1 =
∞
∫ D(E
1 2
)
−∞
The integral for N1 can be analytically defined as N1 =
k B T 2m* 2πh
2
(
log 1 + e
E F1 − U scf /k BT
)
(B4)
A similar expression exists for N2, states occupied according to drain Fermi level N2 =
(
k B T 2m* 2πh
log 1 + e
2
E F2 − U scf /k BT
)
(B5)
Current for positive k-states is evaluated as I1 =
q A
∑υ
x
f (E − E F1 )
k x > 0,k y
d 2k
∫ ∫ 2π
=
2
qυ x f (E − E F 1 )
k x > 0,k y ∞
=
∫
f (E − E F1 )dE
−∞
∞
=
∫
−∞
f (E − E F1 )
q 2
dS
∫ 2π
S(E)
(
2
υx
1 ∇E (k )
) (
)
q υ x E − U scf D E − U scf dE 2
(B6)
Where υ x (E ) is the average value of υ x over the constant energy surface, S(E), expressed as
94
(
υ x E − U scf
)
dS
∫
=
S(E − U scf
2π 2
dS
∫
S(E − U scf )
1 ∇E (k )
υx
(B7)
1 ∇E (k )
2π 2
Defining the current-density-of-states as
(
J E − U scf
)
=
(
) (
)
q υ x E − U scf D E − U scf , 2
(B8)
Thus, we have ∞
I1 =
∫ J (E − U ) f (E − E scf
F!
)dE
(B9)
−∞
In general, for the 2D electron density, the υ x (E ) can be analytically evaluated to obtain
(
J E − U scf
)
=
1 ⎛⎜ 2 q 2 ⎜π ⎝
(
)
2 E − U scf ⎞⎟ D E − U scf ⎟ m* ⎠
(
)
(B10)
Where the factor 2/π appears because of averaging υ x over all possible k values at energy E – Uscf. I1 can be analytically integrated to obtain I1 =
1 2m * qk B T 2 πh 2
(
2kT (E −U ) / k T log 1 + e F 1 scf B * πm
)
(B11)
)
(B12)
Similar expression exists for current at negative k-states I2 =
1 2m * qk B T 2 2 πh
(
2kT (E −U ) / k T log 1 + e F 2 scf B * πm
