Characteristic Impedance of Microstrip-like Interconnections Guarded by Ground Tracks Rohit Sharma1, T. Chakravarty2, A. B. Bhattacharyya3 1
Jaypee University of Information Technology, Waknaghat, HP, 173215, INDIA,
[email protected] 2 Tata Consultancy Services, Bangalore, KA, 560067, INDIA,
[email protected] 3 Jaypee Institute of Information Technology, Noida, UP, 201307, INDIA,
[email protected]
Abstract Grounded guard tracks placed adjacent to transmission line interconnects can change their impedance significantly. We report closed-form expressions for line capacitance and impedance of transmission line interconnects with adjacent guard tracks. Results are validated by finite-difference time-domain (FDTD) simulations and measurements. The proposed results can have significant impact on the analysis of coupled interconnect lines, where the use of these grounded tracks is a common design practice.
1. Introduction Grounded guard tracks adjacent to transmission line interconnect are often used for reduction of crosstalk in a variety routing topologies [1] and high-speed mixed signal systems [2-5]. While full-wave spectral domain analysis for crosstalk reduction using additional ground tracks has been discussed in detail [6]; the effect of such ground tracks on the impedance of the interconnect line itself is usually lost sight of. From system design consideration an accurate design formula for the impedance of such interconnects is of substantial practical use. With the introduction of grounded guard tracks, the line impedance becomes a function of the separation between the line and ground tracks, in addition to the interconnect line width, height of the substrate and the dielectric constant of the substrate. In this work, we report closed-form expressions for the capacitance and impedance of transmission line interconnects with adjacent ground tracks using variational technique combined with transverse transmission line technique [7], which offers a relatively simple approach for the solution of such type of problems. The design methodology presented in this paper can aid designers to strategically place guard tracks, thereby ensuring lower crosstalk and superior signal integrity. It may be mentioned that the structure under discussion has useful application in reducing crosstalk between interconnect lines in multichip modules carrying high-speed signals and is different from coplanar stripline structures which does not have a bottom ground plane. Out of all the analytical methods, the variational method treats the dielectric boundary conditions in a generalized way. Thus it is possible to analyze multilayer microstrip lines also without much difficulty. The accuracy of this method is insensitive to the choice of the trial function. Thus it is possible to take into account all the dielectric boundary conditions no matter how many planar boundaries exist in these lines [8]. The method is based on the calculation of the line capacitance by the static field theory, and, therefore it is an approximation to the EM theory. Unlike conformal mapping and other analytical techniques – which are also the static field theory – the analytical treatment of multiple boundaries is easier by the variational method [7-9]. The computational time is also far lesser than other techniques. All of this makes the variational method combined with the transverse transmission line technique a natural choice for analysis of the interconnect structures in our paper. The analytical model has been verified both by field simulator and measurements performed on specially designed PCB interconnect tracks.
2. Analytical Model Fig. 1 shows the cross-section of the interconnect line which is at the centre over a ground plane at the bottom and resembles a standard microstrip-like structure. In order that the interconnect line carrying signal is isolated, grounded metallic traces have been placed on both sides of the line. The interconnect line is assumed to be very thin having a width ‘w’. The thickness of the dielectric (lower region) is b2 having a permittivity ε2. The ground tracks, coplanar with the interconnect line, has a separation ‘d’ from the line on both sides. The interconnect line, therefore, sees grounded planes both below vertically and sideways laterally.
Upper Region Charge Plane
ε3
Ground Track
Ground Track
Line
d
b3
d w
ε2
b2
Substrate
Lower Region 0
c
x Fig. 1 Lateral view of the interconnect structure guarded by ground tracks The standard technique for determining line capacitance is explained in detail in [7] and hence only salient steps leading to the variational formula for the capacitance are presented here. The variational expression for the capacitance of a multilayer structure, as shown in Fig. 1, is given by;
[(1 + 0.25A) ] 2
C=
∑(L
n
(1)
+ AM n ) 2 Pn / Y
n
where Ln = sin( β n w / 2)
[{
}
{
}
M n = (2 / β n w) 3 3 ( β n w / 2) 2 − 2 cos(β n w / 2) + ( β n w / 2) ( β n w / 2) 2 − 6 sin( β n w / 2) + 6
]
Pn = (2 / nπ )(2 / β n w) 2
β n = nπ / c
∑ (L − 4M )L P / Y A=− ∑ (L − 4M )M P / Y n
n
n n
n
n
n n
n odd
n odd
n = 1, 2, 3..∞ Note that in equation (1) the only parameter that needs to be determined is the admittance Y at the charge plane y = y0. To compute the admittance Y, we take shield walls (both lateral and top) in the upper region at very large distance to simulate open boundary conditions of an open microstrip structure and electric walls in the specified physical distance in the lower region. The admittance of the lower region in Fig. 1 is given by
YLower ,n = ε 0ε 2 coth( β n b2 )
β n = nπ / c
(2)
c = 2.d + w where, ε2 and b2 is the permittivity and height of the dielectric layer, respectively, and is computed for odd values of n excluding n = 0. The distance c is shown by dotted lines. The admittance of the upper region in Fig. 1 is given by
YUpper ,n = ε 0ε 3 coth( β n b3 )
β n = nπ / c '
(3)
c' >> w b3 >> b2
where, ε3 and b3 is the permittivity and height of the dielectric layer (upper region) respectively and is computed for even values of n excluding n = 0. Substituting equations (2) and (3) in (1), we compute the line capacitance for these two regions; CLower and CUpper, respectively. The proposed design model is versatile and can qualitatively be used to analyze microstrip lines also. It can be seen as the separation ‘d’ increases, the admittance parameter YLower modifies and formulation given above reduces to the basic microstrip formulation. The results are valid for a range of dielectric substances. The results obtained in this paper are accurate up to 5 - 7 GHz, which incidentally happens to be the frequency of interest in current high-speed interconnects. If the interconnect has a small but finite thickness ‘t’, equation (1) can still be used by replacing Y in equations (2) and (3) by Y/h (βn, t) as reported in [7-10]. The expression for h (βn, t) for the structure considered is given by
h (β n , t ) =
1 sinh{β n (b2 − t )} 1 + 2 sinh{β n b2 }
(4)
From the expression of characteristic impedance for a microstrip line [9], the impedance Z of the interconnect structure can now be computed as
1
Z= v
a
(5)
a a (C Lower + CUpper )(C Lower + CUpper )
3. Results
Characteristic impedance (Z ) in ohms
Results obtained from the above discussion are compared with FDTD simulations to check their accuracy. Fig. 2 gives a comparative plot of the characteristic impedance of an interconnect line with adjacent grounded guard tracks for a range of dielectric substrates (εr = 2.2, 4.6, and 9.9). Simulated results (εr = 9.9) Simulated results (εr = 4.6) Measured Results (εr = 4.6) Analytical results (εr = 2.2)
140
Analytical results (εr = 9.9) Analytical results (εr = 4.6) Simulated results (εr = 2.2)
120 100 80 60 40 20 0 0
0.5
1
1.5
2
2.5
3
Separation between line and ground tracks (d ) in mm
Fig. 2 Simulated, predicted, and measured characteristic impedance (w = 1 mm and h = 1.59 mm)
3.5
It is interesting to know that the characteristic impedance Z reduces substantially when the ground tracks are placed close to the line interconnects. The introduction of guard tracks close to the interconnect line results in increase in the lateral capacitance between the line and the guard tracks. This reduces the characteristic impedance of the interconnect line. The results are validated by measurements performed on fabricated interconnect structures of different specifications, using vector network analyzer and are highlighted in Fig. 2. The theoretical results show good agreement with the measured data, which validates our analysis. As the distance between the line and the ground tracks increases, the characteristic impedance Z settles to a final value, which corresponds to that of a microstrip line. These values corroborate to the microstrip line impedance obtained from Wheeler’s equation [10]
4. Conclusion While the use of ground tracks is reported for crosstalk alleviation, its effect on the line impedance has not been reported so far. We propose a fast and efficient design methodology for computation of line impedance of a transmission line interconnect with adjacent grounded guard tracks. The proposed analysis highlights the effect of ground tracks on line impedance. The design methodology can be applied to ensure superior signal integrity in dense routing topologies and coupled interconnects where ground tracks are commonly used to avoid crosstalk. It may be mentioned that though the present work is concerned with the effect of ground tracks on the impedance of interconnect lines; the analysis can be used for crosstalk related performance evaluation of coupled interconnect lines also.
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2.
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7.
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8.
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10.
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