Circuit-Level Reliability Requirements for Cu ... - Semantic Scholar

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005

Circuit-Level Reliability Requirements for Cu Metallization Syed M. Alam, Member, IEEE, Chee Lip Gan, Member, IEEE, Frank L. Wei, Carl V. Thompson, Senior Member, IEEE, and Donald E. Troxel, Life Senior Member, IEEE

Abstract—Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure characteristics depending on the via position and configuration in a line. Unlike Al technology, a ( jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been developed. Using data from the literature, the layout-specific circuitlevel reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced. Index Terms—Aluminum interconnects, barrierless via, circuitlevel reliability simulation, copper interconnects, electromigration, integrated-circuit (IC) reliability, reliability estimation.

I. I NTRODUCTION

T

HE International Technology Roadmap for Semiconductors (ITRS) projects that an exponentially increasing number of interconnect segments will be required to carry increasing current densities in the years to come. Both trends separately require rapid improvements in interconnect reliability. Copper (Cu) has been replacing aluminum (Al) as the metal of choice for interconnects due to its lower resistivity and higher resistance to electromigration. While the electromigrationreliability phenomenon in Al interconnects is well studied [1]–[3], the reliability of Cu technology is still under active investigation. In this paper, we contrast the failure mechanisms in Cu and Al technologies and compare electromigrationManuscript received October 24, 2004; revised May 22, 2005. This work was supported by the Microelectronics Advanced Research Corporation (MARCO) Interconnect Focus Research Center Program, by Semiconductor Research Corporation (SRC), and by the Massachusetts Institute of Technology (MIT)–Singapore Alliance. S. M. Alam was with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA. He is now with Freescale Semiconductor, Inc., Austin, TX 78735-8598 USA (e-mail: [email protected]). C. L. Gan is with the School of Materials Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). F. L. Wei and C. V. Thompson are with the Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA (e-mail: [email protected]; [email protected]). D. E. Troxel is with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TDMR.2005.853507

reliability assessments at the circuit level. Circuit-level assessments carried out at the design and layout stages allow accurate reliability projections, and also allow technology and layout changes for improved reliability with still-optimized performance. We have developed and exercised a tool, SysRel, for circuit-level interconnect-reliability assessments with either Al or Cu metallization, and used it to assess the reliability impact and requirements for Cu metallization. Sections II and III gives an overview of the interconnect metallization schemes for Al and Cu technologies, and outlines the distinct electromigration characteristics in Cu, in light of the differences in metallization schemes. Section IV describes the atomic-diffusivity models and parameter values used in our work. A default model to compute lifetimes due to electromigration failures is then presented in Section V. Using the diffusivity and default models, we have investigated lifetime trends in a straight-line interconnect that is outlined in Section VI. We have used parameter values from selected publications, as well as those from our own work. Parameter values derived from experiments depend on fabrication processes, materials, and structural details. However, the models and methodologies we have developed for circuit-level reliability analyses are general, and can be used with any set of experimentally derived input parameters. Simple straight-line interconnects are often studied for analytical and experimental purposes, even though multisegment trees interconnected in a complex fashion exist in actual circuit layouts. In Section VII, we present a set of methodologies for circuit-level reliability analysis with either Cu or Al metallization in the layout. The methodologies are implemented in a computer-aided-design (CAD) tool, SysRel, with which we have compared circuit-level reliabilities for various circuit layouts. Results are presented in Sections VIII and IX. Finally, Section X addresses the impact of nonblocking vias, a unique phenomenon in Cu technology, on electromigration and circuitlevel reliability. II. I NTERCONNECT P ROCESSING T ECHNOLOGY The fabrication processes are drastically different for Cu and Al due to their differences in chemical properties. Al reacts with SiO2 to form alumina, which eliminates Al atomic diffusion into the dielectric. Al metallization is processed by subtractive etching in which the patterned lines are formed by etching the deposited blanket Al film. The Al architecture has thick refractory metal layers (made of TiN, Al3 Ti, or both), at the top and bottom of the lines serving as antireflection coatings and

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ALAM et al.: CIRCUIT-LEVEL RELIABILITY REQUIREMENTS FOR Cu METALLIZATION

Fig. 1. (a) Al interconnects, with W-filled vias and conducting shunt layers at the top and bottom of the line. (b) Dual-damascene Cu interconnects, with Cu-filled vias, thin refractory liners at the side and bottom of the line, and a dielectric capping layer at the top of the line.

seed layer for the via-fill process, respectively. Robust tungsten (W)-filled vias are used to connect different levels of Al metallization [Fig. 1(a)]. Unlike Al, Cu does not chemically reduce SiO2 . Furthermore, suitable etchants for Cu thin films are unavailable. Consequently, Cu interconnects are fabricated by the damascene method, in which a trench is etched into the interlevel dielectric before filling it with Cu by electroplating. Thin refractory metal layers consisting of Ta or Ta/TaN are placed at the sides and bottom of the Cu interconnect lines to prevent Cu from diffusing into the device layer. The Cu lines are capped with a dielectric diffusion barrier (DDB), such as Si3 N4 . Dual-damascene Cufilled vias are used to connect different levels of metallization in Cu interconnects [Fig. 1(b)]. III. C ONTRASTING F AILURE C HARACTERISTICS In Cu interconnects, it has been widely reported that the Cu/cap interface acts both as the dominant diffusion path and as the likely site for void nucleation [3]–[5]. Due to this, the lifetimes of via-above (or M1)-type interconnects are different from that of via-below (or M2)-type interconnects [4], [5]. In M1 structures, vias and connector lines are located above the test lines. Conversely, in M2 structures, the vias and connector lines are located below the test lines (Fig. 2). We have experimentally demonstrated that the lifetimes of M2-type structures are always higher than those of the M1-type structures, given the same dimensions and the number of vias at the ends [4]. During electromigration, a tensile stress develops at the cathode ends of Cu lines, where the Ta liner forms a blocking boundary to the electromigration of Cu atoms. For current Cu technology, the critical tensile stress for void nucleation has been estimated to be 41 MPa or less [3], compared to 500 MPa for Al technology [2]. In M2 Cu structures, voids preferentially nucleate at the Cu/Si3 N4 interface due to the low critical stress for nucleation at that interface. An opencircuit failure occurs only when the void grows to span the entire thickness of the line, resulting in a large critical void volume for failure. On the other hand, in M1 structures, the maximum tensile stress develops at the Cu/Si3 N4 interface near the cathode via. Therefore, an open-circuit failure would

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Fig. 2. Side-view schematic of void formation in M1 (via-above) and M2 (viabelow) interconnects. (a) A small-volume fatal void in an M1 interconnect; (b) A large-volume nonfatal void in an M2 interconnect.

occur if a small-volume void spans the bottom of the via, such that the pathway for electron flow is blocked (Fig. 2). Vias in our test structures are smaller than the linewidth. However, if the via size is the same or larger than the linewidth, or is in contact with the sidewalls of the metal liner, the early failure lifetime would not be applicable for via-above-type structures. In this work, we will be focusing on geometric structures where vias are smaller than the linewidth, which is the most common scenario in actual circuit layouts. However, the methodology described below is general, and could be modified to account for cases in which there is via/liner contact. The asymmetry in the void volume required for failure not only accounts for the M1–M2 asymmetry in lifetimes, but also contributes to the different short-length effects for immortality in via-above- and via-below-type interconnects. At short lengths, the reliability improves for both Al and Cu interconnects [3], [7]–[9]. However, unlike Al interconnects, the tolerable nonfatal void volumes in M1 and M2 structures are different. Consequently, different critical products of the current density and line length ( jL)critical for immortality have been reported. Lee and colleagues obtained a value of 3700 A/cm for M2 structures [7], [8], and Hau–Riege reported a ( jL)critical of 2100 A/cm for M1 structures [3]. In contrast, only one ( jL)saturation is needed (4000 A/cm) for Al interconnects [10]. This is because the Al interconnect architecture has top and bottom conducting shunt layers that can divert electron flow around small voids for both M1 and M2 geometries. IV. D IFFUSIVITY M ECHANISMS AND M ODELS When quantifying electromigration, we can represent the dominant diffusion paths in Al and Cu interconnects using (1) and (2), respectively, following the convention presented by Hu et al. [11]:

 2 d ∗ ∗ ∗ δGB (Dz )eff = DS zS δS + DGB zGB 1− (1) h d w
 1 . (2) (Dz ∗ )eff = DS zS∗ δS h Here, D is the diffusivity, which has an Arrhenius or exponential dependence on temperature, z ∗ is the effective charge, δ is the diffusion interface width, and d, h, and w, are the

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005

grain size, line thickness, and linewidth, respectively. S denotes the Al/refractory-metal-liner interfaces and the Cu/overlayer interface for Al and Cu systems, respectively. GB represents grain boundaries. We assume that all other diffusion paths have negligible contributions. In Al interconnects, grain-boundary diffusion dominates when lines are wider than the average grain size. Interface diffusion dominates in lines with bamboo microstructure, i.e., lines which are narrower than the average grain size and which have been subjected to a postpatterning anneal. Equations (3) and (4) model diffusivity in Al polygranular and bamboo-type lines, respectively: Dpoly = DGB,0 × e Dbam = DS,0 × e

−

Ea GB kT

Ea − kTS

×


 d δGB × 1− × d w 2δS . href

(3) (4)

For the calculations to follow, we use an average Al grain size d = 0.5 µm, z ∗ = 4, DS,0 = 1.49E − 4 m2 /s, EaS = 0.9 eV, a reference line thickness, href = 0.4 µm yielding 2δS /href = 4E − 5, DGB,0 = 1.9E − 5 m2 /s, EaGB = 0.8 eV, δGB = 0.5 nm [12], [13]. The effective diffusivity in Al polygranular lines (w > d) depends on linewidth w. In Cu interconnects, the Cu/cap interface is the dominant diffusion path [3]–[5]. We determined the kinetic parameters associated with the effective diffusivity through conventional package-level electromigration stress experiments using fully processed dual-damascene Cu interconnects (both via-above and via-below structures) under constant current densities. The structures used for these experiments were fabricated by Intel Corporation, Sematech, and the Institute of Microelectronics in Singapore, using 130-nm technology on 200-mm Si wafers. In these experiments, we observed that in both types of structures, a significant fraction of the test population exhibited a steady resistance increase over time prior to failure. We have postulated that this gradual resistance increase results from void growth and have correlated the rate of resistance increase with the drift velocity for electromigration [14], [15]. Among other results, we have determined the activation energy for Cu electromigration to be 0.80 ± 0.06 eV, which is in very close agreement with the value found from other lifetime analyses for the same structures. We also determined (DS,0 δS )/href to be 1.3E − 9 m2 /s, where z ∗ = 1 from [11]. Equation (5) is used to model atomic diffusivity in Cu interconnects, Ea

DCu = DS,0 × e− kT ×

δS . href

(5)

Comparing Al and Cu diffusivities, for a given linewidth, Cu diffusivity is always about 1/15 of that for polygranular Al, due to the similarity in activation energies. Al bamboo diffusivity is lower than that of Cu only for temperatures lower than 302 ◦ C, because the activation energy for Cu diffusivity is lower than that for Al bamboo structures. The atomic diffusivity in Cu-interconnect systems strongly depends on the material used, such as the capping layer, among other variables [16]. In this work, we will be considering the effect of a Si3 N4

capping layer as seen in our experiments. Simulation work in the following sections will utilize diffusivity parameters for the Cu/Si3 N4 interconnect system. We will consider the variation of the capping layer as a means to improve the circuitlevel reliability of Cu interconnects in Section IX. V. E LECTROMIGRATION L IFETIME M ODEL A conservative model for the analysis of interconnect trees has been previously proposed by Hau–Riege [2]. An extension of that model for Cu interconnects is presented in [17]. The time to void nucleation tnucl and the time to extrusion textru at a via can be expressed in closed form using the critical stresses σnucl and σextru : 

tnucl

textru

   √ 2 π kT Di i = 4 BΩ i Di ji     √ 2 Di σextru Ω π kT i = ρez ∗ 4 BΩ i Di ji σnucl Ω ρez ∗

(6)

(7)

where σnucl and σextru are the critical stresses required to nucleate a void or initiate an extrusion, respectively, ji and Di are the current density and effective diffusivity of each of the i limbs meeting at a junction, respectively, Ω is the atomic volume of the electromigrating species, ρ is the resistivity of the metal, and B is the effective modulus of the materials surrounding the metal [17]. At each via, the stress evolution of the whole subtree (the segments of the tree connected to a single via) is considered. Each subtree is then replaced with a semi-infinite limb with an effective diffusivity and current density. Once a void nucleates, it starts to grow and leads to a resistance increase in one of the limbs. Assuming that the void spans the whole width and thickness of the interconnect, the void length can be written as a function of time. The time to growth of a void to length Lv , tgrow can be expressed as tgrow =

1 Lv kT  . z ∗ eρ Di ji

(8)

i

All the vias in a mortal interconnect tree are evaluated individually using (6)–(8). The methodologies for estimating the lifetime of an interconnect tree for Cu and Al technologies are as follows. Derivation of tree time-to-failure (TTF): Cu technology 1. For each via in a tree 2. if (via-above) 3. TTF = tnucl 4. if (via-below) 5. TTF = min{(tnucl + tgrow), textru} 6. Tree’s TTF = min{all via TTFs} Derivation of tree time-to-failure (TTF): Al technology 1. For each via in a tree 2. TTF = min{(tnucl + tgrow), textru} 3. Tree’s TTF = min{all via TTFs}

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TABLE I PARAMETER DESCRIPTION AND VALUES FOR LIFETIME CALCULATION

Fig. 4. Example of an interconnect tree defined as continuously connected conducting metal within one layer of metallization, usually ending at vias or contacts.

VII. C IRCUIT -L EVEL R ELIABILITY A NALYSIS

Fig. 3.

Lifetime comparison for various types of straight-line interconnects.

It is important to note that in our work, extrusions have not been observed to be the primary cause of failure for circuits operating under accelerated testing conditions ( j < 5 MA/cm2 ). Therefore, in what follows, (tnucl + tgrow ) is calculated as the TTF of via-below-type nodes in Cu technology and for all nodes in Al technology. Extrusion failures are expected to be more common in low-k systems. VI. L IFETIME T RENDS AND C OMPARISONS Lifetime comparisons for Cu and Al technologies have been made for a straight line interconnect with semi-infinite length connected to a via. The current density in the segment is set at 0.5 MA/cm2 . Table I shows the parameter values used in the lifetime model [(6) and (7)]. Fig. 3 shows the lifetime versus temperature graph for the interconnect with different via classifications in Cu technology and different line types, bamboo or polygranular, in Al technology. According to Fig. 3, an Al polygranular-type line (using width = 1 µm) has the lowest lifetime. Via-above-type Cu lines have better lifetimes than Al polygranular. Via-belowtype Cu and Al bamboo-type lines compete for the best lifetime depending on the temperature. An Al bamboo-type line has a better lifetime than the Cu via-below-type line for temperatures less than 161 ◦ C. This crossover temperature is a sensitive function of the exact values used for activation energies. However, it is noteworthy that at the individual line or test-device level, the reliabilities of Cu and bamboo Al are similar.

In view of the differences between Al and Cu architectures, we have developed a new set of methodologies for circuit-level layout-specific reliability analysis for Cu interconnects [18]. The methodologies are implemented in SysRel, a new reliability CAD tool for electromigration-reliability analysis and materials and process technology-dependent comparison of circuit layouts. As long as the vias between layers of metallization block electromigration, the reliability of interconnect trees (Fig. 4) can be treated independently in circuit-level analyses. In Al-technology, the condition that vias be blocking is satisfied by the presence of W, and in Cu technology, the condition is generally satisfied by the presence of refractory metal liners at the base of vias. Various immortality, diffusivity, and lifetime parameter values, such as ( jL) products, activation energy, and effective modulus, are dependent on the fabrication process, materials, and structural details. In SysRel, we have used the values as noted in earlier sections based on our own experiments and previously published work. While these values are used in the following sections, the methodologies employed in SysRel are general, and can be employed using parameter values derived from other experiments. SysRel is a public domain tool that can be downloaded from [19] and is designed such that critical parameters are user-defined input. A. Hierarchical Reliability Analyses for Cu SysRel utilizes a hierarchical reliability analysis flow that sufficiently captures the differences between Al and Cu electromigration. SysRel treats circuit layouts from Magic, a widely used layout editor in academia. The steps in the hierarchical reliability analysis for Cu metallization are as follows. 1) Extract interconnect trees from a layout. In addition to geometric properties, the locations of the vias/contacts are also identified on each interconnect tree. Given an interconnect tree, every via is classified as “via-above” or “via-below” depending on whether it is located above or below the interconnect line, respectively. 2) Determine the maximum terminating via-to-via distance, Lmax , in an interconnect tree. 3) Filter interconnect trees using the “M1” ( jL)crit_nuc failure criterion. The first step of the filtering algorithm assumes the worst case scenario. The maximum current

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density allowed by the design rule, jmax , can be obtained from the ITRS [20]. Assuming the worst case condition of ( jL)crit_nuc = 1500 A/cm [21] (i.e., the via is above the line at the cathode end as in an M1 test structure), the program checks whether ( jL)crit_nuc /jmax > Lmax for every interconnect tree. If this inequality is satisfied, the tree is considered immortal and can be ignored in further analyses. 4) Filter mortal interconnect trees using the “M2” ( jL)crit_sat failure criterion. Determine if either of the vias contributing to Lmax is a via-above. If at least one of the vias happens to be a via-above, the interconnect tree may fail with an M1 ( jL)crit_nuc failure criterion as determined in the previous step, and the hierarchical flow proceeds directly to step 5. However, if both of the vias are via-below, the M2 ( jL)crit_sat failure criterion of ( jL)crit_sat = 3700 A/cm [7] is applied. The condition ( jL)crit_sat /jmax > Lmax is then checked. However, even if a tree passes this test, all the other vias in the tree must be considered before classifying it as immortal. This is because via-above nodes have a much smaller immortality value, and thus shorter lengths may fail. The longest distance in the graph from any via-above node to all other vias, Lmax _va , is determined. We again apply the test ( jL)crit_nuc /jmax > Lmax _va to determine whether the tree might fail. 5) Estimate the current density ji in interconnect segments. The Vdd and Gnd lines must be identified as they have unidirectional current flow and are most susceptible to electromigration failure. Most local interconnects transmit signals between devices in the form of bidirectional or alternating current. In these cases, average current flow is taken for the current-density calculation, following the findings in [22] and [23]. Experiments [22] and modeling [23] have shown that the equivalent direct current (dc) for such current stress scenarios are given by the average to account for healing effects in alternating current (ac) or bidirectional electromigration. SysRel identifies Vdd and Gnd lines in a layout and uses the total power dissipation to estimate current stresses in those lines. SysRel conservatively calculates local current density in signal networks using average cell-level power dissipations. 6) Filter mortal interconnect trees by detailed calculation of steady-state stresses. The concept of steady-state stresses in interconnect trees is an extension of the immortality condition in stud-to-stud lines. The maximum stress difference in an interconnect tree ∆σmax is given by the path that has the highest sum of the ( jL) products, summing over the limbs in the path [2], [15]. This is expressed by ∆σmax = ( jL)eff ≡

z ∗ eρ ( jL)eff Ω max

all junction pairs i, j

(9)  

 jk Lk

(10)

k

where ∆σ max is the stress difference between the anode and the cathode, jk and Lk are the current density in,

TABLE II ELECTROMIGRATION ANALYSIS FOR Cu TECHNOLOGY IN A 32- BIT C OMPARATOR L AYOUT

and length of, segment k, respectively, and the rest of the parameters are as defined earlier. To filter the immune interconnect trees using ( jL)eff , repeat steps 3 and 4 by replacing ( jL)max with ( jL)eff . 7) Analyze remaining mortal interconnect trees with the electromigration-lifetime model discussed in Section V. 8) Apply a full-chip stochastic-reliability model. Using the lifetime from step 7 as t50 of an interconnect tree and using a standard deviation determined in experiments, we define a lognormal lifetime distribution for each mortal tree. Lifetimes are combined using a joint stochastic process with a series combination of all failure units. Given a target lifetime for the chip, the full-chip reliability metrics for output are: probability of survival for a given time, failure rate in failure units (FITs) at a given time, the maximum failure rate, and the time to given cumulative percentage failure. B. Contrast With Hierarchical Analysis for Al Via classification is not required in the analogous hierarchical analysis flow for Al technology. Steps 3 and 4 in the hierarchical-reliability analysis are merged into one where a single ( jL) product, ( jL)sat = 4000 A/cm, is applied to check for immortality [10]. VIII. C IRCUIT -L EVEL R ELIABILITY C OMPARISON A 32-bit comparator-circuit layout has been treated using SysRel for electromigration circuit-level reliability analyses for Cu and Al technologies. A jmax value of 0.96 MA/cm2 and a T of 105 ◦ C were used. The total dynamic power reported in Synopsys Design Analyzer using library cell characterizations is 26.6 mW at Vdd = 5 V. While the signal lines in the design are stressed with bidirectional currents, the Vdd and Gnd lines have the worst case unidirectional current density of 0.42 MA/cm2 . Table II shows the simulation results for Cu technology. Fig. 5 shows the layout after the final simulation step when the mortal trees are marked. According to the analysis, Vdd and Gnd rings in metal1 and metal2 are prone to electromigration failure. Step 4 in Table II shows the lifetime of each unit. The

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Fig. 6. Layout technique for Al polygranular to bamboo-type conversion in an interconnect line. TABLE IV FULL-CHIP RELIABILITY ANALYSIS WITH 64-BIT ALU IN D IFFERENT M ETALLIZATION T ECHNOLOGIES

Fig. 5. Layout view of the 32-bit comparator with mortal Vdd and Gnd lines marked. TABLE III ELECTROMIGRATION ANALYSIS FOR Al TECHNOLOGY IN A 32- BIT C OMPARATOR L AYOUT

worst lifetime of 23.2 years is due to a via-above-type Cu line in metal 1. Increasing the linewidth of those four lines from 2.5 to 5 µm and running the reliability simulation again, SysRel predicts a lifetime improvement from 23.2 to 92.9 years and the overall reliability metrics are t50 of 37.5 years, FIT of 563, and probability of survival of 0.98. Table III shows reliability-simulation results with the 32-bit comparator layout for Al technology. The same interconnect trees in Vdd and Gnd rings, as shown in Fig. 5, are mortal in Al technology. However, the lifetime of each unit is now only 4.39 years, due to the 2.5-µm wide Al polygranular-type lines in the power-delivery rings. Using a track-layout method with narrow (0.5 µm) metal lines, as shown in Fig. 6, we can convert the mortal lines in the power-supply rings from polygranular to bamboo type. Using such a technique, the lifetime of each metal line can be improved to 306.82 years and the overall reliability metrics are a t50 of 99.8 years, an FIT of 5.9, and probability of survival is 0.99. Therefore, the best reliability can be achieved with Al bamboo-type interconnects in the circuit layout. IX. C IRCUIT -L EVEL R ELIABILITY R EQUIREMENTS A significantly larger circuit, a 64-bit arithmetic and logic unit (ALU), has also been analyzed using SysRel, for the same layout with different metallization technologies to investigate reliability requirements in Cu metallization. The ALU circuit

is laid out in a 1036 µm × 1035 µm area using five layers of metal routing. The circuit consumes 2.129 W of power and has a maximum current density of 0.46 MA/cm2 in the powerdelivery lines. SysRel reports 89 176 interconnect trees in the layout. With Cu/SiO2 -based interconnect technology, 81 619 trees are first identified to be “immortal” using the ( jmax L) filter. Another 6415 trees are filtered out using the ( jL)eff filter. Only 1142 trees are reported to be mortal in Cu/SiO2 based interconnect technology. Table IV illustrates reliabilitysimulation results with different metallization technologies in the ALU layout. The worst case interconnect temperature of 105 ◦ C and full-chip target lifetime of 20 years were used in the simulations. Due to the higher ( jL) product thresholds for immortality in Al metallization, only 179 trees are identified as mortal. Consistent with our previous analysis, full-chip reliability is the best with Al bamboo interconnects and worst with Al polygranular interconnects, even without layout modifications. The lower ( jL) product thresholds in Cu/SiO2 -based interconnects result in a larger fraction of the interconnect trees being subject to electromigration-induced failure, and consequently results in a lower relative reliability at circuitlevel than at the test-device level. To decrease interconnect delay, a wide range of materials with a low dielectric constant, generally referred to as low-k dielectrics, are being investigated as replacements for SiO2 . Lower ( jL) product thresholds are observed for such interlayer dielectric (ILD) materials [24], [25]. Using a lower ( jL)

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Fig. 8. Median-time-to-failures of a straight-line test-structure and various circuits with different interconnect-metallization technologies.

Fig. 7. Maximum failure rate of the 64-bit ALU circuit with a Cu/low-k interconnect system as a function of jL threshold for immortality.

immortality threshold of 700 A/cm, we observe 2739 mortal trees (Table IV) in the ALU circuit, leading to a still further reduction in the full-chip reliability. Hau–Riege et al. reported some critical material parameters from electromigration experiments on straight line via-to-via Cu interconnects with a particular low-k dielectric material, as shown in the last row of Table IV [24], [26]. Using the threshold jL determined for this material, this low-k material in the 64-bit ALU leads to still lower chip-level reliability. The lower critical stress for void nucleation and lower effective-modulus also reduces the expected lifetime of mortal trees. Both effects contribute to the worst case full-chip reliability predictions for this particular Cu/low-k material shown in the last row of Table IV. Low dielectric constant materials have correspondingly low elastic moduli, and therefore lower effective moduli B and threshold jL product [21]. Fig. 7 illustrates the impact of decreasing threshold jL products on the circuit-level reliability of systems with low-k dielectrics. As summarized in Fig. 8, we therefore see that even when the test-level reliability of Cu is superior to Al bamboo, Al bamboo is superior at service conditions, and still better when characterized in circuits. The advantage of Al bamboo increases in larger circuits of greater complexity. Cu must therefore have a significantly better test/device-level reliability to have the same circuit-level reliability as Al with bamboo structure. The above analysis shows the impact of material and process parameters on full-chip reliability. The reverse is also possible in SysRel and particularly useful for predicting material and process parameters required to achieve desired full-chip reliability. Results from such analysis can aid process and reliability engineers in setting goals for improving test-level reliability. We have conducted similar studies with the 64-bit ALU circuit to investigate the required Cu atomic diffusivity, a parameter that can be controlled during process development, for example using capping layers other than Si3 N4 [16], [27]. The full-chip reliability goal is set to the best case probability of 0.994 of no failure within the target lifetime achieved with

Al bamboo-type interconnects. Our simulations indicate that Cu diffusivity needs to be reduced by approximately 12 times to achieve the equivalent reliability with Cu/SiO2 -based interconnects. With Cu/low-k interconnects, the required improvement in atomic diffusivity is even higher. A factor of 44 decrease in Cu atomic diffusivity is required with Cu/low-k interconnects to achieve the same reliability in the 64-bit ALU, as would be achieved with Al bamboo-type interconnects. Use of Cobalt Tungsten Phosphide (CoWP) capping layers have been reported to lead to an activation energy (Ea ) of 1.22 eV [16], which significantly reduces the atomic diffusivity at service conditions. Using Ea = 1.2 eV in SysRel, we predict a full-chip probability of no failure of 1 within the target lifetime of 20 years for the 64-bit ALU circuit with both Cu/SiO2 and Cu/low-k-based interconnect systems. X. NON-BLOCKING VIAS IN Cu INTERCONNECTS As liner thicknesses are decreased in future technology, the liners at vias are more likely to be discontinuous, or to rupture due to electromigration stresses, so that all vias may not be fully blocking for electromigration. Hu et al. carried out electromigration experiments with different liner thicknesses and blocking materials at the cathode and anode ends [28]. The study demonstrated that in the specific test structure used, a 3-nm-thick liner can lead to an increase in median-timeto-failure by more than an order of magnitude. Wei et al. conducted electromigration experiments with straight-line viato-via Cu dual-damascene test-structures connected to bond pads [9]. A few long lines tested at high current density never failed, even though analytically computed mechanical stress values in the lines were easily high enough for void nucleation. It was postulated that the apparent immortality of a subpopulation of the long lines was the result of stress-induced ruptures of the Ta liners at the vias. In a test-structure, liner ruptures would allow continuous flow of Cu to and from the lead lines and contact pads, which serve as large sinks and reservoirs for Cu atoms. Therefore, the liner ruptures would cause high lifetime or immortality in simple test structures. To investigate the impact of nonblocking vias on circuit-level reliability, we have added nonblocking-via analysis capabilities in SysRel.

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TABLE V FULL-CHIP RELIABILITY SIMULATION WITH NONBLOCKING VIAS IN THE 32-BIT COMPARATOR LAYOUT

Fig. 9. Illustration of interconnect tree merging in a three-input NAND gate. (a) There are eight trees in the layout. (b) The number of trees decreases to three with nonblocking vias, but the average tree length increases. The longest tree paths are marked in the layouts.

Users can stochastically or deterministically assign nonblocking vias in a circuit layout. W-filled vias for source/drain/ gate and substrate contacts in Cu metallization technology are rigid and always treated as blocking. Multiple trees, when linked by nonblocking metal-to-metal vias, are merged to create a single tree, which is then treated as the fundamental reliability unit. Merging interconnect trees connected by a nonblocking via often increases the effective length, Lmax (equivalently, the longest distance between blocking vias). Fig. 9 illustrates the effect of tree merging in a threeinput NAND gate with metal routing at the output. Total number of trees decreases due to tree merging and the longest effective length in the layout also increases. The increase in effective line length can influence the outcome of immortality condition filters based on ( jL) products. Multiple trees that would be immortal with blocking vias can be linked to form mortal trees. However, two or more mortal trees can be linked to form a single mortal tree with a longer effective length. The latter effect results in an overall reduction in the number of mortal trees, as illustrated for a 32-bit comparator circuit layout in Table V. The default model presented in Section V for estimating the lifetime of a mortal tree assumes semi-infinite segment lengths. Therefore, there is a predicted reliability improvement with nonblocking vias. However, if the impact of effective line length is taken into account (e.g., the lifetime to be inversely proportional to line length), the full-chip reliability would degrade (Table V). The impact of nonblocking vias depends on how reliability depends on length, and how nonblocking vias affect the line

Fig. 10. Test-structure for investigating the line-length dependence on reliability in the presence of nonblocking vias.

length dependence of reliability. SysRel simulation results with the 32-bit comparator circuit demonstrate the critical need for understanding and accurately modeling the line-length dependence on reliability. We have proposed the development and use of long multiple-metal-level test structures (Fig. 10) with nonblocking vias for intermetal connections and blocking vias at the ends [29]. If reliability is indeed a strong function of line length, the circuit-level reliability requirement in Cu technology with nonblocking vias would be even more demanding. XI. C ONCLUSION The difference in interconnect architectures for Al and Cu technologies leads to different failure mechanisms. Consequently, different reliability-assessment methodologies must be applied to Cu interconnects compared to Al interconnects. Unlike Al technology, a ( jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required in Cu interconnect trees. We have developed a set of methodologies for circuit-level reliability analysis with either Al or Cu metallization in the circuit layout. The methodologies are implemented in a public-domain reliability CAD tool, SysRel. Using data from the literature, as well as our own experimental work with Al and Cu/Si3 N4 interconnect systems, comparison of lifetime of a straight line interconnect shows that Al bamboo has the best lifetime in typical operating condition ( j < 0.5 MA/cm2 and T < 105 ◦ C) followed by Cu via-below, Cu via-above, and Al polygranular-type lines. SysRel has been used to compare circuit-level electromigration reliability for 32-bit comparator and 64-bit ALU circuit layouts with different technologies. The impact of nonblocking vias in Cu metallization with thin liners has also been

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investigated with the 32-bit comparator circuit. Considering Cu/Si3 N4 -based interconnect system, the best full-chip reliability is achieved with Al bamboo-type interconnects. To match the best case reliability, an improvement in test-level reliability is required in Cu. More importantly, the required improvement increases as low-k materials are introduced and liner thicknesses are reduced.

R EFERENCES [1] C. K. Hu, K. P. Rodbell, T. D. Sullivan, K. Y. Lee, and D. P. Bouldin, “Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines,” IBM J. Res. Develop., vol. 39, no. 6, pp. 465–497, 1995. [2] S. P. Hau–Riege, “New methodologies for interconnect reliability assessments of integrated circuits,” Ph.D. dissertation, Dept. Mater. Sci. Eng., Massachusettes Inst. Technol., Cambridge, Apr. 2000. [3] ——, “Probabilistic immortality of Cu damascene interconnects,” J. Appl. Phys., vol. 91, no. 4, p. 2014, 2002. [4] C. L. Gan, C. V. Thompson, K. L. Pey, W. K. Choi, H. L. Tay, B. Yu, and M. K. Radhakrishnan, “Effect of current direction on the lifetime of different levels of Cu dual-damascene metallization,” Appl. Phys. Lett., vol. 79, no. 27, p. 4592, 2001. [5] C. L. Gan, C. V. Thompson, K. L. Pey, W. K. Choi, F. Wei, B. Yu, and S. P. Hau–Riege, “Experimental characterization of the reliability of 3-terminal dual-damascene copper interconnect trees,” in Materials Research Society (MRS) Proc., San Francisco, CA, Spring 2002, vol. 716, p. 431. [6] C. S. Hau–Riege and C. V. Thompson, “The effects of microstructural transitions at width transitions on interconnect reliability,” J. Appl. Phys., vol. 87, no. 12, p. 8467, 2000. [7] K. D. Lee, E. T. Ogawa, H. Matsuhashi, P. R. Justison, K. S. Ko, and P. S. Ho, “Electromigration critical length effect in Cu/oxide dualdamascene interconnects,” Appl. Phys. Lett., vol. 79, no. 20, p. 3236, 2001. [8] E. T. Ogawa, A. J. Bierwag, K. D. Lee, H. Matsuhashi, P. R. Justison, A. N. Ramamurthi, and P. S. Ho, “Direct observation of a critical length effect in dual-damascene Cu/oxide interconnects,” Appl. Phys. Lett., vol. 78, no. 18, p. 2652, 2001. [9] F. Wei, C. L. Gan, C. V. Thompson, J. J. Clement, S. P. Hau–Riege, K. L. Pey, W. K. Choi, H. L. Tay, B. Yu, and M. K. Radhakrishnan, “Length effects on the reliability of dual-damascene Cu interconnects,” in Materials Research Society (MRS) Proc., San Francisco, CA, Spring 2002, vol. 716, p. 645. [10] R. G. Filippi, G. A. Biery, and R. A. Wachnik, “The electromigration short-length effect in Ti-AlCu-Ti metallization with tungsten studs,” J. Appl. Phys., vol. 78, no. 6, p. 3756, 1995. [11] C. K. Hu, R. Rosenberg, and K. Y. Lee, “Electromigration path in Cu thin-film lines,” Appl. Phys. Lett., vol. 74, no. 20, p. 2945, 1999. [12] Y. J. Park, V. K. Andleigh, and C. V. Thompson, “Simulations of stress evolution and the current density scaling of electromigration-induced failure times in pure and alloyed interconnects,” J. Appl. Phys., vol. 85, no. 7, p. 3546, 1999. [13] V. T. Srikar and C. V. Thompson, “Diffusion and electromigration of copper in SiO2 -passivated single-crystal aluminum interconnects,” Appl. Phys. Lett., vol. 74, no. 1, p. 37, 1999. [14] F. Wei, “The electromigration drift velocity and the reliability of dualdamascene copper of interconnect trees,” M.S. thesis, Dept. Mater. Sci. Eng., Massachusettes Inst. Technol., Cambridge, MA, 2003. [15] C. L. Gan, “Reliability assessment methodologies for copper-based interconnects in integrated circuits,” Ph.D. dissertation, Dept. Advanced Mater. for Micro- and Nano-System (AMM&NS) at the Singapore-MIT Alliance, Nat. Univ. Singapore, Singapore, 2003. [16] M. W. Lane, E. G. Liniger, and J. R. Lloyd, “Relationship between interfacial adhesion and electromigration in Cu metallization,” J. Appl. Phys., vol. 93, no. 3, p. 1417, 2003. [17] C. L. Gan, C. V. Thompson, K. L. Pey, and W. K. Choi, “Experimental characterization and modeling of the reliability of three-terminal dualdamascene Cu interconnect trees,” J. Appl. Phys., vol. 94, no. 2, p. 1222, 2003. [18] S. M. Alam, C. L. Gan, D. E. Troxel, and C. V. Thompson, “Circuit level reliability analysis of Cu interconnects,” in Proc. Int. Symp. Quality Electronic Design (ISQED), San Jose, CA, Mar. 22–24, 2004, pp. 238–243.

[19] SysRel: System-Level IC Reliability, Massachusetts Inst. Technol., Cambridge, MA, Sep. 2004. [Online]. Available: http://www-mtl.mit. edu/research/reliability/SysRel.html [20] “Interconnect chapter of the International Technology Roadmap for Semiconductors,” International Technology Roadmap for Semiconductors. [Online]. Available: http://public.itrs.net. [21] C. S. Hau–Riege, A. P. Marathe, and V. Pham, “The effect of line length on the electromigration reliability of Cu interconnects,” in Proc. Advanced Metallization Conf., San Diego, CA, 2002, p. 169. [22] J. A. Maiz, “Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents,” in Proc. 27th Int. Reliability Physics Symp., Phoenix, AZ, 1989, p. 220. [23] J. J. Clement, “Reliability analysis for encapsulated interconnect lines under dc and pulsed dc current using a continuum electromigration transport model,” J. Appl. Phys., vol. 82, no. 12, pp. 5991–6000, 1997. [24] C. S. Hau–Riege, A. P. Marathe, and V. Pham, “The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths,” in Proc. 41st Int. Reliability Physics Symp., Dallas, TX, 2003, pp. 173–177. [25] S. H. Kang, private communication, 2005. [26] C. S. Hau–Riege, S. P. Hau–Riege, and A. P. Marathe, “The effect of interlevel dielectric on the critical tensile stress to void nucleation for the reliability of Cu interconnects,” J. Appl. Phys., vol. 96, no. 10, p. 5792, 2004. [27] M. Hatano, T. Usui, Y. Shimooka, and H. Kaneko, “EM lifetime improvement of Cu damascene interconnects by p-SiC cap layer,” in Proc. Int. Interconnect Technology Conf. (IITC), San Francisco, CA, 2002, pp. 212–214. [28] C. K. Hu, L. Gignac, S. G. Malhotra, R. Rosenberg, and S. Boettcher, “Mechanisms for very long electromigration lifetime in dual-damascene Cu interconnects,” Appl. Phys. Lett., vol. 78, no. 7, p. 904, 2001. [29] S. M. Alam, F. L. Wei, C. L. Gan, C. V. Thompson, and D. E. Troxel, “Impact of non-blocking vias on electromigration and circuit-level reliability assessments of Cu interconnects,” in Proc. Advanced Metallization Conf., San Diego, CA, Oct. 2004, p. 233. [30] S. P. Hau–Riege and C. V. Thompson, “The effects of the mechanical properties of the confinement material on electromigration in metallic interconnects,” J. Mater. Res., vol. 15, no. 8, p. 1797, 2000.

Syed M. Alam (M’04) received the B.S. degree in electrical engineering from the University of Texas, Austin, in May 1999, and the S.M. and Ph.D. degrees in electrical engineering and computer science from Massachusetts Institute of Technology, Cambridge, in June 2001 and September 2004, respectively. He is currently a Senior Staff Design Engineer at Freescale Semiconductor, Austin, TX. His research interests include three-dimensional (3-D) integrated circuits (ICs), reliability computer-aided design (CAD), thermal analysis in ICs, and signalintegrity analysis. He has several publications including an invited tutorial on interconnect reliability at ICCAD and patents pending on 3-D IC technology. Dr. Alam is a full member of the Sigma Xi Scientific Research Society.

Chee Lip Gan (S’99–M’03) received the B.Eng. degree in electrical engineering from the National University of Singapore, Singapore, on June 1999, and the Ph.D. degree in advanced materials for microand nanosystems from the Singapore–Massachusetts Institute of Technology Alliance in June 2003. He is currently an Assistant Professor in the School of Materials Engineering at Nanyang Technological University, Singapore. His research interests include reliability of advanced interconnect systems, 3-D interconnects, and nanointerconnects. Prof. Gan is a Member of the Executive Committee of the Singapore IEEE (Rel/CPMT/ED) Chapter.

ALAM et al.: CIRCUIT-LEVEL RELIABILITY REQUIREMENTS FOR Cu METALLIZATION

Frank L. Wei received the B.S. degree in chemical engineering from the University of California, Berkeley, in 2000, and the S.M. degree in materials science and engineering from Massachusetts Institute of Technology (MIT), Cambridge, in 2003. He is currently pursuing the Ph.D. degree in materials science and engineering at MIT, Cambridge. He has research interests on the effects of mechanical properties of interconnect systems on interconnect reliability and the development of a circuit-level reliability-assessment simulation tool. Mr. Wei is a full member of the Sigma Xi Scientific Research Society and the Materials Research Society.

Carl V. Thompson (SM’95) received the S.B. degree in materials science and engineering from Massachusetts Institute of Technology, Cambridge, in 1976, and the S.M. and Ph.D. degrees in applied physics from Harvard University, Cambridge, MA, in 1977 and 1982, respectively. He is the Stavros Salapatas Professor of Materials Science and Engineering in the Department of Materials Science and Engineering at the Massachusetts Institute of Technology, Cambridge. He has authored or coauthored more than 300 research publications on the material science and engineering of thin films and micro- and nanostructures. Specific current interests include processing, materials selection, and design for improved reliability in advanced IC metallization; the origin and control of residual stress in thin films; and assembly of systems of nanoscale materials.

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Donald E. Troxel (S’55–M’57–SM’75–LSM’97) received the B.S. degree in electrical engineering from Rutgers University, New Brunswick, NJ, in 1956. He received the S.M. and Ph.D. degrees in electrical engineering from Massachusetts Institute of Technology (MIT), Cambridge, in 1960 and 1962, respectively. He has been at MIT since 1962, first as a Ford Foundation Postdoctoral Fellow, Assistant Professor, Associate Professor, Professor of Electrical Engineering, and now as Professor Emeritus. His teaching activities have centered around undergraduate electronics and digital systems laboratories. Dr. Troxel’s principal research interests include digital systems design and reliability of integrated circuits. Early research interests were concerned with tactile communication, sensory aids for the blind, optical character recognition, picture processing, image-bandwidth compression, graphic-arts applications, and computer-aided fabrication of integrated circuits. He has also been a Consultant to various companies. Dr. Troxel is a Member of the Association for Computing Machinery (ACM). He is also a Member of the honorary societies Tau Beta Pi, Eta Kappa Nu, Sigma Xi, and Pi Mu Epsilon.