International Journal of Electronics Vol. 95, No. 9, September 2008, 879–889
CMOS CCII– based on modified dual output-OTA for high frequency applications H.J. Motlak* and S.N. Ahmad Department of Electronics and Communication Engineering, F/o Engineering and Technology, Jamia Millia Islamia, New Delhi, India (Received 12 September 2007; final version received 21 June 2008) A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (73 dB BW), 1.8 ns settling time, 48 V/ms slew rate, and low power consumption around 3.25 mW for +2.5 V supply. P-Spice simulation results are included for 0.5 mm MIETEC CMOS technology. Keywords: analogue circuit design; current conveyors; high frequency applications
1.
Introduction
An analogue circuit design using the current-mode approach has recently gained considerable attention (Bodur, Kuntman and Cicekoglu 2004, Mahmoud 2006). This stems from the inherent advantages of DO-OTA circuit such as wide bandwidth, high slew rate, low power consumption and simple circuitry (Chang and Liao 2002; Ergun and Kuntman 2005). Furthermore, current-mode circuits are suitable for integration with CMOS technology and thus have become more and more attractive in electronic circuit design in recent years (Wang and Lee 2000). At present, a number of current-mode circuits are realised using integrated circuits (ICs) such as current conveyors (CCs), operational transconductance amplifiers (OTAs), current feed-back amplifiers (CFAs) and current followers (CFs) (Drakakis and Karybakas 1999; Tsukutani, Edasaki, Sumi and Fukui 2006; Noulis, Deradonis and Siskos 2007). Second generation current conveyors (CCIIs) have found wide use in a variety of realisations of active network elements and currentmode circuits (Schmid and Moschytz 1997; Toker, Cicekoglu, Ozcan and Kuntman 2001). For voltage-mode circuits, the input and output variables are voltages; whereas in currentmode circuits these quantities are selected as current. The classical voltage amplifier with its high input impedance and low output impedance is a suitable element for voltage-mode circuits (Wang and Lee 2000). The current conveyor, however, with its one high impedance (ideally infinite) input, one low impedance (ideally zero) input and one high
*Corresponding author. Email:
[email protected] ISSN 0020-7217 print/ISSN 1362-3060 online Ó 2008 Taylor & Francis DOI: 10.1080/00207210802312146 http://www.informaworld.com
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impedance output is suitable element for both voltage-mode and current-mode circuits (Wang and Lee 2000). The operational transconductance amplifier (OTA) is an important building block in analogue signal processing applications (Zhang, Maundy, ElMasry and Finvers 2000). Many techniques used to maximise the bandwidth of second generation current conveyors have been published (Alves and Aguiar 1999; Zhang et al. 2000; Alves and Aguiar 2001; Barthelemy, Fillaud, Bourdel and Gaubert 2006; Hassan and Soliman 2006). A new CMOS realisation of an operational transconductance amplifier is based on the cross-coupled configuration and is biased by common-mode voltage. The circuit used to realise CCII is proposed by Zhang et al. (2000). Class AB CMOS CCII using some modifications to improve bandwidth and a differential CMOS CCII based buffer stage to implement controlled low input impedance using a feedback loop with a variable resistance between Z and Y terminals are proposed in Alves and Aguiar (1999, 2001). The configuration by Hassan and Soliman (2006) uses an additional source follower section at the input stage to achieve wideband and high accuracy of CMOS CCII. A new versatile class AB CCIIþ using six digital CMOS inverters to improve the performance of CCIIþ in high frequency operation is proposed by Barthelemy et al. (2006). A novel class AB CMOS CCII based on a novel high-performance voltage follower topology is proposed by Calvo, Celma, Martinez and Sanz (2003). A new wide range CMOS differential voltage current conveyor (DVCC) using two wide linear range transconductors at the input stage and a class AB CMOS push–pull network at the output stage to guarantee high current driving capability is proposed by Mahmoud (2008). The properties of the nullor and mirror elements are used to relate the different devices in the ideal case as well as to define the adjoint network for each building block. Two new types of second generation current conveyors (CCII) are obtained by taking adjoint of CCII by Awad (1999). These CMOS realisations are based on voltage-tocurrent-mode transformation on CCIIþ and CCII–, namely negative inverting second generation current conveyor (ICCII-) and positive second generation current conveyor (ICCII+). A new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance mode is presented by Barthelemy, Fillaud, Bourdel and Gaubert (2007). A new circuit element referred to as an operational conveyor comprising an operational amplifier and a current conveyor is proposed by Gift (2005). In this communication, a high-performance negative second generation current conveyor (CCII–) based on folded cascode CMOS DO-OTA is proposed. The primary advantages of a dual output folded cascode CMOS OTA are enhanced frequency response, improved settling time and reduced power dissipation. This new CMOS DO-OTA based CCII– exhibits wide bandwidth, high slew rate, high output impedance, low power consumption and high linearity which are the inherent attractive features of the folded cascode DO-OTA. Measurement results for 0.5 mm CMOS implementation are included. 2.
Design of Dual-Output Folded Cascode CMOS OTA (CMOS DO-OTA)
Figure 1 shows the architecture of an operational transconductance amplifier (OTA) called dual-output folded cascode CMOS DO-OTA. This OTA uses cascoding in the output stage combined with an unusual implementation of the differential amplifier to achieve good input common-mode range. Thus, the folded cascode OTA offers self-compensation, good input common-mode range and the gain of a two-stage OTA (Allen and Holberg 2002). The CMOS DO-OTA does not require perfect balance of currents in the differential
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Figure 1.
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Circuit schematic of CMOS DO-OTA.
amplifier because excess dc current can flow into or out of the current mirror. Because the drains of M1 and M2 are connected to the drains of M5 and M6, the positive input common-mode voltage of Figure 1 is achieved (Allen and Holberg 2002). The specifications for the CMOS DO-OTA shown in Figure 1 are: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10)
Open loop gain ¼ 70 dB. Biasing current ¼ 100 mA. Supply requirements are +2.5 V. Unity gain bandwidth ¼ 10 MHz. Slew rate ¼ 10 V/ms. Phase margin ¼ 608. Input common mode range ¼ þ2V, 71.5 V. Output voltage swing ¼ +2 V. Load capacitor ¼ 10 pF. Power dissipation ¼ 5 mW.
When the bias current and overdrive voltage of each transistor is known, we can easily determine the aspect ratios from the following equation: ID ¼ ð1=2ÞmCOX ðW=LÞðVGS VTH Þ2
ð1Þ
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To minimise the device capacitances, we choose the minimum channel length for each transistor, obtaining a corresponding gate width. The design has thus far satisfied the output swing, power dissipation and supply voltage specifications (Rosenfeld, Kozak and Friedman 2004). Let us now calculate the maximum output voltage swing of the CMOS DO-OTA in Figure 1, where M5-M10 represents current sources with proper choice of Vb1 and Vb2, the lower end of the swing is given by Lower end swing ¼ VSS þ VOD3 þ VOD5
ð2Þ
Upper end swing ¼ VDD ðVOD5 þ VOD3 þ ðjVOD7 þ VOD9 jÞ:
ð3Þ
and the upper end by
The small-signal voltage gain of CMOS DO-OTA is given by: jAv j ¼ Gm Rout
ð4Þ
where Gm and Rout represents the overall transconductance and output resistance of CMOS DO-OTA, respectively. The output short-circuit current is approximately equal to the drain current of M1 because the impedance seen looking into the source of M3, that is, (gm3 þ gmb3)–1//rO3 is typically much lower than rO1//rO5. Thus, Gm gm1. And Rout ROP ==½ðgm3 þ gmb3 ÞrO3 ðrO1 ==rO5 Þ
ð5Þ
It follows from Rosenfeld et al. (2004) that jAv j gm1 ½½ðgm3 þ gmb3 ÞrO3 ðrO1 ==rO5 Þ==½ðgm7 þ gmb7 ÞrO7 rO9
ð6Þ
The frequency response of the folded-cascode OTA in Figure 1 is determined primarily by the output dominant pole which is given by Allen and Holberg (2002) as: pout ¼
1 Rout Cout
ð7Þ
where Cout is the total capacitance connected from the output of the OTA to ground. The success of the output pole being dominant depends on the fact that there are no other poles whose magnitude is less than GBW which is given as: GBW ¼
gm1;2 CL
ð8Þ
where gm1,2 represent the input transconductance of folded-cascode OTA. Equation (8) indicates that we can increase the value of GBW by decreasing the value of load capacitor CL with save the value of phase margin in acceptable value. Other method of increasing the value of GBW by increase the value of input transconductance gm1,2. The drawback pffiffiffiffiffiffiffiffi of this method is increasing in power consumption because of the expression gm a Ibias , so that we apply the first method in proposed design to increase GBW without increasing power consumption.
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The non-dominant poles are located at node A and B which are given as: pA;B ¼
gm3;4 Cp
ð9Þ
where gm3,4 is the transconductance of the common gate transistors (M3,M4), and Cp is the total parasitic capacitance at the source of the common gate transistors (Allen and Holberg 2002). The slew rate of OTA is given as: SR ¼
Ibias CL
ð10Þ
where Ibias represents the bias current. The power supply rejection ratio of the folded-cascode OTA has been greatly improved over the two-stage op-amp. The negative power-supply ripple is transferred directly to the gates of M11, M7, M8, M9 and M10. Here a slightly different approach is made to calculate the PSRR. In this case, we find the transfer function from the ripple to the output rather than the PSRR. For good PSRR, this transfer function should be small. The transfer function Vout/Vss can be found as: Vout sCgd8 Rout Vss sCout Rout þ 1
ð11Þ
The positive power-supply injection is similar to the negative power supply injection and the ripple appears at the gates of M5, M6, M3 and M4.The primary source of injection is through the gate-drain capacitor of M4, which is the same situation as for the negative power supply injection (Allen and Holberg 2002). 2.1. Common-Mode Feedback Circuit (CMFB) In high-gain amplifiers, the output common mode (CM) level is quite sensitive to device properties and mismatches and it cannot be stabilised by means of differential feedback. Thus, a common-mode feedback network must be added to sense the CM level of the two outputs and accordingly adjust one of the bias currents in the OTA. The technique of comparing the measured CM level with a reference and returning the error to the OTA’s bias network is applied (Rosenfeld et al. 2004). The CMFB circuit connected to the current sources of OTA suffers from several drawbacks. First, the value of the output CM voltage level is a function of device parameters. Second, the voltage drop across output resistors of CMFB circuit limits the output voltage swings. To minimise this voltage drop, MOS transistors should work in triode region which represents the output resistors of CMFB with high aspect ratio. The capacitive effect of CMFB of OTA in high frequency operation is thus neutralised (Rosenfeld et al. 2004). A modification to the previous technique which makes the output level relatively independent of device parameters and lowers the sensitivity to the value of biasing voltage of tail current source transistor is introduced here. The idea is to define biasing voltage of tail current source by a current mirror arrangement such that Ibias11 ‘‘track’’ I12 and VREF of CMFB circuit. For simplicity, we suppose that (W/L)11 ¼ (W/L)12 and (W/L)CM3,4 ¼ (W/L)CM1,2. Thus, Ibias11 ¼ Ibias only if Vout,CM ¼ VREF. In other words, the circuit produces an output CM level equal to a reference but it requires no resistors in sensing Vout,CM (Rosenfeld et al. 2004).
884 2.2.
H.J. Motlak and S.N. Ahmad Biasing Circuit
In the OTA circuit of Figure 1, the input CM level and the bias voltages must be chosen so as to allow maximum output swing, where M5–M10 represent the ideal current sources. Thus, the peak-to-peak swing on each side is equal to VDD 7 (VOD3 þ VOD5 þjVOD7jþjVOD9j). We should nonetheless note that, carrying a large current, M5 and M6 may require a high overdrive voltage if their capacitance contribution to nodes A and B is not to be minimised. The supply voltages VDD and VSS of the proposed design are +2.5 V. We assume that the values of overdrive voltages of each transistor as follows: VOD1,2 ¼ 0.16 V, VOD3,4 ¼ 0.3 V, VOD5,6 ¼ 0.5 V, VOD7,8,9,10 ¼ 0.225 V and VOD11,12 ¼ 0.5 V. The minimum allowable CM level equals VGS1 þ VOD11 ¼ VTH1 þ VOD1 þ VOD11 ¼ 1.42 V. The minimum value of Vb1 is Vb1 ¼ VSS þ VGS7 þ VOD9 ¼71.43 V. Similarly, Vb2, Vb4 and Vb3 are given as Vb2 ¼ VDD7(jVGS3j þ jVOD5j) ¼ 1.12 V, Vb4 ¼ VG9 ¼ VGS97VS9 ¼ VOD9 þ VTH97VSS ¼71.7 V and Vb3 ¼ VG5 ¼ VGS57VS5 ¼VDD7 VOD5 þ VTH5 ¼ 1.42 V. We can use simple voltage divider circuit to produce these voltages (Razavi 2002), where VOD1, VOD5, VOD9 and VOD11 represents over drive voltages of M1, M5, M9 and M11, respectively. VDD and VSS represent the supply voltage. Table 1 presents gate dimension and biasing currents of CMOS OTA. 3.
Realization of CMOS CCII– Based on CMOS DO-OTA
Sedra, Roberts and Gohh (1990) suggested the alternative ways of realising a negative current conveyor. For example, a CCII– can be approached quite closely by replacing the fully differential op-amp with a floating VCVS of large gain, or alternatively, with a floating VCCC of large transconductance. In this article, a simple CMOS CCII– is proposed which is suitable for high frequency applications. The negative output terminal of a CMOS DOOTA is connected to positive input terminal of DO-OTA to achieve a negative second generation current conveyor realised by CMOS technology as described in Figure 2. The CCII is a three-terminal device with a characteristic matrix given by Eq. (8). X and Y are the current and voltage input terminals, respectively. Z is the current output terminal. The ‘+’ sign in the characteristics matrix determines whether the conveyor is formulated as a non-inverting or inverting circuit: CCIIþ or CCII–, respectively (Zhang et al. 2000). 2 3 2 32 3 IY 0 0 0 VY 4 VX 5 ¼ 4 1 0 0 5 4 IX 5 ð12Þ 0 1 0 IZ YZ Table 1.
Gate dimension and biasing currents of CMOS DO-OTA.
Transistors no. M1, M2 M3, M4 M5, M6 M7, M8, M9, M10 M11, M12 Mcm1, Mcm2, Mcm3, Mcm4
W (mm)
L (mm)
Biasing current (mA)
Overdrive voltage (V)
12.0 16.1 11.59 6.21 2.51 0.49
0.5 0.5 0.5 0.5 0.5 1.0
50.0 50.0 100.0 50.0 100.0 50.0
0.16 0.3 0.5 0.225 0.5 0.63
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Figure 2.
Block diagrams of CMOS CCII– based on a modified CMOS DO-OTA.
Figure 3.
Circuit schematic of CMOS CCII– based on a CMOS DO-OTA.
Table 2. GBW, DC gain, settling time and phase margin, of the CMOS DO-OTA with different values of CL. CL (pF) 10.0 8.0 6.0 4.0 2.0 1.0 0.5 0.1 0.05 0.035
DC gain (dB)
GBW
Phase margin (8)
Settling time (ns)
64.3 ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼
8.5 MHz 10.9 MHz 14.4 MHz 21.2 MHz 42.0 MHz 81.45 MHz 375.1 MHz 726.2 MHz 1.14 GHz 1.50 GHz
89.8 89.7 89.6 88.6 81.2 79.2 76.6 75.7 53.7 46.5
303.0 239.8 175.1 118.2 49.6 18.2 13.1 4.7 2.1 1.8
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Figure 4. (a) Frequency response of CMOS DO-OTA. (b) Step response of CMOS DO-OTA. (c). Plot of the transconductance of CMOS DO-OTA with frequency.
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Figure 5. (a) Frequency response of the voltage gain between terminals X and Y of the CMOS CCII–. (b) DC characteristics of voltage mode CMOS CCII–. (c) Frequency response of the voltage gain between terminals X and Z of the CMOS CCII– with gain defined by Rz/Rx. (d) DC characteristics of current mode CMOS CCII–.
The equivalent circuit of CMOS CCII– based on CMOS DO-OTA is illustrated in Figure 3. We note that the common-mode feedback circuit is removed from DO-OTA because of connected negative output terminal to positive input terminal of OTA. 4. Measurement Results of CMOS DO-OTA and CMOS CCII– Attractive features of dual output folded cascode CMOS DO-OTA for high frequency signal processing applications are presented. Table 2 and Figures 4a and b show that when the load capacitor CL of CMOS DO-OTA is decreased, the performance parameters such as gain bandwidth product (GBW), dc gain (DC Gain) and settling time are improved. Figure 4c depicts the overall variation of the transconductance Gm of DO-OTA with frequency. Figure 5a shows the frequency response (magnitude) of CMOS CCII– with high 73 dB (BW) around 1.37 GHz which is approximately equal to the gain bandwidth product (GBW) of CMOS DO-OTA. Figure 5b indicates the dc characteristics of CMOS CCII– from this curve and we note that there is a very good linearity of CMOS CCII– especially in the range between 70.5 V and 0.7 V. The voltage-mode frequency response in term of Rz/Rx is shown in Figure 5c. This response shows that the 73 dB (BW) of
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Table 3.
Summary results of the CMOS DO-OTA.
Parameters
CMOS DO-OTA in Figure 1
(DC) gain GBW Phase margin Slew rate (þ) Slew rate (7) Settling time Output swing HD3(1 Vpp@10 MHz)) Dynamic range PSRRþ PSRR7 Power consumption Die area
Table 4.
64.3 dB 1.5 GHz 46.58 48.4 V/mS 744.7 V/mS 1.8 ns þ2.1V,72.4V 725.9 dB 30.9 dB 74.0 dB 69.7 dB 3.25 mW 0.047 mm2
Performance parameters of the proposed CMOS CCII–.
Parameters Voltage supply DC bias current Simulation in voltage – mode simulate at Y node Voltage gain Vx/Vy 73 dB bandwidth (BW) Vx-THD%@Vy ¼ 1Vpp (10 kO) Loading @X Simulation in current current-mode simulate at node X Rx Current gain Iz/Ix 73 dB bandwidth Iz THD% @ Ix ¼ 100 mA pp
Proposed CMOS CCII–in Figure 3 +2.5 V 100 mA 0.999 1.37 GHz 0.9% 3.9 kO 0.987 1.3 GHz 1%
CMOS CCII– is less than 73 dB (BW) in voltage-mode which is about 1.3 GHz. In addition to these high-performance parameters of CMOS CCII–, there is a very small current error between Ix and Iz shown in the Figure 5d. Table 4 summarises the performance parameters of CMOS CCII– in both voltage-mode and current-mode as well. (See Figure 4, Figure 5, Table 2, Table 3, and Table 4.) 5.
Conclusions
A new CMOS CCII– based on high performance folded cascode CMOS DO-OTA is presented. The proposed CMOS CCII– circuit is suitable for high-frequency applications because of attractive features such as wide bandwidth in current as well as voltage mode, high slew rate, small settling time and low power consumption, it also provides good linearity. This circuit is very economical in the environments where OTAs and CCII+ are used together on the same chip. The DO-OTA circuit can be very easily converted into a CCII– or CCIIþ just by the connection shown in Figure 3. The common-mode feedback circuit connection is made in such a manner that it does not affect the high-frequency performance of the DO-OTA and thus of the CCII–.
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