CMOS Logic

CMOS Logic INEL 4207 - Fall 2011 - Set 2

Wednesday, September 7, 11

Figure 14.17 The CMOS inverter.

Microelectronic Circuits, Sixth Edition


Sedra/Smith

Copyright © 2011 by Oxford University Press, Inc.

Figure 14.18



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Figure 14.19



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Figure 14.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.



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Qn and Qp are matched: kn = kp Use Vtn = Vtp = Vt .

VIH Qp is in saturation, Qn is in triode region.


iDp

=

iDn

=

(VDD

vi

kp (VDD 2 kn 2 (vi 2

vi

2

Vt )

Vt ) vO

Vt )2 = 2 (vi

2 vO

Vt ) vO

2 vO

2(VDD

vi

Vt ) = 2vO + 2 (vi vO = VIH

(VDD

VIH

Vt )2 = 2 (VIH

VIH


vO Vt ) vi

2vO

vO vi

VDD 2

✓

Vt ) VIH

1 = (5VDD 8

VDD 2 2Vt )

◆

✓

VIH

VDD 2

◆2

Use symmetry on VTC VIH VIL

VDD VDD = 2 2

VIL

1 = (3VDD + 2Vt ) 8

1 N MH = (3VDD + 2Vt ) = N ML 8


p If Qn and Qp are not matched: r = kn /kp VM kp (VDD 2 VDD

VM

kn + Vtp ) = (VM 2 2

VM + Vtp = r (VM

Vtn )2 Vtn )

VDD + Vtp + rVtn = VM (1 + r) VM


VDD + rVtn = 1+r

|Vtp |

Figure 14.21



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Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.



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Approach from Secs. 10.2.3/4.10 5th edition Using piecewise integration

tP HL = tP LH =


kn0 kp0

1.6C W L n VDD 1.6C W V L p DD

2nd approach using ave. current

Discharge tP HL

=

iav

=

iDN (E)

=

iDN (M )

=

tP HL

=

n

=


C

(VDD /2)

VDD

iav

=

CVDD 2iav

1 (iDN (E) + iDN (M )) 2 ✓ ◆ 1 0 W (VDD Vtn )2 kn 2 L n ✓ ◆ 1 0 W k (VDD Vtn )VDD 2 n L n nC

kn0

W L n

7 4

3Vtn VDD

VDD 2 ⇣ ⌘2 tn + VVDD

✓

VDD 2

◆2 !

Equivalent to eq. 10.18 on 5th ed. but more general

Charging tP LH = p

=

pC

kp⇥

W L p VDD

2 7 4

3|Vtp | VDD

+

⇣

tP HL + tP LH tp = 2 Wednesday, September 7, 11

Vtp VDD

⌘2

Another Alternative Approach

Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter. Microelectronic Circuits, Sixth Edition


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3rd Alternative approach

tP HL = 0.69RN C tP LH = 0.69RP C Empirical expressions 12.5 RN = k (W/L)n 30 RP = k (W/L)p These apply for several CMOS processes including 0.25µm, 0.18µm and 0.13µm. Wednesday, September 7, 11

Logic Gates

Sec. 10.3 in 5th edition

Figure 14.28 Examples of pull-down networks.



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C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw

Cg3,g4 = (W L)3,4 Cox + Cgsov3,gsov4 + Cgdov3,gdov4

Sec. 10.2.3 in 5th ed.

f14.24 Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.



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Cgd1,2, Cgsov3,4 and Cgdov3,4 are overlap capacitances

Figure 14.25 The Miller multiplication of the feedback capacitance Cgd1.



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Example: CMOS 0.25μm process with Cox = 6fF/μm2, μnCox = 115μA/V2, μpCox = 30μA/V2, Vtn = - Vtp = 0.5V, and VDD = 2.5V. (W/L)n = 0.375μm/0.25μm, (W/L)p = 1.125μm/0.25μm Cgd, Cgsov, Cgdov 0.3fF/μm×W Cdbn = Cdbp = 1fF , CW= 0.2fF Find tp when the inverter is driving an identical inverter.


Example: CMOS 0.25μm process with Cox = 6fF/μm2, μnCox = 115μA/V2, μpCox = 30μA/V2, Vtn = - Vtp = 0.5V, and VDD = 2.5V. (W/L)n = 0.375μm/0.25μm, (W/L)p = 1.125μm/0.25μm Cgd, Cgsov, Cgdov 0.3fF/μm×W Cdbn = Cdbp = 1fF , CW= 0.2fF Find tp when the inverter is driving an identical inverter. C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw

Cg3,g4 = (W L)3,4 Cox + Cgsov3,gsov4 + Cgdov3,gdov4

Cg3=(0.375)(0.25)(6fF) + (0.3fF)(0.375)×2=0.7875fF Cg4=(1.125)(0.25)(6fF) + (0.3fF)(1.125)×2=2.3625fF C=2(0.3fF)(0.375)+2(.3fF)(1.125)+1fF×2+0.7875fF+2.3625fF +0.2fF = 6.25fF αn = 1.7, tPHL = 24.6ps, tPLH = 31.5ps, tp = 28ps


Inverter Sizing C = Cint + Cext Increasing W/L by a factor S increases Cint C = SCint0 + Cext and decreases Req = (RN + RP )/2 by S with respect to the original Req0 . tp = 0.69

✓ ✓

Req0 S

◆

(SCint0 + Cext )

1 = 0.69 Req0 Cint0 + Req0 Cext S


◆

Example: If the inverter in the previous example, find (a) Cint and Cext, (b) factor S to reduce extrinsic part of tp by 2, (c) resulting tp, and (d) factor by which the area is increased. Ans. (a) 2.9fF, 3.35fF; (b) 2; (c) 20.5ps; (d) 2.


Ipeak

µn Cox = (W/L)n 2

✓

f14.26

Figure 14.26 The current in the CMOS inverter versus the input voltage.


VDD 2

Vtn

◆2